JPS6381948A - 多層配線半導体装置 - Google Patents

多層配線半導体装置

Info

Publication number
JPS6381948A
JPS6381948A JP61227252A JP22725286A JPS6381948A JP S6381948 A JPS6381948 A JP S6381948A JP 61227252 A JP61227252 A JP 61227252A JP 22725286 A JP22725286 A JP 22725286A JP S6381948 A JPS6381948 A JP S6381948A
Authority
JP
Japan
Prior art keywords
layer
region
electrode
high melting
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61227252A
Other languages
English (en)
Other versions
JPH039616B2 (ja
Inventor
Kazuo Endo
遠藤　和夫
Takashi Kimura
隆 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61227252A priority Critical patent/JPS6381948A/ja
Publication of JPS6381948A publication Critical patent/JPS6381948A/ja
Priority to US07/420,727 priority patent/US5087578A/en
Publication of JPH039616B2 publication Critical patent/JPH039616B2/ja
Granted legal-status Critical Current

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    • H01L23/4827—Materials
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の目的１ （産業上の利用分野） この発明は、多層配線を有する半導体装置に係わるもの
で、特に素子上ボンディングを用いる多層配線半導体装
置に関する。
（従来の技術） 一般に、この種の半導体装置においては、素子上ボンデ
ィングを行なうために、半導体基板上に形成される配線
領域の平坦化技術が必要となる。
このような平坦化技術として側壁法と呼ばれる方法が知
られており、バイポーラトランジスタに適用すると第３
図（ａ）〜（ｄ）に示すような製造工程となる。すなわ
ち、まず、（ａ）図に示すようにコレクタａ域となるＮ
型半導体基板１１の表面領域にベース領域としてのＰ型
不純物拡散領域１２を形成した後、このＩＮ域１２の表
面領域にエミッタ領域となるＮ型不純物拡散領域１３を
形成する。そして、上記半導体基板１１上の全面にアル
ミニウム層を形成し、バターニングを行なって上記ベー
ス領域１２およびエミッタ領域１３上にそれぞれ第１層
目の電ｗ１１４．１５を形成する。その後、上記半導体
基板１１上の全面にＣＶＤ−８ｉ　０２１１１６を成長
形成する。次に、反応性イオンエツチングを行なって上
記ＣＶＤ−３ｉ０２膜１６を除去し、上記電極１４、１
５ノ側壁部に−（７）ミｃＶＤ−８ｉ　０２１１１６を
残存させる。その後、上記半導体基板１１上に再びＣＶ
Ｄ−８ｉ　０２１１１７を堆積形成する（（ｂ）図）。
次に、上記電極１４．１５上の上記ＣＶＤ−８ｉ０２膜
１７にそれぞれコンタクトホール１８．１９を形成した
後、全面にアルミニウム層を形成してバターニングを行
なうことにより第２層目の電１１ｉ２０．２１を形成す
る（（Ｃ）図）。次に、上記ＣＶＤ−８ｉＯ２膜１１お
よび第２層目の電極２０．２１上に保護膜２２を形成し
、上記電極２０．２１上に開孔２３．２４を形成してこ
れらの電極２０．２１の表面を露出させる。そして、ボ
ンディングワイヤ２５．２６で上記第２層目の電極２０
．２１上にボンディングを行ない、ベースおよびエミッ
タを導出する。なお、コレクタは、上記半導体基板１１
の裏面から導出する。
しかし、上記のような構成では、第１層目の電極１４．
１５の側壁部に残存されるＣＶＤ−８ｉ０２１１１１７
のばらつきが大きく、第２層目の電極２０．２１の形成
時に下地状態の相違に起因するアルミニウム層の膜質の
変化によりマイグレーションが発生し易くなる。このた
め、フンタクト部の信頼性が低下する欠点がある。また
、能動領域上に直接ボンディング領域を形成した場合に
は、下地である第１！ｌｌ目の電極が硬度の低いアルミ
ニウムで形成されているため、ボンディング時に層間絶
縁膜であるＣＶＤ−８ｉ０２膜１７にクラックが発生し
易くなる。
（発明が解決しようとする問題点） 上述したように、従来の多層配線半導体装置では、平坦
化工程が複雑でかつ安定性が悪く、信頼性が低い欠点が
ある この発明は上記のような事情に鑑みて成されたもので、
その目的とするところは、配線領域の平坦化工程を簡単
化かつ安定化でき、信頼性を向上できる多層配線半導体
装置を提供することである。
［発明の構成］ （問題点を解決するための手段と作用）すなわち、この
発明においては、上記の目的を達成するために、第１Ｗ
！１目の電極を高融点金属あるいはそのシリサイドで形
成し、この第１！１目の電極上にＢＰＳＧＩＩＩを形成
した後、熱処理を施して平坦化させ、上記第１層目の電
極上の上記ＢＰＳＧＩＩにコンタクトホールを形成し、
このコンタクトホールを介して上記第１層目の電極と接
続される第２１ｉ目の電極を形成する。そして、この第
２層目の電極にワイヤボンディングを行なうようにして
いる。
（実施例） 以下、この発明の一実施例について図面を参照して接続
する。第１図（ａ）〜（Ｃ）は、製造工程を順次示す断
面図で、まず、（ａ）図に示す如くコレクタ領域となる
Ｎ型半導体基板２７の表面領域にベース領域としてのＰ
型不純物拡散領域２８を形成した後、このｆｌｉＲ２Ｂ
の表面領域にエミッタ領域となるＮ型不純物拡散領域２
９を形成する。次に、上記半導体基板１１上の全面に高
融点金属、例えばＭｏ、Ｗ、Ｔｉあるいはこれらの高融
点金属のシリサイドＭｏＳｉ、ＷＳｉ、ＴｉＳｉからな
る金属層を形成し、バターニングを行なって上記ベース
領域２８およびエミッタ領域２９上にそれぞれ第１層目
の電極３０．３１を形成する。その後、上記半導体基板
１１上の全面にＢＰＳＧＩＷ３２を成長形成する。次に
、上記半導体基板１１に１０００℃程度の温度で熱処理
を施し、非晶質な上記高融点金属層３０．３１を再結晶
化するとともに、上記ＢＰＳＧ１１３２の溶融を行なう
。これによって、上記ＢＰＳＧ膜３２は平坦化される。
その後、上記第１層目の電極３０．３１上の上記ＢＰＳ
Ｇ膜３２にコンタクトホール３３．３４を開孔すると（
ｂ）図に示すようになる。次に、上記ＢＰＳＧＩ１３２
上の全面にアルミニウム層を形成し、バターニングを行
なって第２層目の電極３５．３８を形成する。次に、上
記ＢＰＳＧ膜３２および上記層Ｉｌ！３５．３６上に保
護膜３７を形成し、上記電極３５．３６上の上記保護１
１３７に開孔３８．３９を形成してこれらの電極３５．
３６の表面を露出させた後、ボンディングワイヤ４０．
４１でボンディングを行なってエミッタおよびベースを
導出する。なお、コレクタは上記半導体基板２７の裏面
から導出する。
このような構成によれば、第１層目の電極として高融点
金属層（あるいは高融点金属のシリサイド層＞　３０．
３１を用いているので高温での熱処理が可能であり、こ
の高融点金属層３０．３１上にＢＰＳＧ１３２を設けて
熱処理を施すことによりこのＢＰＳＧ膜３２を溶融させ
て表面を平坦化できる。そして、上記ＢＰＳＧａ３２の
平坦化のための熱処理の際、上記高融点金属層３０．３
１の再結晶化を行なう。
上記ＢＰＳＧｌ＄３２中のリンは、アルカリイオンに対
して阻止作用を持っているので、素子特性の安定化に寄
与する。また、上記ＢＰＳＧＩＩ３２中のボロンは、ガ
ラスのｍｍｍ震度引き乍げる作用を持っているので、Ｂ
ＰＳＧＩＩ３２は例えばＰＳＧＩＩ！よりも比較的低温
で溶融し、平坦化が容易である。
さらに、第１層目の電極３０．３１として用いた高融点
金属は、アルミニウムに比して硬いため、素子上でボン
ディングする時の圧力によって発生する１１１間絶縁膜
（ＣＶＤ−８ｉ　０２　！１３２）等ツクラックの発生
を抑制できる。
従って、製造工程の簡単化、信頼性の向上、および歩留
りの向上などが図れる。
なお、上記実施例では第１層目の電極として高融点金属
およびそのシリサイドを用いたが、第２図に示すように
、高融点金属層４２．４３とそのシリサイド層４４．４
５を積層形成すれば、シリサイド層を単体で使用した場
合よりも電極配線抵抗を低く設定できる。第２図におい
て、前記第１図（Ｃ）と同一構成部には同じ符号を付し
てその詳細な説明は省略する。なお、上記高融点金属層
とそのシリサイド層との積層構造は、上記第２図の構造
に限られるものではなく、他の積層構造であっても良い
のはもちろんである。
［発明の効果］ 以上説明したようにこの発明によれば、配線領域の平坦
化工程を簡単化かつ安定化でき、信頼性を向上できる多
層配線半導体装置が得られる。
【図面の簡単な説明】
第１図はこの発明の一実施例に係わる多層配線半導体装
置について説明するための図、第２図はこの発明の他の
実施例について説明するための図、第３図は従来の多層
配線半導体装置について説明するための図である。 ２７・・・Ｎ型半導体基板（コレクタ領域）、２８・・
・Ｐ型不純物拡散領域（ベース領域）、２９・・・Ｎ型
不純物拡散領域（エミッタ領域）　、３０．３１・・・
第１層目の電極、３２・・・ＢＰＳＧＩＩ！（絶縁膜）
　、　３３．３４・・・コンタクトホール、３５．３６
・・・第２層目の電極、３７・・・保護膜、４０．４１
・・・ボンディングワイヤ。 出願人代理人　弁理士　鈴江武彦 第１図

Claims (3)

    【特許請求の範囲】
  1. （１）半導体基体と、この半導体基体上に形成された、
    高融点金属層あるいは高融点金属のシリサイド層から成
    る第１層目の電極と、上記半導体基体上および上記第１
    層目の電極上に形成され、熱処理が施されて平坦化され
    る絶縁膜と、上記第１層目の電極上の上記絶縁膜上に形
    成されコンタクトホールを介して上記第１層目の電極と
    接続される第２層目の電極とを具備し、上記第２層目の
    電極にワイヤボンディングを行なうことを特徴とする多
    層配線半導体装置。
  2. （２）前記第１層目の電極は、高融点金属層と高融点金
    属のシリサイド層との積層構造を有することを特徴とす
    る特許請求の範囲第１項記載の多層配線半導体装置。
  3. （３）前記絶縁層は、ボロンとリンを含んだ酸化シリコ
    ンから成ることを特徴とする特許請求の範囲第１項記載
    の多層配線半導体装置。
JP61227252A 1986-09-26 1986-09-26 多層配線半導体装置 Granted JPS6381948A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61227252A JPS6381948A (ja) 1986-09-26 1986-09-26 多層配線半導体装置
US07/420,727 US5087578A (en) 1986-09-26 1989-10-11 Semiconductor device having multi-layered wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61227252A JPS6381948A (ja) 1986-09-26 1986-09-26 多層配線半導体装置

Publications (2)

Publication Number Publication Date
JPS6381948A true JPS6381948A (ja) 1988-04-12
JPH039616B2 JPH039616B2 (ja) 1991-02-08

Family

ID=16857902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61227252A Granted JPS6381948A (ja) 1986-09-26 1986-09-26 多層配線半導体装置

Country Status (2)

Country Link
US (1) US5087578A (ja)
JP (1) JPS6381948A (ja)

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Also Published As

Publication number Publication date
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JPH039616B2 (ja) 1991-02-08

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