JPS6366414B2 - - Google Patents

Info

Publication number
JPS6366414B2
JPS6366414B2 JP14559881A JP14559881A JPS6366414B2 JP S6366414 B2 JPS6366414 B2 JP S6366414B2 JP 14559881 A JP14559881 A JP 14559881A JP 14559881 A JP14559881 A JP 14559881A JP S6366414 B2 JPS6366414 B2 JP S6366414B2
Authority
JP
Japan
Prior art keywords
etching
solution
mixture
present
semiconductor crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14559881A
Other languages
Japanese (ja)
Other versions
JPS5848424A (en
Inventor
Hideto Furuyama
Yutaka Uematsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP14559881A priority Critical patent/JPS5848424A/en
Publication of JPS5848424A publication Critical patent/JPS5848424A/en
Publication of JPS6366414B2 publication Critical patent/JPS6366414B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 本発明は、InP半導体結晶のエツチング方法の
改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for etching InP semiconductor crystals.

近時、各種の半導体素子にGaP、GaAsおよび
InP等の−族化合物半導体が用いられてい
る。これらの化合物半導体はSiやGe等の族半
導体にない特殊な性質を有し、高速デバイス、セ
ンサデバイスおよび光デバイス等に極めて有効な
ものである。そして最近、上記した各種デバイス
の高性能化に伴いデバイス構造が複雑な形状を有
するようになり、それら形状の形成プロセス技
術、特にエツチングによる微細パターン形成技術
が要求されるに至つている。
Recently, GaP, GaAs and
- group compound semiconductors such as InP are used. These compound semiconductors have special properties not found in group semiconductors such as Si and Ge, and are extremely effective in high-speed devices, sensor devices, optical devices, and the like. Recently, as the various devices mentioned above have improved in performance, device structures have come to have complex shapes, and there has been a demand for process techniques for forming these shapes, particularly techniques for forming fine patterns by etching.

エツチングに必要なエツチング液は各種材料に
よつて異なるが、−族半導体、特にGaP、
GaAsおよびInP等にはBr2が有効である。また、
通常Br2はそのままでは非常に不安定であり、
CH3OH中に混入している場合が多い。Br2
CH3OHは半導体結晶の両方位性の表われ易いエ
ツチング液であり、メサエツチングや逆メサエツ
チング等に効果がある。
The etching solution required for etching differs depending on the material, but it
Br 2 is effective for GaAs, InP, etc. Also,
Normally Br 2 is very unstable as it is,
It is often mixed in CH 3 OH. Br2−
CH 3 OH is an etching solution that easily reveals bidirectional properties of semiconductor crystals, and is effective in mesa etching, reverse mesa etching, etc.

しかしながら、Br2−CH3OH混合液をエツチ
ング液として用いても、材料によつて両方位性が
表われ難い場合がある。特に、逆メサエツチング
の場合には、第1図に示す如く基板1上のウエス
ト部分2に第2図に示す如き逆メサ状のウエスト
形状が表われ難くなることがある。これは、エツ
チング形態が反応律速型ではなく、拡散律速型に
なつているためである。なお、上記問題は特に
InP半導体結晶のエツチングにおいて顕著であ
る。また、Br2−CH3OHに限らず、Br2
C2H5OH混合液をエツチング液として用いる場合
にあつても上記と同様の問題があつた。
However, even if a Br 2 --CH 3 OH mixture is used as an etching solution, it may be difficult to exhibit bidirectionality depending on the material. In particular, in the case of reverse mesa etching, an inverted mesa-like waist shape as shown in FIG. 2 may be difficult to appear on the waist portion 2 on the substrate 1 as shown in FIG. This is because the etching mode is not a reaction rate-limiting type, but a diffusion rate-limiting type. In addition, the above problem is especially
This is noticeable in the etching of InP semiconductor crystals. Moreover, not only Br 2 −CH 3 OH but also Br 2
The same problem as above occurred when a C 2 H 5 OH mixed solution was used as an etching solution.

本発明は上記事情を考慮してなされたもので、
その目的とするところは、Br2−CH3OH混合液
或いはBr2−C2H5OH混合液を用いてInP半導体
結晶をエツチングするに際し、両方位に依存した
エツチング形状を得ることができ、メサエツチン
グおよび逆メサエツチングに適したInP半導体結
晶のエツチング方法を提供することにある。
The present invention was made in consideration of the above circumstances, and
The purpose of this is to be able to obtain an etched shape that depends on both positions when etching an InP semiconductor crystal using a Br 2 --CH 3 OH mixture or a Br 2 --C 2 H 5 OH mixture; An object of the present invention is to provide a method for etching InP semiconductor crystals suitable for mesa etching and reverse mesa etching.

まず、本発明の概要を説明する。本発明者等
は、Br2−CH3OH混合液によるInP半導体結晶の
エツチングが常に反応律速型となるよう鋭意研究
を重ねた結果、上記混合液にH2Oを加えればよ
いことを見出した。さらに、Br2−C2H5OH混合
液の場合も同様であることを見出した。
First, an overview of the present invention will be explained. The present inventors conducted extensive research to ensure that the etching of InP semiconductor crystals using the Br 2 -CH 3 OH mixture is always reaction rate-limited, and as a result, they discovered that it is sufficient to add H 2 O to the above mixture. . Furthermore, it has been found that the same holds true for the Br 2 -C 2 H 5 OH mixture.

すなわち、本発明はBr2−CH3OH混合液或い
はBr2−C2H5OH混合液にH2Oを所定量加えたエ
ツチング液にて、InP半導体結晶をエツチングす
るようにした方法である。したがつて、エツチン
グ形態を反応律速型とすることができ、InP半導
体結晶をその両方位が表われ易い状態でエツチン
グすることができる。このため、メサエツチング
や逆メサエツチングを容易に行い得る等の効果を
奏する。
That is, the present invention is a method in which an InP semiconductor crystal is etched using an etching solution in which a predetermined amount of H 2 O is added to a Br 2 -CH 3 OH mixed solution or a Br 2 -C 2 H 5 OH mixed solution. . Therefore, the etching mode can be made reaction rate-limited, and the InP semiconductor crystal can be etched in a state where both positions are easily exposed. Therefore, effects such as mesa etching and reverse mesa etching can be easily performed.

以下、本発明の詳細を図面を参照して説明す
る。
Hereinafter, details of the present invention will be explained with reference to the drawings.

本発明者等がBr2−CH3OH混合液にH2Oを所
定量加えた溶液をエツチング液として用い、InP
半導体結晶基板の(100)面上に<110>方向のマ
スクを付けてエツチングを行つたところ、第3図
a〜dに示すエツチング形状が得られた。ここ
で、Br2は0.2〔%)で一定とし、H2Oの量を変え
てエツチングを行つた。第3図aはH2Oが0
〔%〕、bはH2Oが10〔%〕、cは15〔%〕、dは
H2Oが50〔%〕の場合である。これらから判るよ
うに、エツチングの形態が反応律速型か拡散律速
型かと云うことは、CH3OHに混合するH2Oの量
によつて決定することになる。したがつて、
H2Oの混合量を適当に定めることによつて、InP
半導体結晶基板3を逆メサ状にエツチングするこ
とが可能となる。
The present inventors used a solution in which a predetermined amount of H 2 O was added to a Br 2 -CH 3 OH mixture as an etching solution.
When etching was performed using a <110> direction mask on the (100) plane of the semiconductor crystal substrate, the etched shapes shown in FIGS. 3a to 3d were obtained. Here, Br 2 was kept constant at 0.2%, and etching was performed by changing the amount of H 2 O. In Figure 3 a, H 2 O is 0.
[%], b is H 2 O is 10 [%], c is 15 [%], d is
This is the case when H 2 O is 50 [%]. As can be seen from these, whether the etching mode is a reaction rate-limited type or a diffusion rate-limited type is determined by the amount of H 2 O mixed with CH 3 OH. Therefore,
By appropriately determining the amount of H 2 O mixed, InP
It becomes possible to etch the semiconductor crystal substrate 3 into an inverted mesa shape.

また、本発明者等の実験によれば、CH3OHに
対するH2Oの体積比が15〔%〕を越えるとエツチ
ング形態が反応律速型となり、15〔%)以上にお
いては拡散律速型から反応律速型への極端な変移
は見られなかつた。さらに、CH3OHに対する
H2Oの体積比が50〔%〕以上になると、Br2の蒸
発が多くなりエツチング液の寿命が短くなること
が判つた。このことから、CH3OHに対するH2O
の体積比を15〜50〔%〕に設定すればよいのが判
る。
Furthermore, according to experiments conducted by the present inventors, when the volume ratio of H 2 O to CH 3 OH exceeds 15 [%], the etching mode becomes a reaction rate-limiting type, and when the volume ratio exceeds 15 [%], the etching mode changes from a diffusion-limited type to a reaction rate-limiting type. No extreme shift to the rate-limiting type was observed. Furthermore, for CH 3 OH
It was found that when the volume ratio of H 2 O exceeds 50%, evaporation of Br 2 increases and the life of the etching solution becomes shorter. From this, H 2 O for CH 3 OH
It can be seen that it is sufficient to set the volume ratio of 15 to 50 [%].

かくして本発明によれば、Br2−CH3OH混合
液にH2Oを所定量加えたエツチング液を用い、
InP半導体結晶基板3をエツチングすることによ
り、基板3の逆メサ形状を制御性良く作成するこ
とができる。
Thus, according to the present invention, using an etching solution in which a predetermined amount of H 2 O is added to a Br 2 -CH 3 OH mixture,
By etching the InP semiconductor crystal substrate 3, the inverted mesa shape of the substrate 3 can be created with good controllability.

なお、上述した説明では逆メサ形状を作成する
例を示したが、順メサ形状の作成にも本発明を適
用できるのは勿論のことである。また、Br2
CH3OH混合液の代りにBr2−C2H5OH混合液を
用いても同様の結果が得られた。したがつて、
InP半導体結晶をエツチングするに際し、そのエ
ツチング液としてBr2−CH3OH混合液或いはBr2
−C2H5OH混合液にH2Oを所定量加えた溶液を用
いればよいことになる。その他、本発明はその要
旨を逸脱しない範囲で、種々変形して実施するこ
とができる。
In the above explanation, an example of creating an inverted mesa shape was shown, but it goes without saying that the present invention can also be applied to creating a forward mesa shape. Also, Br 2
Similar results were obtained when a Br 2 -C 2 H 5 OH mixture was used instead of the CH 3 OH mixture. Therefore,
When etching InP semiconductor crystal, Br 2 -CH 3 OH mixed solution or Br 2
A solution obtained by adding a predetermined amount of H 2 O to a −C 2 H 5 OH mixture can be used. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は拡散律速型のエツチング例を示す断面
図、第2図は反応律速型のエツチング例を示す断
面図、第3図a〜dは本発明の作用を説明するた
めのもので同図aは従来方法によるエツチング例
を示す断面図、同図b〜dは本発明方法によるエ
ツチング例を示す断面図である。 1…基板、2…ウエスト部分、3…InP半導体
結晶基板。
FIG. 1 is a sectional view showing an example of diffusion controlled etching, FIG. 2 is a sectional view showing an example of reaction controlled etching, and FIGS. 3 a to 3 d are for explaining the operation of the present invention. A is a sectional view showing an example of etching by a conventional method, and b to d of the same figure are sectional views showing an example of etching by the method of the present invention. 1...Substrate, 2...Waist part, 3...InP semiconductor crystal substrate.

Claims (1)

【特許請求の範囲】 1 Br2−CH3OH混合液或いはBr2−C2H5OH混
合液をエツチング液として用いInP半導体結晶を
エツチングするに際し、前記エツチング液に
H2OをCH3OH或いはC2H5OHに対して15〜50
〔%〕の体積比となるように加えエツチング形態
が反応律速型となるようにしたことを特徴とする
InP半導体結晶のエツチング方法。
[Claims] 1. When etching an InP semiconductor crystal using a Br 2 -CH 3 OH mixed solution or a Br 2 -C 2 H 5 OH mixed solution as an etching solution, the etching solution is
15-50 for H 2 O to CH 3 OH or C 2 H 5 OH
[%], and the etching form is reaction rate-limiting.
Etching method for InP semiconductor crystal.
JP14559881A 1981-09-17 1981-09-17 Etching method of inp semiconductor crystal Granted JPS5848424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14559881A JPS5848424A (en) 1981-09-17 1981-09-17 Etching method of inp semiconductor crystal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14559881A JPS5848424A (en) 1981-09-17 1981-09-17 Etching method of inp semiconductor crystal

Publications (2)

Publication Number Publication Date
JPS5848424A JPS5848424A (en) 1983-03-22
JPS6366414B2 true JPS6366414B2 (en) 1988-12-20

Family

ID=15388760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14559881A Granted JPS5848424A (en) 1981-09-17 1981-09-17 Etching method of inp semiconductor crystal

Country Status (1)

Country Link
JP (1) JPS5848424A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60172669A (en) * 1984-01-31 1985-09-06 株式会社トスカ Banding band
JP2677318B2 (en) * 1992-09-18 1997-11-17 竹内工業 株式会社 cable tie

Also Published As

Publication number Publication date
JPS5848424A (en) 1983-03-22

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