JPS63152162A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63152162A JPS63152162A JP30077886A JP30077886A JPS63152162A JP S63152162 A JPS63152162 A JP S63152162A JP 30077886 A JP30077886 A JP 30077886A JP 30077886 A JP30077886 A JP 30077886A JP S63152162 A JPS63152162 A JP S63152162A
- Authority
- JP
- Japan
- Prior art keywords
- mold layer
- semiconductor device
- resin mold
- recess
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 239000011347 resin Substances 0.000 claims abstract description 27
- 229920005989 resin Polymers 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にフラットパッケージタ
イプの半導体装置に係る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a flat package type semiconductor device.
半導体集積回路装置においては高密度実装を可能とする
ためにフラットパッケージ（以下ＦＰと略す）タイプの
ものが従来から知られている。第２図に示すようにＦＰ
タイプの半導体装置の外部リード２は樹脂モールド層ｌ
の底面と略同レベルまで曲げられ、かつその先端部はモ
ールド層１の底面と平行になっている。そして上記ＦＰ
タイプの半導体装置は第３図に示すようにプリント回路
板３の所定位置に外部リードの先端部を半田付して実装
される。2. Description of the Related Art Flat package (hereinafter abbreviated as FP) type semiconductor integrated circuit devices have been known to enable high-density packaging. FP as shown in Figure 2
The external leads 2 of this type of semiconductor device are made of a resin mold layer l.
It is bent to approximately the same level as the bottom surface of the mold layer 1, and its tip is parallel to the bottom surface of the mold layer 1. And the above FP
This type of semiconductor device is mounted by soldering the tips of external leads to predetermined positions on a printed circuit board 3, as shown in FIG.
上述した従来のＦＰタイプの半導体装置の実装に際して
は、デュアルーイ／−ラインパッケージ（ＤＩＰ）品の
ように外部リードの先端部をプリント回路の穴に挿入し
て実装することができないために、誤実装、逸脱等の問
題があった。When mounting the conventional FP type semiconductor device mentioned above, it is not possible to insert the tips of the external leads into the holes of the printed circuit unlike dual-line package (DIP) products, which can lead to incorrect mounting. There were problems such as deviations.
また、ＦＰタイプの半導体装置の樹脂モールド層＆てそ
の底面よりも下方に突出して位置決め用ガイドを設ける
ことにより実装を確実に行なう方法が考えられるが、こ
の場合は既存のプリント回路基板等の改造が必要となり
、保管する際には従来のマガジンケースが使用できない
などの欠点がある。Another possible method is to provide a positioning guide that protrudes below the resin mold layer and bottom of the FP type semiconductor device, but in this case, the existing printed circuit board, etc. must be modified. However, there are disadvantages such as the fact that conventional magazine cases cannot be used for storage.
上述した従来のＦＰタイプの半導体装置に対し、本発明
は樹脂モールド層の底面に位置決め用ガイドとして凹部
を穿設し、プリント回路基板に設けた位置決め用突起部
にはめ込むことによシ実装時における誤実装、逸脱等を
防止することができる。In contrast to the conventional FP type semiconductor device described above, the present invention provides a recessed portion as a positioning guide on the bottom surface of the resin mold layer, and is fitted into a positioning protrusion provided on a printed circuit board, thereby making it easier to use the recessed portion during mounting. Mis-implementation, deviation, etc. can be prevented.
またＦＰタイプの半導体装置の樹脂モールド層の底面に
突出して位置決め用ガイドを設けることにより実装を確
実に行なう方法忙比べると、突出した位置決め用ガイド
の場合、プリント回路基板には位置決め穴が必要である
のに対し、本発明のＦ Ｐタイプの半導体装置は通常の
プリント回路基板にも実装することが可能である。In addition, when compared to methods for ensuring reliable mounting by providing a positioning guide protruding from the bottom of the resin mold layer of an FP type semiconductor device, in the case of a protruding positioning guide, a positioning hole is required on the printed circuit board. On the other hand, the FP type semiconductor device of the present invention can also be mounted on a normal printed circuit board.
本発明のＦＰタイプの半導体装置は、内部に半導体チッ
プを封止した樹脂モールド層と、該樹脂モールド層内部
で前記半導体チップに接続され、かつ樹脂モールド層の
側面から外部に延出して樹脂モールド層の底面と略同レ
ベルまで折曲げられた外部リードを有し、前記樹脂モー
ルド層の底面に位置決め用ガイドとして凹部を有してい
る。The FP type semiconductor device of the present invention includes a resin mold layer in which a semiconductor chip is sealed, and a resin mold layer connected to the semiconductor chip inside the resin mold layer and extending outside from a side surface of the resin mold layer. It has an external lead bent to approximately the same level as the bottom surface of the layer, and a recessed portion as a positioning guide on the bottom surface of the resin mold layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（８）は本発明のＦＰ半導体装置を示す平面図で
あり、第１図（Ｂ）はその右側面図である。これらの図
において１は樹脂モールド層、２は外部リードである。FIG. 1(8) is a plan view showing the FP semiconductor device of the present invention, and FIG. 1(B) is a right side view thereof. In these figures, 1 is a resin mold layer and 2 is an external lead.
外部リード２は樹脂モールド１内部でその中に気密封止
された図示しない半導体チップと電気的に接続されてい
る。また、外部リード２は樹脂モールド層１の底面と略
同レベルまで曲げられ、その先端部はモールド層１の底
面と平行に折シ曲げられている。そして、樹脂モールド
層１の底面にはモールド成形によりガイド用の凹部３が
形成されている。The external leads 2 are electrically connected inside the resin mold 1 to a not-shown semiconductor chip hermetically sealed therein. Further, the external lead 2 is bent to approximately the same level as the bottom surface of the resin mold layer 1, and its tip portion is bent parallel to the bottom surface of the mold layer 1. A guide recess 3 is formed on the bottom surface of the resin mold layer 1 by molding.
上記構成から成るＦＰ半導体装置は、第２図に示すよう
にプリント回路板６に設けられた位置決め用突起に前記
樹脂凹部３をはめこんで実装される。The FP semiconductor device having the above configuration is mounted by fitting the resin recess 3 into a positioning projection provided on a printed circuit board 6, as shown in FIG.
この結果、従来のような実装時の位置ずれは完全に防止
され、確実かつ効率的な実装が可能となる。As a result, positional displacement during mounting, which is conventional, is completely prevented, and reliable and efficient mounting is possible.
〔実施例２〕
第５図は本発明の実施例２のＦＰ半導体装置の平面図で
ある。[Embodiment 2] FIG. 5 is a plan view of an FP semiconductor device according to Embodiment 2 of the present invention.
この実施例では、第１図（５）における位置決めガイド
用凹部３の数が２つであるのに対し、３つのガイド用凹
部２３を中心点に対し非対称形に配置しである。この実
施例では、ガイド用凹部の配置によりＦＰ半導体装置の
向きが一定に決まるため、過まって逆向きに実装するこ
とがなくなるという利点がある。In this embodiment, the number of positioning guide recesses 3 in FIG. 1(5) is two, but three guide recesses 23 are arranged asymmetrically with respect to the center point. In this embodiment, since the orientation of the FP semiconductor device is fixed depending on the arrangement of the guide recess, there is an advantage that there is no possibility of accidentally mounting the FP semiconductor device in the opposite direction.
以上説明したように、本発明は樹脂モールド層の底面に
位置決め用ガイドとして凹部を穿設し、プリント回路基
板側に設けた位置決め突起部にはめ込むことにより、高
精度かつ高率的に実装を行なうことができるＦＰタイプ
の半導体装置を提供できるものである。As explained above, in the present invention, a recess is formed in the bottom of the resin mold layer as a positioning guide, and the recess is inserted into the positioning protrusion provided on the printed circuit board side, thereby achieving high-precision and high-efficiency mounting. Accordingly, it is possible to provide an FP type semiconductor device that can perform the following steps.
第１図（５）は本発明のＦＰ半導体装置の平面図、第１
図（ロ）は第１図（５）の右側面図、第２図は第１図囚
、（ロ）のＦＰ半導体装置の実装形態を示す断面図、第
３図（５）は従来のＦＰ半導体装置の平面図、第３図（
Ｂｌは第３図（５）の右側面図、第４図は第３図（５）
。
但のＦＰ半導体装置の実装形態を示す断面図、第５図は
第２の実施例のＦＰ半導体装置の平面図。
１．１１．２１・・・・・・樹脂モールド層、２．１２
．２２・・・・・・外部リード、３．２３・・・・・・
位置決めガイド用凹部、４．１４・・・・・・プリント
配線、訃・・・・・位置決めガイド用突起部、６．１６
・・・・・・プリント回路基板。
弗Ｓ ス
第４図FIG. 1 (5) is a plan view of the FP semiconductor device of the present invention.
Figure (B) is a right side view of Figure 1 (5), Figure 2 is a cross-sectional view showing the mounting form of the FP semiconductor device in Figure 1 (B), and Figure 3 (5) is a conventional FP semiconductor device. Plan view of semiconductor device, Figure 3 (
Bl is the right side view of Figure 3 (5), Figure 4 is the right side view of Figure 3 (5)
. However, FIG. 5 is a cross-sectional view showing a mounting form of the FP semiconductor device, and FIG. 5 is a plan view of the FP semiconductor device of the second embodiment. 1.11.21...Resin mold layer, 2.12
．． 22...External lead, 3.23...
Recess for positioning guide, 4.14...Printed wiring, bottom...Protrusion for positioning guide, 6.16
...Printed circuit board. Figure 4
Claims (1)
脂モールド層内部で前記半導体チップに接続され、かつ
樹脂モールド層の側面から外部に延出して樹脂モールド
層の底面と略同レベルまで折曲げられた外部リードを有
し、前記樹脂モールド層の底面に位置決め用ガイドとし
て凹部を穿設したことを特徴とするフラットパッケージ
タイプの半導体装置。a resin mold layer in which a semiconductor chip is sealed; and a resin mold layer that is connected to the semiconductor chip inside the resin mold layer, extends outward from a side surface of the resin mold layer, and is bent to approximately the same level as the bottom surface of the resin mold layer. 1. A flat package type semiconductor device, characterized in that the resin mold layer has a recessed portion as a positioning guide in the bottom surface of the resin mold layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30077886A JPS63152162A (en) | 1986-12-16 | 1986-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30077886A JPS63152162A (en) | 1986-12-16 | 1986-12-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63152162A true JPS63152162A (en) | 1988-06-24 |
Family
ID=17888978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30077886A Pending JPS63152162A (en) | 1986-12-16 | 1986-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63152162A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19526511A1 (en) * | 1994-07-22 | 1996-01-25 | Mitsubishi Electric Corp | PCB mounting applications of an encapsulated semiconductor package |
| US6541311B1 (en) | 1998-04-06 | 2003-04-01 | Infineon Technologies Ag | Method of positioning a component mounted on a lead frame in a test socket |
-
1986
- 1986-12-16 JP JP30077886A patent/JPS63152162A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19526511A1 (en) * | 1994-07-22 | 1996-01-25 | Mitsubishi Electric Corp | PCB mounting applications of an encapsulated semiconductor package |
| US6541311B1 (en) | 1998-04-06 | 2003-04-01 | Infineon Technologies Ag | Method of positioning a component mounted on a lead frame in a test socket |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5781415A (en) | Semiconductor package and mounting method | |
| JP2885414B2 (en) | Semiconductor device, mounting method thereof, and electronic device | |
| JPS59161851A (en) | Electronic component parts | |
| JPS63152162A (en) | Semiconductor device | |
| JPS62118555A (en) | Integrated circuit package | |
| JPH05226803A (en) | Mounting circuit board | |
| KR100338225B1 (en) | Semiconductor device | |
| JPS61285739A (en) | High-density mounting type ceramic ic package | |
| JPH021829Y2 (en) | ||
| JP2521944B2 (en) | Integrated circuit package | |
| JPS60263448A (en) | Plastic ic package | |
| JPS62263666A (en) | Resin sealed type semiconductor package | |
| JPH0199245A (en) | Ic package | |
| JPS60245155A (en) | Plastic ic package | |
| JPS6032350A (en) | Stacked package type semiconductor device | |
| JPS614436U (en) | Packages for semiconductor devices | |
| JPS62262448A (en) | Semiconductor device and mounting thereof | |
| JPH05144998A (en) | Semiconductor package | |
| JPH0565171A (en) | Carrier taping packing of chip-shaped electronic parts and carrier tape | |
| JPH06334097A (en) | Electronic component package | |
| JPS63278355A (en) | Resin-sealed semiconductor device | |
| JPH02270354A (en) | Resin-sealed semiconductor device | |
| JPH06278392A (en) | Ic module and its production | |
| JPS58122755A (en) | Printed circuit board structure | |
| JPH02126617A (en) | Chip type capacitor |