JPS629642A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS629642A
JPS629642A JP60148908A JP14890885A JPS629642A JP S629642 A JPS629642 A JP S629642A JP 60148908 A JP60148908 A JP 60148908A JP 14890885 A JP14890885 A JP 14890885A JP S629642 A JPS629642 A JP S629642A
Authority
JP
Japan
Prior art keywords
semiconductor element
electrode
electrodes
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60148908A
Other languages
English (en)
Other versions
JPH0357618B2 (ja
Inventor
Kenzo Hatada
畑田　賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60148908A priority Critical patent/JPS629642A/ja
Priority to US06/877,967 priority patent/US4693770A/en
Priority to DE8686305067T priority patent/DE3686457T2/de
Priority to EP86305067A priority patent/EP0208494B1/en
Priority to KR1019860005412A priority patent/KR900008665B1/ko
Publication of JPS629642A publication Critical patent/JPS629642A/ja
Publication of JPH0357618B2 publication Critical patent/JPH0357618B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法に関し、特に半導体素
子等の高密度、薄型、小型の実装技術に関するものであ
る。
従来の技術 近年、ＩＣ，ＬＳＩ等の半導体素子は、各種の家庭電化
製品、産業用機器の分野、へ導入されている。これら家
庭電化製品、産業用機器は省資源化、省電力化のために
あるいは利用範囲を拡大させるために、小型化、ＷＩ型
化のいわゆるボータプル化が促進されてきている。
半導体素子においてもボータプル化に対応するために、
パッケージングの小型化、薄型化°が要求されてきてい
る。拡散工程、電極配線工程の終了したシリコンスライ
スは半導体素子単位のチップに切断され、チップの周辺
に設けられたアルミ電極端子から外部端子へ電極リード
を取出して取扱いやすくしまた機械的保護のためにパッ
ケージングされる。通常、これら半導体素子のパッケー
ジングには、ＤＩＬ、デツプキャリヤ、フリップチップ
、テープキャリヤ方式等が用いられているが、ＯＩＬ、
チップキャリヤの如きは半導体素子の電極端子から外部
端子へは直径２５〜３５μ−のＡｕまたはＡｌｌの極細
線で一本づつ順次接続するものである。このために、半
導体素子上の電極端子数が増大するにしたがい、接続の
箇所の信頼度は低下するばかりか、外部端子の数もこれ
にしたがって一定間隔で増大するため、パッケージング
の大きさも増大する。
メモリーやマイクロコンピュータ用のＬＳＩと連結して
いるｌ　１０（７）如きし８１では、機能数の増大とと
もに、電橋端子数も６０〜１００端子と著しく増大して
しまい、前述した如く、パッケージングの大きさは、わ
ずか数１ＯＮｌ’の半導体素子を取扱うのに数１００１
１と大きくなってしまう。このことは小型化、薄型化の
ｌｌ器の促進を防げるものであった。
これら半導体素子を高密度に小型、薄型に実装する方法
として、従来第３図（Ａ）（Ｂ）に示したような方法が
ある。第３１ｉｉ！Ｉ（Ａ）においては、配線パターン
１を有する配線基板２上に半導体素子３ａ、３ｂを固定
し、半導体素子３ａ　、３ｂのアルミ電極４ａ、４ｂと
配線パターン１とをＡＬＩもしくはＡｎの極［１１５で
接続するものである。
すなわち半導体素子３ａ　、３ｂを平面的に搭載し、極
細線５で接続する方法であって、この方法においては、
極Ｉｌｌ線５が半導体素子３ａ　、３ｂより高くなり、
薄型の実装が困難であるばかりか、接続のために半導体
素子３ａ　、３ｂのアルミ電極４ａ。
４ｂと配線パターン１とを含む領域を必要とし、平面的
な実装面積が増大し、小型化しにくいという欠点がある
。
また第３図（Ｂ）の方法は、半導体素子３ａ。
３ｂのアルミ電１ｉ４ａ　、４ｂ上に金属突起６ａ。
６ｂを形成し、これにフィルムリード７ａ、７ｂを接合
せしめ、配線基板２の配線パターン１と前記フィルムリ
ード７ａ、７ｂとを接続するものである。この方法は、
半導体素子３ａ、３ｂのアルミｉ！Ｉｆ１４ａ　、　４
ｂに金属突起６ａ、６ｂを形成するために、蒸着工程、
フォトリソ工程、エツチング工程、メッキ処理工程等を
必要とするため、半導体素子３ａ、３ｂの歩留りを低下
せしめるばかりか、実装コストを高くするものである。
また第３図＜Ａ）に示す方法と同じく、フィルムリード
７ａ、７ｂを配線パターン１に接合するための領域を必
要とするため、平面的な実装面積が増大し、小型化しに
くいという欠点があった。
発明が解決しようとする問題点 このように従来の方法においては、実装面積が増大し、
薄型・小型に実装する事が困難であるばかりか、実装コ
ストも増大するものであった。
本発明は上記従来の問題点を解消するもので、実装コス
トを安価にできると同時に、高密度に実装できる半導体
装置の製造方法を提供することを目的とする。
問題点を解決するための手段 上記問題点を解決するため、本発明の半導体装置の製造
方法は、第１の半導体素子の電極に、基板上に形成した
金属突起を転写・接合する工程と、前記第１の半導体素
子の電極に対向する電極を有する第２の半導体素子の電
極と前記第１の半導体素子の電極上の金属突起とを当接
して加圧・加熱する工程とを含み、前記金属突起を介し
て前記第１の半導体素子の電極と第２の半導体素子の電
極とを接合するものである。
作用 上記方法によれば、一括接合が、できるばかりか、両方
の半導体素子の電極間の接合を、端に金属突起のみを介
在させるだけで行なえるので、著しく簡便に接合できる
。
実施例 以下、本発明の一実施例を第１図〜第２図に基づいて説
明する。
第１図は本発明の一実施例における半導体装置の製造方
法の工程を説明する断面図で、１１は基板、１２は八〇
からなる金属突起物、１３．１４は半導体素子、１５．
１６は八ρからなる電極、１７は／ｌからなる外部接続
用電極である。
製造に際しては、先ず第１図（Ａ）に示すように、基板
１１と半導体素子１３とを、基板１１の金属突起物１２
と半導体素子１３の電極１５とが相対向するように位置
合わせする。そして金属突起物１２と電極１５とを当接
させ、加圧・加熱する。この加圧・加熱により、基板１
１上の金属突起物１２は半導体素子１３の電極１５上に
転写・接合される。ここで、Ａｕかうなる金属突起物１
２とＡｆｌからなる電極１５とは若干のＡｕ−Ａ１合金
で接合される。次に第１図（Ｂ）に示すように、半導体
素子１３と半導体素子１４とを、半導体素子１３の電極
１５に接合された金属突起物１２と半導体素子１４の電
極１６とが相対向するように位置合わせする。そして金
属突起物１２と電極１６とを当接させ、加圧・加熱する
。これにより、第１図（Ｃ）に示すように、半導体素子
１３の電極１５と半導体素子１４の電極１６とは、金属
突起物１２を介して互いにＡ１１−ＡＱ金合金より半導
体素子１４の外部接続用電極１１は、外部回路と接続す
るための電極である。
なお、半導体素子１３の電極１５に金属突起物１２を転
写・接合する場合、Ａｕ−／１合金を形成する代わりに
、電極１５の表面あるいは金属突起物１２の表面に尋電
性接着剤を塗布して、単に加圧あるいは若干の加熱で転
写・接合するようにしてしよい。
また、金属突起物１２を形成する基板１１は、第２図に
示す様に、例えば耐熱性ガラスやセラミック等の絶縁性
基板１８上に、Ｐ【もしくはＩＴＯＩＩ等の導電膜１９
を形成し、この上に５ｉ０２．５ｉｘＮ４あるいはポリ
イミド樹脂等の耐熱性１１１２Ｇを設け、半導体素子１
３の電極１５に対向した所定の位置に開孔２１を設けた
構成である。金属突起物１２は、Ｓ電９１１９を一方の
電極として電解メッキ法により５〜４０μ鰯の厚さに形
成されるものであり、突起物の材料は、半導体素子１３
．１４の電極材料と少なくとも合金を作りやすいか、も
しくは圧著しやすい材料で形成されるもので、ＣＬＩ　
、　ＡＩＪ　、半田、Ｎｌ　、ＡＱ等を用いてもよい。
ここで、１ｓ電躾１９であるｐｔやＩＴＯ膜は著しくメ
ッキ処理が容易で、金属突起物１２の剥離性が良好であ
る。
また半導体素子１３．１４は、例えばＳｉ　、　ＧａＡ
ｓ、ＩｎＰなどのいわゆる半導体基板であっても良いし
、抵抗やコンデンサを有する回路基板であってもよい。
また、電極１５．１６は一般的にはＡＱであるが、Ｃｕ
、Ａｕ、Ｎｉ等を用いても良い。半導体素子１３、１４
が８１基板で、電極１５．１６がＡＱで、金属突起物１
２がＡｕであれば、半導体素子１３．１４の電極１ｓ、
　１６１！１１の接合はＡＵ−ＡＱの合金で構成される
。また半導体素子１３．１４の電極１５．１６は、半導
体素子１３．１４の表面の全域に形成しても良いし、周
縁に形成しても良く、その平面寸法は５×５μｍ以上な
ら容易に形成できる。また接合を確実にするために、各
々の半導体素子１３．１４の表面は少なくとも平坦化す
る必要がある。
また半導体素子１３の電極１４に金属突起物１２を転写
・接合する条件は、２００〜４５０℃で、金属突起物１
２の平面寸法が２０Ｘ　２０μ論であれば、１個の金属
突起物１２当り１０〜７０Ｑである。また電極１５．１
６同士の接合条件は、３５０〜５００℃、１１ｍの金ｆ
１１突起物１２当り５０〜２ｏｏｇである。
このように本実施例によれば、半導体素子１３゜１４が
メモリーであれば、同−平ｒｌｉ′ｉ積で倍の容量を容
易に得る事ができるし、あるいはまた、半導体素子１３
．１４１７）一方がＩｎ　ｐ、Ｑａ　ＡＳ等で構成した
レーザー、ＬＥＤ等のチップで、他方がＳｉ基板からな
る前記チップの駆動回路であれば、これらチップと駆動
回路との異種の材料、機能を一体化でき、配線抵抗や接
続の損失を防止できる。また、ＥＬや液晶ディスプレイ
等の駆動回路に見られる様に、耐圧の高い素子とこれを
駆動する回路とを別々に１ＩＪＩＩＬ、、本実施例の方
法により接合すれば、歩回りを高く、安価にできる。
なお本実施例の方法により、１個の金属突起物１２当り
約１５１）以上の接合強度を得ることができた。
発明の効果 以上述べたごとく本発明によれば、半導体素子の電極に
何らの処理を施すことなく、簡便に電極同士を接合でき
、しかも良好な接合強度を得ることができ、したがって
安価で信頼性の高い、薄型、小型の半導体装置を得るこ
とができる。また、半導体素子を積層構造とし、しかも
外部回路との接続領域を必要としないので、実装平面積
を縮小できる。また、機能の異なる半導体素子同士を近
接して容易に接合できるので、新しい機能を有する付加
価値の高い半導体装置を形成できる。また、接続点数が
著しく少なく、かつ、接続が著しく短いので、高い信頼
性を得ることができ、材料コストが安価になる。
【図面の簡単な説明】
第１図（Ａ）〜（Ｃ）は本発明の一実施例における半導
体装置の製造方法の工程を示す断面図、第２図は同製造
方法に用いる基板の断面図、第３図（Ａ）（Ｂ）は各々
従来の半導体装置の実装状態を示すＩｌｉ面図である。 １１・・・基板、１２・・・金属突起物、１３．１４・
・・半導体素子、１５．１６・・・Ｔｉ機 代理人　　　森　　本　　義　　弘 第１図 １、！；、／ｌ−・・奄待

Claims (1)

    【特許請求の範囲】
  1. １、第１の半導体素子の電極に、基板上に形成した金属
    突起を転写・接合する工程と、前記第１の半導体素子の
    電極に対向する電極を有する第２の半導体素子の電極と
    前記第１の半導体素子の電極上の金属突起とを当接して
    加圧・加熱する工程とを含み、前記金属突起を介して前
    記第１の半導体素子の電極と第２の半導体素子の電極と
    を接合する半導体装置の製造方法。
JP60148908A 1985-07-05 1985-07-05 半導体装置の製造方法 Granted JPS629642A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP60148908A JPS629642A (ja) 1985-07-05 1985-07-05 半導体装置の製造方法
US06/877,967 US4693770A (en) 1985-07-05 1986-06-24 Method of bonding semiconductor devices together
DE8686305067T DE3686457T2 (de) 1985-07-05 1986-06-30 Verfahren zum herstellen eines halbleiterapparates mit zwei halbleiteranordnungen.
EP86305067A EP0208494B1 (en) 1985-07-05 1986-06-30 Method of fabricating a semiconductor apparatus comprising two semiconductor devices
KR1019860005412A KR900008665B1 (ko) 1985-07-05 1986-07-04 반도체장치의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60148908A JPS629642A (ja) 1985-07-05 1985-07-05 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS629642A true JPS629642A (ja) 1987-01-17
JPH0357618B2 JPH0357618B2 (ja) 1991-09-02

Family

ID=15463348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60148908A Granted JPS629642A (ja) 1985-07-05 1985-07-05 半導体装置の製造方法

Country Status (5)

Country Link
US (1) US4693770A (ja)
EP (1) EP0208494B1 (ja)
JP (1) JPS629642A (ja)
KR (1) KR900008665B1 (ja)
DE (1) DE3686457T2 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6311766A (ja) * 1986-06-30 1988-01-19 藤森工業株式会社 コンクリ−ト打設用型枠
JPH03194867A (ja) * 1989-12-22 1991-08-26 Sumitomo Metal Ind Ltd 電気的接続部材
JPH08227917A (ja) * 1994-12-22 1996-09-03 Toshiba Corp 半導体素子の実装構造、液晶表示装置及び半導体装置
US5821627A (en) * 1993-03-11 1998-10-13 Kabushiki Kaisha Toshiba Electronic circuit device
JP2006283366A (ja) * 2005-03-31 2006-10-19 Daiwa House Ind Co Ltd コンクリート型枠用板状透水材

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149432A (ja) * 1984-08-18 1986-03-11 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS63119552A (ja) * 1986-11-07 1988-05-24 Sharp Corp Ｌｓｉチツプ
JPS63160352A (ja) * 1986-12-24 1988-07-04 Semiconductor Energy Lab Co Ltd 半導体装置の実装方法
US4865245A (en) * 1987-09-24 1989-09-12 Santa Barbara Research Center Oxide removal from metallic contact bumps formed on semiconductor devices to improve hybridization cold-welds
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
DE3829538A1 (de) * 1988-08-31 1990-03-08 Siemens Ag Verfahren zum verbinden eines halbleiterchips mit einem substrat
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
US4979664A (en) * 1989-11-15 1990-12-25 At&T Bell Laboratories Method for manufacturing a soldered article
JPH03291947A (ja) * 1990-04-09 1991-12-24 Mitsubishi Electric Corp ハイブリッド型デバイス
KR930701561A (ko) * 1990-06-08 1993-06-12 게리 엘. 그리스울드 전자 용품용 재처리가능한 접착제
US5143785A (en) * 1990-08-20 1992-09-01 Minnesota Mining And Manufacturing Company Cyanate ester adhesives for electronic applications
JP2629435B2 (ja) * 1990-10-17 1997-07-09 日本電気株式会社 アレイ状光素子用サブ基板の作製方法
US5532031A (en) * 1992-01-29 1996-07-02 International Business Machines Corporation I/O pad adhesion layer for a ceramic substrate
US6714625B1 (en) 1992-04-08 2004-03-30 Elm Technology Corporation Lithography device for semiconductor circuit pattern generation
TW223184B (ja) * 1992-06-18 1994-05-01 Matsushita Electron Co Ltd
US5739053A (en) * 1992-10-27 1998-04-14 Matsushita Electric Industrial Co., Ltd. Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step
KR0129500B1 (en) * 1992-10-27 1998-04-06 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
US6741085B1 (en) 1993-11-16 2004-05-25 Formfactor, Inc. Contact carriers (tiles) for populating larger substrates with spring contacts
US7081938B1 (en) 1993-12-03 2006-07-25 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
US5532550A (en) * 1993-12-30 1996-07-02 Adler; Robert Organic based led display matrix
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
JP3402400B2 (ja) 1994-04-22 2003-05-06 株式会社半導体エネルギー研究所 半導体集積回路の作製方法
US6943764B1 (en) * 1994-04-22 2005-09-13 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for an active matrix display device
US5542174A (en) * 1994-09-15 1996-08-06 Intel Corporation Method and apparatus for forming solder balls and solder columns
US5567654A (en) * 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
US5579573A (en) * 1994-10-11 1996-12-03 Ford Motor Company Method for fabricating an undercoated chip electrically interconnected to a substrate
EP0886894B1 (en) * 1995-05-26 2005-09-28 Formfactor, Inc. Contact carriers for populating substrates with spring contacts
CA2156941A1 (en) * 1995-08-21 1997-02-22 Jonathan H. Orchard-Webb Method of making electrical connections to integrated circuit
JP2793528B2 (ja) * 1995-09-22 1998-09-03 インターナショナル・ビジネス・マシーンズ・コーポレイション ハンダ付け方法、ハンダ付け装置
JPH09152979A (ja) * 1995-09-28 1997-06-10 Matsushita Electric Ind Co Ltd 半導体装置
KR100438256B1 (ko) * 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 반도체장치 및 그 제조방법
US6404063B2 (en) 1995-12-22 2002-06-11 Micron Technology, Inc. Die-to-insert permanent connection and method of forming
US5686318A (en) * 1995-12-22 1997-11-11 Micron Technology, Inc. Method of forming a die-to-insert permanent connection
US5886414A (en) * 1996-09-20 1999-03-23 Integrated Device Technology, Inc. Removal of extended bond pads using intermetallics
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6271111B1 (en) 1998-02-25 2001-08-07 International Business Machines Corporation High density pluggable connector array and process thereof
WO1999066556A1 (de) * 1998-06-16 1999-12-23 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Vertikal integriertes mikroelektronisches system und verfahren zur herstellung
US6657313B1 (en) * 1999-01-19 2003-12-02 International Business Machines Corporation Dielectric interposer for chip to substrate soldering
JP2001144197A (ja) * 1999-11-11 2001-05-25 Fujitsu Ltd 半導体装置、半導体装置の製造方法及び試験方法
US6621168B2 (en) 2000-12-28 2003-09-16 Intel Corporation Interconnected circuit board assembly and system
JP2002289770A (ja) * 2001-03-27 2002-10-04 Nec Kansai Ltd 半導体装置
US6748994B2 (en) 2001-04-11 2004-06-15 Avery Dennison Corporation Label applicator, method and label therefor
AU2003255254A1 (en) 2002-08-08 2004-02-25 Glenn J. Leedy Vertical system integration
US7253517B2 (en) * 2003-10-28 2007-08-07 Raytheon Company Method and apparatus for combining multiple integrated circuits
JP5568979B2 (ja) * 2009-12-22 2014-08-13 住友電気工業株式会社 検出装置、受光素子アレイ、および検出装置の製造方法
JP5644286B2 (ja) * 2010-09-07 2014-12-24 オムロン株式会社 電子部品の表面実装方法及び電子部品が実装された基板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869471A (ja) * 1971-12-22 1973-09-20
JPS5317069A (en) * 1976-07-30 1978-02-16 Fujitsu Ltd Semiconductor device and its production

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4032058A (en) * 1973-06-29 1977-06-28 Ibm Corporation Beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads
US4273859A (en) * 1979-12-31 1981-06-16 Honeywell Information Systems Inc. Method of forming solder bump terminals on semiconductor elements
US4396140A (en) * 1981-01-27 1983-08-02 Bell Telephone Laboratories, Incorporated Method of bonding electronic components
JPS57152147A (en) * 1981-03-16 1982-09-20 Matsushita Electric Ind Co Ltd Formation of metal projection on metal lead
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US4585157A (en) * 1985-04-04 1986-04-29 General Motors Corporation Tape bonding of two integrated circuits into one tape frame

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869471A (ja) * 1971-12-22 1973-09-20
JPS5317069A (en) * 1976-07-30 1978-02-16 Fujitsu Ltd Semiconductor device and its production

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6311766A (ja) * 1986-06-30 1988-01-19 藤森工業株式会社 コンクリ−ト打設用型枠
JPH03194867A (ja) * 1989-12-22 1991-08-26 Sumitomo Metal Ind Ltd 電気的接続部材
US5821627A (en) * 1993-03-11 1998-10-13 Kabushiki Kaisha Toshiba Electronic circuit device
JPH08227917A (ja) * 1994-12-22 1996-09-03 Toshiba Corp 半導体素子の実装構造、液晶表示装置及び半導体装置
JP2006283366A (ja) * 2005-03-31 2006-10-19 Daiwa House Ind Co Ltd コンクリート型枠用板状透水材

Also Published As

Publication number Publication date
EP0208494B1 (en) 1992-08-19
US4693770A (en) 1987-09-15
EP0208494A2 (en) 1987-01-14
EP0208494A3 (en) 1988-08-24
DE3686457D1 (de) 1992-09-24
DE3686457T2 (de) 1993-02-11
KR900008665B1 (ko) 1990-11-26
KR870001663A (ko) 1987-03-17
JPH0357618B2 (ja) 1991-09-02

Similar Documents

Publication Publication Date Title
JPS629642A (ja) 半導体装置の製造方法
JP3186941B2 (ja) 半導体チップおよびマルチチップ半導体モジュール
US5654584A (en) Semiconductor device having tape automated bonding leads
US5904499A (en) Package for power semiconductor chips
KR100507300B1 (ko) 멀티칩 모듈 및 그 제조방법
US6627480B2 (en) Stacked semiconductor package and fabricating method thereof
JPH0332914B2 (ja)
JPH0448767A (ja) 樹脂封止型半導体装置
JPH06302653A (ja) 半導体装置
JPS59194460A (ja) 半導体装置
JPS6290937A (ja) 半導体装置の製造方法
US6575765B2 (en) Interconnect assembly for an electronic assembly and assembly method therefor
JP2004288815A (ja) 半導体装置及びその製造方法
JPH10340925A (ja) 半導体装置およびその製造方法
JPH04342148A (ja) テープキャリア
JPS61210649A (ja) 半導体装置の製造方法
JP2879503B2 (ja) 面実装型電子回路装置
JPH04291993A (ja) 薄膜ユニットの接合方法
JPS6091656A (ja) 半導体装置の製造方法
JPS6132560A (ja) 半導体装置
JPH02172245A (ja) 半導体装置
JPH1022329A (ja) 半導体装置
JPS5824014B2 (ja) 実装体の製造方法
JPS61212034A (ja) 半導体装置の製造方法
JPH03273655A (ja) 混成集積回路装置

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term