JPS6284665A - Television receiver - Google Patents
Television receiverInfo
- Publication number
- JPS6284665A JPS6284665A JP22514585A JP22514585A JPS6284665A JP S6284665 A JPS6284665 A JP S6284665A JP 22514585 A JP22514585 A JP 22514585A JP 22514585 A JP22514585 A JP 22514585A JP S6284665 A JPS6284665 A JP S6284665A
- Authority
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- Japan
- Prior art keywords
- signal
- circuit
- video signal
- image
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はテレビジョン受像機の画面に同時に２種類の画
像を映出できるテレビジョン受像機に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television receiver that can simultaneously display two types of images on the screen of the television receiver.
従来の技術
近年、テレビジョン画像の高解像度化高画質化が求めら
れ、走査線数が現行ＮＴＳＣ方式やＰＡＬ方式の約２倍
の走査線数を有し、周波数帯域を広帯域化して高解像度
化をはかり、かつ、アスペクト比を現行４：３よりも横
長な例えば５：３にしたテレビジョン方式が種々提案さ
れ、横長な表示部を有する受像機が実用化されている。Conventional technology In recent years, there has been a demand for higher resolution and higher quality television images, and the number of scanning lines is approximately twice that of the current NTSC and PAL systems, and the frequency band is widened to achieve high resolution. Various television systems have been proposed in which the aspect ratio is wider than the current 4:3, for example 5:3, and television receivers with horizontally long display sections have been put into practical use.
また、このようなアスペクト比５：３の横長の表示部を
用する受像機にアスペクト比４；３の現行テレビジョン
方式の画像をも表示出来る機能を有する受像機も提案さ
れている。ところがこの様な機能を有する受像機で現行
テレビジョン放送を受像し、第２図に示すように、アス
ペクト比６：３の表示部全体に表示すると、画像が歪む
という不都合（第２図ｂ）が生じる。そのため偏向電流
を制御して表示部の一部にアスペクト比４：３の画像を
表示することによって（第２図Ｃ）歪が生じないように
している。Moreover, a receiver that uses such a horizontally elongated display section with an aspect ratio of 5:3 has a function of displaying images of the current television format with an aspect ratio of 4:3. However, when current television broadcasts are received by a receiver with such functions and displayed on the entire display area with an aspect ratio of 6:3, as shown in Figure 2, the image becomes distorted (Figure 2b). occurs. Therefore, distortion is prevented by controlling the deflection current and displaying an image with an aspect ratio of 4:3 on a part of the display section (FIG. 2C).
ところがこの様に偏向電流を制御して歪を無くす方式の
受像機において、画面の一部に、別の画像を同時に表示
する、いわゆる親子画面の機能をさらに追加しようとす
ると、第２図ｄに示すように、子画像によって、親画像
が欠落するという不都合が生じる。However, when trying to add a so-called parent-child screen function that simultaneously displays different images on a part of the screen to a receiver that eliminates distortion by controlling the deflection current, the problem occurs as shown in Figure 2 (d). As shown, the child image causes the inconvenience that the parent image is missing.
さらに子画像は縮少表示するために、水平、垂直とも間
引かれるために画質が悪くなるという欠点を有している
。Furthermore, since the child images are displayed in a reduced size, they are thinned out both horizontally and vertically, resulting in poor image quality.
発明が解決しようとする問題点
そこで本発明は、現行テレビジョン方式（アスペクト比
４：３）よりも横長なアスペクト比（例えば５：３）の
表示部に、現行テレビジョン方式の画像を親子画面で表
示する際に、横長な表示部を有効に使用して子画像によ
って欠落する親画像部を最小にするとともに、親画像部
を倍速走査で表示し、子画像部を間引くことなく表示す
ることによって高画質な親子画像表示が出来る受像機を
提供することを目的とする。Problems to be Solved by the Invention Therefore, the present invention aims to display an image of the current television system on a display section with a wider aspect ratio (for example, 5:3) than the current television system (aspect ratio of 4:3) in a parent-child screen. To effectively use the horizontal display area to minimize the portion of the parent image that is lost due to the child image, and to display the parent image portion at double speed scanning without thinning out the child image portion. The purpose of the present invention is to provide a receiver capable of displaying high-quality parent-child images.
問題点を解決するための手段
本発明はアスペクト比ｃｏｄの表示部全体を倍速で走査
する偏向回路と、第１のテレビジョン信号を記憶する第
１の記憶装置と、第３のテレビジョン信号を記憶する第
２の記憶装置を備えたテレビジョン受像機である。Means for Solving the Problems The present invention includes a deflection circuit that scans the entire display section with an aspect ratio of cod at double speed, a first storage device that stores a first television signal, and a third television signal that stores a first television signal. The television receiver includes a second storage device for storing data.
作用
本発明は前記した構成によう、親画像部は倍速表示を行
ない、子画像部は間引くことなく表示を行なうことによ
シ画質劣化のない親子表示を行うとともに、横長な表示
部を有効に使用し、親画像の欠落を最小にしようとする
ものである。According to the above-described structure, the present invention displays the parent image area at double speed and displays the child image area without thinning out, thereby performing parent and child display without deteriorating the image quality and making the horizontally long display area effective. The purpose is to minimize the loss of the parent image.
実施例
第１図は本発明の一実施例におけるテレビジョン受像機
のブロック図を示すものである。第１図において、１と
２０は入力端子、２と２１は映像信号処理回路、３と２
２はム／Ｄ変換器、４と２３は記憶装置、６は切換回路
、６は１）／Ａ変換器、７はマトリックス、８は増幅回
路、９は偏向ヨーク、１０は陰極線管、１１と２４は同
期分離回路、１２は偏向回路、１３は制御回路、１４は
走査信号発生回路、１５は補間回路である。Embodiment FIG. 1 shows a block diagram of a television receiver in an embodiment of the present invention. In Fig. 1, 1 and 20 are input terminals, 2 and 21 are video signal processing circuits, and 3 and 2 are input terminals.
2 is a MU/D converter, 4 and 23 are storage devices, 6 is a switching circuit, 6 is a 1)/A converter, 7 is a matrix, 8 is an amplifier circuit, 9 is a deflection yoke, 10 is a cathode ray tube, 11 and 24 is a synchronization separation circuit, 12 is a deflection circuit, 13 is a control circuit, 14 is a scanning signal generation circuit, and 15 is an interpolation circuit.
ここで理解を容易とするために横長な表示部のアスペク
ト比として６：３．親子表示するテレビジョン信号とし
て４；３とする。またＮ＝２とし表示される子画面の大
きさは親画面のＡとして説明するが、本発明はこれらに
限定されるものではない。Here, for ease of understanding, the aspect ratio of the horizontally long display section is 6:3. The television signal for parent-child display is 4;3. Furthermore, although the size of the child screen displayed with N=2 will be described as A of the main screen, the present invention is not limited to this.
入力端子１に到来した親画像用の映像信号は、映像信号
処理回路２で輝度信号Ｙと色差信号Ｒ−Ｙ、Ｂ−Ｙに復
調された後、ム／Ｄ変換器３で各々デジタル映像信号に
変換される。さらに到来した映像信号は同期分離回路１
１にも供給され同期信号が分離される。同期分離回路１
１で分離された水平同期信号は受信した水平同期信号の
２倍の周波数の倍速水平同期信号を発生する走査信号発
生回路１４に供給される。走査信号発生回路１４の出力
信号は偏向回路１２を介して偏向ヨーク９に供給され、
陰極線管１０上に２倍の走査線数を有するラスターを形
成する。この時形成されたラスターは陰極線管１ｏの表
示面を完全に走査している。同時に前記同期信号は制御
回路１３にも供給されている。ム／Ｄ変換器３の出力の
ディジタル映像信号は制御回路１３よりの書き込み信号
により記憶装置４に書き込まれる。今仮りに第３図に示
すように親画像をアスペクト比５：３の表示面の右側に
寄せ、子画像を表示面の左下側に寄せて表示するとする
。この時記憶装置４からの読み出しは、第３図に示した
ように画面の右側に寄るような位相関係でかつ、画像の
歪みが生じないよう時間軸変換されて読み出される。記
憶装置４の動作について第４図を用いてもう少し詳しく
説明する。到来した映像信号（第４図＆）は画像信号期
間ｔの信号がｔ時間かかって記憶装置４に書き込まれる
。（第４図ｂ）読み出しは、前述したように２倍の走査
線数でラスターが形成されているので１水平走査期間が
ｔ／２になっておシ、（第４図ｄ）アスペクト比の違い
による画像の歪を無くすためにｔ／２×４／＋５＝２ｔ
１５の期間に読み出される。さらに第３図に示すように
表示面の右寄りに表示するためにそれに相当するｔ１１
時間、水平偏向開始点から遅れて読み出している。（第
４図Ｃ）即ち書き込み時間ｔに対し１．時間位相が遅れ
、２ｔ１５時間に時間軸変換された画像信号が記憶装置
４から得られる。記憶装置４からの時間軸変換された信
号は、補間回路１５で増加した走査線の映像信号が作成
される。即ち、前述したようにラスターを形成する走査
線の数は倍速走査によって倍増しているので、映像信号
もそれに見合った本数にする必要があり、補間回路１５
で例えば同じ映像信号を二度使用する前置補間等によっ
て、映像信号を作り出している。補間回路１５よりのデ
ジタル映像信号は切換回路６で、制御回路１３からの制
御信号により、第３図人に相当する期間切換えられ、Ｄ
／Ａ変換器６に送られる。Ｄ／ム変換器ｅでアナログ信
号に変換された信号はマトリックス回路７でＲ，Ｇ、Ｂ
信号に変換され、出力回路８で所望の振幅まで増幅後、
陰極線管１０を駆動し、第３図人の親画像部を倍速走査
で得る。The video signal for the parent image that has arrived at the input terminal 1 is demodulated by the video signal processing circuit 2 into a luminance signal Y and color difference signals RY and B-Y, and then converted into digital video signals by the M/D converter 3. is converted to Furthermore, the incoming video signal is sent to the synchronous separation circuit 1.
1 is also supplied, and the synchronization signal is separated. Synchronous separation circuit 1
The horizontal synchronization signal separated by 1 is supplied to a scanning signal generation circuit 14 that generates a double-speed horizontal synchronization signal having twice the frequency of the received horizontal synchronization signal. The output signal of the scanning signal generation circuit 14 is supplied to the deflection yoke 9 via the deflection circuit 12.
A raster having twice the number of scanning lines is formed on the cathode ray tube 10. The raster formed at this time completely scans the display surface of the cathode ray tube 1o. At the same time, the synchronization signal is also supplied to the control circuit 13. The digital video signal output from the gam/D converter 3 is written into the storage device 4 by a write signal from the control circuit 13. Assume now that the parent image is displayed on the right side of a display screen with an aspect ratio of 5:3, and the child image is displayed on the lower left side of the display screen, as shown in FIG. At this time, the data is read out from the storage device 4 in a phase relationship such that it is closer to the right side of the screen, as shown in FIG. 3, and is read out with the time axis converted so as not to cause image distortion. The operation of the storage device 4 will be explained in more detail using FIG. 4. The arrived video signal (FIG. 4 &) is written into the storage device 4 in a video signal period t, taking t time. (Figure 4b) As mentioned above, the raster is formed with twice the number of scanning lines, so one horizontal scanning period is t/2, and (Figure 4d) the aspect ratio is To eliminate image distortion due to differences, t/2×4/+5=2t
It is read out in a period of 15. Furthermore, as shown in FIG. 3, in order to display on the right side of the display surface, t11
The reading is delayed in time from the horizontal deflection start point. (FIG. 4C) That is, 1. An image signal whose time phase is delayed and whose time axis is converted at time 2t15 is obtained from the storage device 4. The time-base converted signal from the storage device 4 is used in an interpolation circuit 15 to create a video signal of increased scanning lines. That is, as mentioned above, since the number of scanning lines forming a raster is doubled due to double-speed scanning, it is necessary to increase the number of video signals accordingly.
For example, a video signal is created by pre-interpolation, which uses the same video signal twice. The digital video signal from the interpolation circuit 15 is switched by the switching circuit 6 for a period corresponding to the person in FIG. 3 by the control signal from the control circuit 13.
/A converter 6. The signal converted into an analog signal by the D/mu converter e is converted into R, G, B by the matrix circuit 7.
After being converted into a signal and amplified to the desired amplitude by the output circuit 8,
The cathode ray tube 10 is driven to obtain the main image portion of the person shown in FIG. 3 at double speed scanning.
次に子画像部の動作について説明する。Next, the operation of the child image section will be explained.
入力端子２０に到来した子画像用映像信号は、映像信号
処理回路２１で輝度信号Ｙと色差信号Ｒ−Ｙ、Ｂ−Ｙに
復調された後、Ａ／Ｄ変換器２２で各々デジタル信号に
変換され記憶装置２３に書き込まれる。入力端子２０に
到来した映像信号は、同期分離回路２４にも供給されて
おり同期信号が分離される。同期分離回路２４で分離さ
れた同期信号は制御回路１３に供給されている。記憶装
置２３からの読み出しは、制御回路１３からの親画像用
映像信号に同期して読み出される。第３図に示すように
子画像を表示部の左下部Ｂに表示するものとすると、子
画像映像信号に同期して１垂直期間かかって記憶装置２
３に書き込まれた子画像用映像信号（第６図ａ）は第３
図Ｂに相当する期間Ｔｖに親画像に同期して読み出され
る。（第６図ｂ）この時、子画像を歪みなく表示するた
めの体平表示期間ＴＩＩは第６図に示すように’ｌ’Ｉ
Ｉ＝ａ／ｃＸＭＸＨ’で表わされ、前述したように、ア
スペクト比は各々４／ｂ＝４／３．。／ｄ＝５／３であ
り又ｄ／１） ＝ Ｎ ＝ ２なのでＴＨ−１５ｔと表
わせる。即ち、水平有効走査期間がｔの信号をｔ時間か
かって記憶装置２３に書き込まれ、読み出しは６倍の速
度で読み出される。The child image video signal that has arrived at the input terminal 20 is demodulated into a luminance signal Y and color difference signals R-Y and B-Y in a video signal processing circuit 21, and then converted into digital signals by an A/D converter 22. and written to the storage device 23. The video signal arriving at the input terminal 20 is also supplied to a synchronization separation circuit 24, where the synchronization signal is separated. The synchronization signal separated by the synchronization separation circuit 24 is supplied to the control circuit 13. Reading from the storage device 23 is performed in synchronization with the parent image video signal from the control circuit 13. As shown in FIG. 3, if the child image is to be displayed at the lower left B of the display section, it will take one vertical period to display the child image on the storage device in synchronization with the child image video signal.
The video signal for the child image (Fig. 6a) written in No. 3 is
It is read out in synchronization with the parent image during the period Tv corresponding to FIG. B. (Fig. 6b) At this time, the horizontal display period TII for displaying the child image without distortion is 'l'I' as shown in Fig. 6.
I=a/cXMXH', and as mentioned above, the aspect ratios are 4/b=4/3. . /d=5/3 and d/1)=N=2, so it can be expressed as TH-15t. That is, a signal with a horizontal effective scanning period of t is written into the storage device 23 over a period of t, and is read out at six times the speed.
なお水平方向の読み出し開始点は、第３図の場合、水平
偏向の開始点と一致している。記憶装置２３から読み出
された子画像用映像信号は、切換回路５により制御回路
１３からの信号によって、子画像表示期間Ｄ／Ａ変換器
６に送られる。Ｄ／Ａ変換器６でアナログ信号に変換さ
れた信号は、マトリックス回路７でＲ，Ｇ、Ｂ信号に変
換され、出力回路８で所望の振幅まで増幅後、陰極線管
１０を駆動し、子画像を得る。Note that the readout start point in the horizontal direction coincides with the horizontal deflection start point in the case of FIG. The child image video signal read from the storage device 23 is sent to the child image display period D/A converter 6 by the switching circuit 5 in response to a signal from the control circuit 13. The signal converted into an analog signal by the D/A converter 6 is converted into R, G, and B signals by the matrix circuit 7, and after amplified to a desired amplitude by the output circuit 8, the cathode ray tube 10 is driven and the sub-image get.
発明の効果
以上のように本発明によれば、アスペクト比Ｃ：ｄの表
示部全体をカバーする倍速走査のラスターを発生する偏
向回路と、親画像を倍速でかつ歪な、く表示するための
書き込み速度と読み出し速度が異なる記憶装置と、子画
像用の同じく書き込み速度と読み出し速度が異なる記憶
装置を設けることにより、子画像の間引きによる画質劣
化が無く、また例えば親画像は右寄りに、子画像は左寄
りに表示することができ、横長な表示部を有効に使用し
て親画像の欠落部を最小とすることができ、その実用的
効果は大きい。Effects of the Invention As described above, the present invention includes a deflection circuit that generates a double-speed scanning raster that covers the entire display area with an aspect ratio of C:d, and a deflection circuit for displaying a parent image at double speed and without distortion. By providing a storage device with different write speeds and read speeds and a storage device with different write speeds and read speeds for child images, there is no image quality deterioration due to thinning of child images. can be displayed on the left side, and the horizontally long display area can be effectively used to minimize the missing part of the parent image, which has a great practical effect.
第１図は本発明の一実施例におけるテレビジョン受像機
のブロック図、第２図は従来のテレビジョン受像機の表
示状態を示す図、第３図は本発明の受像機の表示状態を
示す図、第４図は親画像用の記憶装置の動作を説明する
だめの波形図、第５図は子画像用記憶装置の動作を説明
するための図、第６図は子画像用記憶装置の読み出し速
度を説明する図である。
１．２０ ・・入力端子、２．２１ ・・映像信号処理
回路、３，２２・・・・・・Ａ／Ｄ変換器、４，２３・
・・・・・記憶装置、５・・・・・切換回路、６・・・
・・Ｄ／Ａ変換器、７・・・・マトリックス、８・・・
・・・増幅回路、９・・・・・偏向ヨーク、１０・・・
・・陰極線管、１１，２４０９．・・・同期分離回路、
１２・・・・・・偏向回路、１３・・・・・・制御回路
、１４・・・・・・走査信号発生回路、１５・・・・・
・補間回路。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名目り
梠 、Ｏ
０８区FIG. 1 is a block diagram of a television receiver according to an embodiment of the present invention, FIG. 2 is a diagram showing a display state of a conventional television receiver, and FIG. 3 is a diagram showing a display state of a television receiver of the present invention. 4 is a waveform diagram for explaining the operation of the storage device for parent images, FIG. 5 is a diagram for explaining the operation of the storage device for child images, and FIG. 6 is a waveform diagram for explaining the operation of the storage device for child images. It is a figure explaining read speed. 1.20...Input terminal, 2.21...Video signal processing circuit, 3,22...A/D converter, 4,23...
...Storage device, 5...Switching circuit, 6...
...D/A converter, 7...matrix, 8...
...Amplification circuit, 9...Deflection yoke, 10...
...Cathode ray tube, 11,2409. ...Synchronization separation circuit,
12...Deflection circuit, 13...Control circuit, 14...Scanning signal generation circuit, 15...
・Interpolation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person Riku, O 08 Ward
Claims (1)
第１のテレビジョン信号のほぼＮ倍の走査線数を有し、
かつアスペクト比ｃ：ｄ（ａ／ｂ＜ｃ／ｄ）の第２のテ
レビジョン信号とを受像するテレビジョン受像機におい
て、第１のテレビジョン信号受像時に受信した水平同期
信号のＮ倍の周波数の倍速水平同期信号を発生する走査
信号発生回路と、アスペクト比ｃ：ｄの表示部全体を走
査する偏向回路と、第１のテレビジョン信号に同期して
第１のテレビジョン信号を書き込み、ｃ／ａ×Ｎの速度
で読み出す第１の記憶装置と、第１のテレビジョン信号
とアスペクト比が同じの第３のテレビジョン信号を、第
３のテレビジョン信号に同期して書き込み、第１のテレ
ビジョン信号に同期して、ｃ／ａ×Ｎ＾２の速度で読み
出す記憶装置を備えたことを特徴とするテレビジョン受
像機。a first television signal having an aspect ratio a:b and a number of scan lines approximately N times that of the first television signal;
and a second television signal with an aspect ratio of c:d (a/b<c/d), the frequency is N times that of the horizontal synchronization signal received when receiving the first television signal. a scanning signal generation circuit that generates a double-speed horizontal synchronizing signal of c:d; a deflection circuit that scans the entire display section with an aspect ratio of c:d; /a×N, and write a third television signal having the same aspect ratio as the first television signal in synchronization with the third television signal. A television receiver comprising a storage device that reads data at a speed of c/a×N^2 in synchronization with a television signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22514585A JPS6284665A (en) | 1985-10-09 | 1985-10-09 | Television receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22514585A JPS6284665A (en) | 1985-10-09 | 1985-10-09 | Television receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284665A true JPS6284665A (en) | 1987-04-18 |
Family
ID=16824651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22514585A Pending JPS6284665A (en) | 1985-10-09 | 1985-10-09 | Television receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284665A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01182886A (en) * | 1988-01-13 | 1989-07-20 | Sharp Corp | Liquid crystal display device |
| US5130800A (en) * | 1989-12-28 | 1992-07-14 | North American Philips Corporation | Picture out of picture feature for wide-screen display |
| US7116379B2 (en) | 2000-12-26 | 2006-10-03 | Seiko Epson Corporation | Projector and method of adjusting projection size |
-
1985
- 1985-10-09 JP JP22514585A patent/JPS6284665A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01182886A (en) * | 1988-01-13 | 1989-07-20 | Sharp Corp | Liquid crystal display device |
| US5130800A (en) * | 1989-12-28 | 1992-07-14 | North American Philips Corporation | Picture out of picture feature for wide-screen display |
| US7116379B2 (en) | 2000-12-26 | 2006-10-03 | Seiko Epson Corporation | Projector and method of adjusting projection size |
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