JP2605255B2 - TV receiver - Google Patents
TV receiverInfo
- Publication number
- JP2605255B2 JP2605255B2 JP59207401A JP20740184A JP2605255B2 JP 2605255 B2 JP2605255 B2 JP 2605255B2 JP 59207401 A JP59207401 A JP 59207401A JP 20740184 A JP20740184 A JP 20740184A JP 2605255 B2 JP2605255 B2 JP 2605255B2
- Authority
- JP
- Japan
- Prior art keywords
- image
- aspect ratio
- signal
- video signal
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 産業上の利用分野 本発明はテレビジョン受像機の画面に同時に２種類の
画像を映出できるテレビジョン受像機に関するものであ
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver capable of simultaneously displaying two types of images on a screen of the television receiver.
従来例の構成とその問題点 近年、テレビジョン画像の高解像度化高画質化が求め
られ、走査線数が現行NTSC方式やPAL方式の約２倍の走
査線数を有し、周波数帯域を広帯域化して高解像度化を
はかり、かつ、アスペクト比を現行4:3よりも横長な例
えば5:3にしたテレビジョン方式が種々提案され、横長
な表示部を有する受像機が実用化されている。Conventional configuration and its problems In recent years, there has been a demand for higher resolution and higher image quality of television images, and the number of scanning lines is twice as large as that of the current NTSC and PAL systems. Various television systems have been proposed in which the resolution is increased to increase the resolution and the aspect ratio is set to, for example, 5: 3, which is longer than the current 4: 3, and a receiver having a horizontally long display unit has been put to practical use.
また、このようなアスペクト比5:3の横長の表示部を
用する受像機にアスペクト比4:3の現行テレビジョン方
式の画像をも表示出来る機能を有する受像機も提案され
ている。ところがこの様な機能を有する受像機で現行テ
レビジョン放送を受像し、第１図に示すように、アスペ
クト比5:3の表示部全体に表示すると、画像が歪むとい
う不都合（第１図ｂ）が生じる。そのため偏向電流を制
御して表示部の一部にアスペクト比4:3の画像を表示す
ることによって（第１図ｃ）歪が生じないようにしてい
る。Also, there has been proposed a receiver having a function of displaying an image of the current television system having an aspect ratio of 4: 3 on a receiver using such a horizontally long display unit having an aspect ratio of 5: 3. However, when a current television broadcast is received by a receiver having such a function and displayed on the entire display portion having an aspect ratio of 5: 3 as shown in FIG. 1, the image is distorted (FIG. 1B). Occurs. For this reason, distortion is prevented from occurring by controlling the deflection current and displaying an image having an aspect ratio of 4: 3 on a part of the display section (FIG. 1c).
ところがこの様に偏向電流を制御して歪を無くす方式
の受像機において、画面の一部に、別の画像を同時に表
示する、いわゆる親子画面の機能をさらに追加しようと
すると、第１図ｄに示すように、子画像によって、親画
像が欠落するという不都合が生じる。However, in the receiver of the type in which the deflection current is controlled to eliminate the distortion as described above, when a function of a so-called parent-child screen for simultaneously displaying another image on a part of the screen is further added, FIG. As shown, the disadvantage that the parent image is missing due to the child image occurs.
発明の目的 そこで本発明は、現行テレビジョン方式（アスペクト
比4:3）よりも横長なアスペクト比例えば、アスペクト
比5:3の表示部に、現行テレビジョン方式の画像を親子
画面で表示するとともに、横長な表示部を有効に使用し
て子画像によって欠落する親画像部を最小にするテレビ
ジョン受像機を提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, the present invention displays an image of the current television system on a display unit having an aspect ratio that is longer than that of the current television system (aspect ratio 4: 3), for example, an aspect ratio of 5: 3, on a parent-child screen. It is another object of the present invention to provide a television receiver that effectively uses a horizontally long display unit and minimizes a parent image portion missing due to a child image.
発明の構成 本発明は親画像信号を歪みなく表示するための書き込
み速度と読み出し速度の異なる記憶装置と子画像用の同
じく書き込み速度と読み出し速度の異なる記憶装置を備
え、例えば親画像は右寄りに、子画像は左寄りに表示し
て、横長な表示部を有効に使用して親画像の欠落部を最
小にしようとするものである。The present invention comprises a storage device having a different writing speed and reading speed for displaying the parent image signal without distortion, and a storage device having the same writing speed and reading speed for the child image, for example, the parent image is to the right, The child image is displayed to the left, and the horizontally long display portion is used effectively to minimize the missing portion of the parent image.
実施例の説明 以下本発明の実施例について図面を参照して説明す
る。DESCRIPTION OF THE EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例におけるテレビジョン受像
機のブロック図を示すものである。第２図において、１
と20は入力端子、２と21は映像信号処理回路、３と22は
A/D変換器、４と23は記憶装置、５は切換回路、６はD/A
変換器、７はマトリックス、８は増幅回路、９は偏向ヨ
ーク、10は陰極線管、11と24は同期分離回路、12は偏向
回路、13は制御回路である。FIG. 2 is a block diagram of a television receiver according to one embodiment of the present invention. In FIG. 2, 1
And 20 are input terminals, 2 and 21 are video signal processing circuits, and 3 and 22 are
A / D converters, 4 and 23 are storage devices, 5 is a switching circuit, 6 is D / A
A converter, 7 is a matrix, 8 is an amplifying circuit, 9 is a deflection yoke, 10 is a cathode ray tube, 11 and 24 are synchronous separation circuits, 12 is a deflection circuit, and 13 is a control circuit.
ここで理解を容易とするために、横長な表示部のアス
ペクト比として5:3、親子表示するテレビジョン信号の
アスペクト比として4:3として説明するが、これらに限
定されるものではない。Here, for ease of understanding, the aspect ratio of the horizontally long display unit will be described as 5: 3, and the aspect ratio of the television signal to be displayed as a parent and a child will be described as 4: 3, but the present invention is not limited to these.
入力端子１に到来した親画像用の映像信号は、映像信
号処理回路２で輝度信号Ｙと色差信号Ｒ−Y,B−Ｙに復
調された後、A/D変換器３で各々デジタル映像信号に変
換される。この時のサンプリング周波数はSとする。
さらに到来した映像信号は同期分離回路11にも供給され
同期信号が分離される。同期分離回路11で分離された同
期信号は偏向回路12を介して偏向ヨーク９に供給され、
陰極線管10上にラスターを形成する。この時形成された
ラスターは陰極線管10の表示面を完全にカバーしてい
る。同時に前記同期信号は制御回路13にも供給されてい
る。A/D変換器３の出力のディジタル映像信号は制御回
路13よりの書き込み信号により記憶装置４に書き込まれ
る。今仮りに第３図に示すように親画像をアスペクト比
5:3の表示面の右側に寄せ、1/4に縮少された子画像を表
示面の左下側に寄せて表示するとする。この時記憶装置
４からの読み出しは、第３図に示したように画面の右側
に寄るような位相関係でかつ、画像の歪みが生じないよ
う時間軸圧縮されて読み出される。記憶装置４の動作に
ついて第４図を用いてもう少し詳しく説明する。到来し
た映像信号（第４図ａ）は、画像信号期間ｔの信号が、
ｔ時間かかって記憶装置４に書き込まれる（第４図
ｃ）。読み出しは画面を右側に寄せるために、到来映像
信号の画像信号のスタート点よりt/5遅れた時点から読
み出しが開始され、読み出し速度は画像の歪を取るため
に4t/5の期間で読み出され、画像信号ｔが4/5tに時間圧
縮される（第４図ｄ）。なおこの時前述したように、ラ
スターを表示面を完全にカバーするため、走査期間はｔ
である（第４図ｂ）。The video signal for the parent image arriving at the input terminal 1 is demodulated by the video signal processing circuit 2 into a luminance signal Y and color difference signals R-Y, B-Y. Is converted to The sampling frequency at this time is S.
Further, the arriving video signal is also supplied to a synchronization separation circuit 11, where the synchronization signal is separated. The synchronization signal separated by the synchronization separation circuit 11 is supplied to the deflection yoke 9 via the deflection circuit 12,
A raster is formed on the cathode ray tube 10. The raster formed at this time completely covers the display surface of the cathode ray tube 10. At the same time, the synchronization signal is also supplied to the control circuit 13. The digital video signal output from the A / D converter 3 is written to the storage device 4 by a write signal from the control circuit 13. Assuming now that the parent image has an aspect ratio as shown in FIG.
It is assumed that the child image reduced to 1/4 is displayed on the lower left side of the display surface, while being displayed on the right side of the display surface of 5: 3. At this time, the data is read out from the storage device 4 in such a way that the phase relationship is shifted toward the right side of the screen as shown in FIG. 3 and the time axis is compressed so that no image distortion occurs. The operation of the storage device 4 will be described in more detail with reference to FIG. The incoming video signal (FIG. 4a) has a signal in the image signal period t,
The data is written to the storage device 4 in the time t (FIG. 4c). Reading is started from the point of time t / 5 behind the start point of the image signal of the incoming video signal to shift the screen to the right, and the reading speed is read in 4t / 5 to remove image distortion. The image signal t is time-compressed to 4 / 5t (FIG. 4d). At this time, as described above, in order to completely cover the display surface with the raster, the scanning period is t.
(FIG. 4b).
記憶装置４から読み出された時間軸圧縮されたデジタル
映像信号は切換回路５で、制御回路13からの制御信号に
より第３図Ａに相当する期間切換えられ、D/A変換器６
に送られる。D/A変換器６でアナログ信号に変換された
信号は、マトリックス回路７で、R,G,B信号に変換さ
れ、出力回路８で所望の振幅まで増幅後、陰極線管10を
駆動し、第３図Ａの親画像部を得る。The time-axis-compressed digital video signal read from the storage device 4 is switched in a switching circuit 5 by a control signal from a control circuit 13 for a period corresponding to FIG.
Sent to The signal converted to an analog signal by the D / A converter 6 is converted into R, G, B signals by a matrix circuit 7, amplified to a desired amplitude by an output circuit 8, and then drives a cathode ray tube 10. 3 Obtain the parent image section of FIG.
次に子画像部の動作について説明する。 Next, the operation of the child image unit will be described.
入力端子20に到来した子画像用映像信号は、映像信号
処理回路21で輝度信号Ｙと色差信号Ｒ−Y,B−Ｙに復調
された後、A/D変換器22で各々デジタル信号に変換され
る。前述したように、子画像の大きさを通常画像1/4と
すると、水平，垂直方向とも1/2に間引けば良い。The video signal for a child image arriving at the input terminal 20 is demodulated by a video signal processing circuit 21 into a luminance signal Y and color difference signals RY and BY, and then converted into digital signals by an A / D converter 22. Is done. As described above, assuming that the size of the child image is 1/4 of the normal image, the size of the child image may be reduced to 1/2 in both the horizontal and vertical directions.
第５図に示すように二重丸印を含む丸印がサンプリン
グ周波数Sでサンプリングされたサンプリング点とす
ると、サンプリング周期を２倍にすると二重丸印がサン
プリング点となり、水平方向に1/2に間引かれる。垂直
方向は１水平走査線おきにサンプリングされ、1/2に間
引かれる。すなわち、制御回路13より第６図に示すよう
な１水平走査期間ごとに、くり返し周波数がS/2のサ
ンプリングパルスによって、子画像用映像信号が、A/D
変換器22でデジタル信号に変換され、記憶装置23に書き
込まれる。なお同期分離回路24で分離された子画像用映
像信号の同期信号は制御回路13に供給されている。記憶
装置23からの読み出しは、制御回路13からの親画像用映
像信号に同期して読み出される。第３図に示すように子
画像を表示部の左下部Ｂに表示するものとすると、子画
像用映像信号に同期して１垂直期間かかって記憶装置23
に書き込まれた子画像用映像信号（第７図ａ）は第３図
Ｂに相当する期間TVに親画像に同期して読み出される
（第７図ｂ）。また水平方向にも1/2に間引かれている
ため、親画像用映像信号と同じ速度で、親画像表示期間
4/5tの半分の期間に読み出される。なお、水平方向の読
み出し開始点は、第３図の場合、水平偏向の開始点と一
致している。このように第３図Ｂに示す画像表示期間に
記憶装置23から読み出された子画像用映像信号は、切換
回路５により制御回路13からの信号によって、前記子画
像表示期間D/A変換器６に送られる。D/A変換器６でアナ
ログ信号に変換された信号は、マトリックス回路７でR,
G,B信号に変換され、出力回路８で所望の振幅まで増幅
後、陰極線管10を駆動し、第３図Ｂの子画像部を得る。As shown in FIG. 5, when a circle including a double circle is a sampling point sampled at the sampling frequency S , if the sampling period is doubled, the double circle becomes a sampling point, and the horizontal circle becomes 1/2. Is thinned out. In the vertical direction, sampling is performed every other horizontal scanning line, and the sampling is halved in half. That is, the control circuit 13 converts the child image video signal into an A / D signal by a sampling pulse having a repetition frequency of S / 2 every one horizontal scanning period as shown in FIG.
The signal is converted into a digital signal by the converter 22 and written into the storage device 23. The synchronization signal of the child image video signal separated by the synchronization separation circuit 24 is supplied to the control circuit 13. Reading from the storage device 23 is performed in synchronization with the parent image video signal from the control circuit 13. As shown in FIG. 3, assuming that the child image is displayed in the lower left portion B of the display unit, it takes one vertical period in synchronization with the video signal for the child image to store in the storage device 23.
Written child image video signal (Fig. 7 a) is read out in synchronization with the parent image in the period T V corresponding to FIG. 3 B (Fig. 7 b). Also, since it is thinned out in half in the horizontal direction, the parent image display period is maintained at the same speed as the parent image video signal.
It is read out during half the period of 4 / 5t. Note that the horizontal reading start point coincides with the horizontal deflection start point in the case of FIG. In this way, the video signal for the child image read out from the storage device 23 during the image display period shown in FIG. 3B is changed by the signal from the control circuit 13 by the switching circuit 5 to the D / A converter. Sent to 6. The signals converted into analog signals by the D / A converter 6 are converted into R,
After being converted into G and B signals and amplified by the output circuit 8 to a desired amplitude, the cathode ray tube 10 is driven to obtain the child image portion shown in FIG. 3B.
以上の説明では親画像及び子画像を第３図の位置に表
示する場合にとり述べてきたが、この位置に限らないこ
とは言うまでもない。また子画像の大きさを親画像の1/
4として述べてきたがこの大きさに制約されることはな
いことは言うまでもない。In the above description, the case where the parent image and the child image are displayed at the positions shown in FIG. 3 has been described, but it goes without saying that the present invention is not limited to these positions. Also, the size of the child image is 1 /
Although described as 4, it is needless to say that the size is not limited.
発明の効果 以上のように本発明によれば、アスペクト比c:dのテ
レビジョン受像時にアスペクト比a:cの表示部をカバー
するラスターを発生する偏向回路と、親画像の歪を無く
すため、書き込み速度と読み出し速度が異なる記憶装置
と、子画像用の同じく書き込み速度と読み出し速度の異
なる記憶装置を設けることにより、例えば親画像は右寄
りに、子画像は左寄りに表示することができ、横長な表
示部を有効に使用して親画像の欠落部を最小とすること
ができ、その実用的効果は大きい。Advantageous Effects of the Invention As described above, according to the present invention, a deflection circuit that generates a raster that covers a display unit having an aspect ratio a: c during television reception with an aspect ratio c: d, and to eliminate distortion of a parent image, By providing a storage device having a different writing speed and a reading speed and a storage device having the same writing speed and reading speed for a child image, for example, the parent image can be displayed on the right side, and the child image can be displayed on the left side. The display portion can be effectively used to minimize the missing portion of the parent image, and the practical effect is large.
第１図は従来のテレビジョン受像機の表示状態を示す画
面の平面図、第２図は本発明の一実施例におけるテレビ
ジョン受像機のブロック図、第３図は同受像機の表示状
態を示す画面の図、第４図は同親画像用の記憶装置の動
作を説明するための波形図、第５図はサンプリング点を
示す図、第６図は同サンプリングタイミングを示す図、
第７図は同子画像用記憶装置の動作を説明するための図
である。 1,20……入力端子、2,21……映像信号処理回路、3,22…
…A/D変換器、4,23……記憶装置、５……切換回路、６
……D/A変換器、７……マトリックス、８……増幅回
路、９……偏向ヨーク、10……陰極線管、11,24……同
期分離回路、12……偏向回路、13……制御回路。FIG. 1 is a plan view of a screen showing a display state of a conventional television receiver, FIG. 2 is a block diagram of the television receiver in one embodiment of the present invention, and FIG. 3 is a display state of the television receiver. FIG. 4 is a waveform diagram for explaining the operation of the storage device for the same-parent image, FIG. 5 is a diagram showing sampling points, FIG. 6 is a diagram showing the same sampling timing,
FIG. 7 is a diagram for explaining the operation of the same-child image storage device. 1,20 input terminal, 2,21 video signal processing circuit, 3,22
... A / D converter, 4,23 ... Storage device, 5 ... Switching circuit, 6
... D / A converter, 7 ... Matrix, 8 ... Amplifier circuit, 9 ... Deflection yoke, 10 ... Cathode tube, 11,24 ... Synchronous separation circuit, 12 ... Deflection circuit, 13 ... Control circuit.
Claims (1)
比c:d（a/b＞c/d）のテレビジョン信号を書き込み、所
定の位相と速度で読み出す親画像用映像信号を記憶する
第１の記憶装置と、前記親画像用映像信号に同期し、前
記アスペクト比a:bの表示部全体をカバーするラスター
を生成する偏向回路と、アスペクト比c:dのテレビジョ
ン信号を1/mに間引いて書き込み、前記親画像と同期
し、所定の位相と速度で読み出す第２の記憶装置を備え
たテレビジョン受像機。1. A display section having an aspect ratio of a: b, a television signal having an aspect ratio of c: d (a / b> c / d) is written, and a parent image video signal is read out at a predetermined phase and speed. A first storage device, a deflecting circuit that synchronizes with the video signal for the parent image and generates a raster that covers the entire display unit with the aspect ratio a: b, and a television signal with an aspect ratio c: d. A television receiver comprising a second storage device that writes data at a rate of / m and writes the data at a predetermined phase and speed in synchronization with the parent image.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207401A JP2605255B2 (en) | 1984-10-03 | 1984-10-03 | TV receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207401A JP2605255B2 (en) | 1984-10-03 | 1984-10-03 | TV receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6184977A JPS6184977A (en) | 1986-04-30 |
| JP2605255B2 true JP2605255B2 (en) | 1997-04-30 |
Family
ID=16539131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59207401A Expired - Lifetime JP2605255B2 (en) | 1984-10-03 | 1984-10-03 | TV receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2605255B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57208772A (en) * | 1981-06-18 | 1982-12-21 | Sony Corp | Television receiver |
| JPS6052622B2 (en) * | 1982-07-02 | 1985-11-20 | 松下電器産業株式会社 | television receiver |
-
1984
- 1984-10-03 JP JP59207401A patent/JP2605255B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6184977A (en) | 1986-04-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |