JPS60135869U - Interleaving RAM read/write pulse generation circuit - Google Patents
Interleaving RAM read/write pulse generation circuitInfo
- Publication number
- JPS60135869U JPS60135869U JP2318584U JP2318584U JPS60135869U JP S60135869 U JPS60135869 U JP S60135869U JP 2318584 U JP2318584 U JP 2318584U JP 2318584 U JP2318584 U JP 2318584U JP S60135869 U JPS60135869 U JP S60135869U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- clock signal
- outputs
- ram
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図および第２図は本考案の背景の説明図、第３図は
本考案の実施例の回路図、第４図は第３図の回路の主要
個所の信号のタイミングチャートである。
１３．１４・・・・・・カウンタ制御回路、１５・・・
・・・第１カウンタ、１７・・・・・・第２カウンタ、
１８・・・・・・ＮＡＮＤ回路、ＣＫ３２・・・・・・
入力クロック信号、ＣＫ２４・・・・・・出力クロック
信号、Ａ３・・・・・・基本信号、ＡＩＯ・・・・・・
読出しパルス信号、Ａｌｌ・・・・・・書込みパルス信
号、Ａ１２・・・・・・所要の処理をするためのパルス
信号。1 and 2 are explanatory diagrams of the background of the present invention, FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a timing chart of signals at the main parts of the circuit of FIG. 3. 13.14... Counter control circuit, 15...
...first counter, 17...second counter,
18...NAND circuit, CK32...
Input clock signal, CK24... Output clock signal, A3... Basic signal, AIO...
Read pulse signal, All...Write pulse signal, A12...Pulse signal for performing required processing.
Claims (1)
納し所要の処理を施した後、前記入力クロック信号と非
同期の出力クロック信号によって出力するＰＣＭ記録再
生装置において、前記人力クロック信号と前記出力クロ
ック信号と、前記ＲＡＭの１ワードのアクセスタイムと
ほぼ等しい同期を有する基本信号とを入力とし、前記入
力クロック信号が高レベルのとき前記出力クロック信号
の立下りによって計数を開始し計数１に対応する前記基
本信号の１周期を表わすパルス信号を発生し前記ＲＡＭ
の読出しパルス信号として出力する第１カウンタと、 前記第１カウンタの計数管の出力直後にこのカウンタを
強制的に零にする制御信号を発生するカウンタ制御回路
と、 前記制御信号により前記第１カウンタの計数が零である
ことを検出し前記入力クロック信号の立下りによって計
数を開始し計数２に対応する前記基本信号の１周期を表
わすパルス信号を発生し前記ＲＡＭの書込みパルス信号
として出力する第２カウンタと、 前記第１カウンタおよび第２カウンタの出力のＮＡＮＤ
を求めそれを前記ＲＡＭの所要の処理のためのパルス信
号として出力するＮＡＮＤ回路とからなることを特徴と
するインタリーブ用ＲＡＭの読出し書込みパルス発生回
路。[Claims for Utility Model Registration] In a PCM recording and reproducing device that once stores input data in a RAM using an input clock signal, performs necessary processing, and then outputs it using an output clock signal that is asynchronous with the input clock signal, A signal, the output clock signal, and a basic signal having synchronization approximately equal to the access time of one word of the RAM are input, and counting is started at the falling edge of the output clock signal when the input clock signal is at a high level. generates a pulse signal representing one cycle of the basic signal corresponding to a count of 1;
a first counter that outputs a read pulse signal as a read pulse signal; a counter control circuit that generates a control signal that forcibly resets the counter to zero immediately after an output from a counter tube of the first counter; Detects that the count is zero, starts counting at the falling edge of the input clock signal, generates a pulse signal representing one cycle of the basic signal corresponding to count 2, and outputs it as a write pulse signal for the RAM. 2 counters, and NAND of the outputs of the first and second counters.
1. A read/write pulse generation circuit for an interleaving RAM, characterized in that the circuit comprises a NAND circuit that calculates the value of the pulse signal and outputs it as a pulse signal for necessary processing of the RAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2318584U JPS60135869U (en) | 1984-02-21 | 1984-02-21 | Interleaving RAM read/write pulse generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2318584U JPS60135869U (en) | 1984-02-21 | 1984-02-21 | Interleaving RAM read/write pulse generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60135869U true JPS60135869U (en) | 1985-09-09 |
Family
ID=30516190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2318584U Pending JPS60135869U (en) | 1984-02-21 | 1984-02-21 | Interleaving RAM read/write pulse generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60135869U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03278375A (en) * | 1990-03-27 | 1991-12-10 | Sharp Corp | Recording position correcting circuit for digital information recording and reproducing device |
-
1984
- 1984-02-21 JP JP2318584U patent/JPS60135869U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03278375A (en) * | 1990-03-27 | 1991-12-10 | Sharp Corp | Recording position correcting circuit for digital information recording and reproducing device |
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