JPS6142964A - Dual gate field effect transistor - Google Patents
Dual gate field effect transistorInfo
- Publication number
- JPS6142964A JPS6142964A JP16520984A JP16520984A JPS6142964A JP S6142964 A JPS6142964 A JP S6142964A JP 16520984 A JP16520984 A JP 16520984A JP 16520984 A JP16520984 A JP 16520984A JP S6142964 A JPS6142964 A JP S6142964A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- width
- dual gate
- mixer
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 title claims description 14
- 230000005669 field effect Effects 0.000 title claims description 4
- 239000002184 metal Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000010355 oscillation Effects 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8124—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with multiple gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は歪特性を改善したデュアル・ゲート電界効果ト
ランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a dual gate field effect transistor with improved strain characteristics.
従来例のＩｉ８戒とその問題点
変調器やミキサーに電界効果トランジスタ（ＦＥＴ）は
よく使われている。特に、最近、高周波特性を向上させ
るために優れた高周波特性を持つＧａ Ａｓ ＭＥＳ
ＦＥＴを用いた変調器やミキサーが開発されている
。とりわけ、デュアル・ゲートＧａ Ａｓ ＭＥＳ
ＦＥＴは局発信号と信号の分離が容易などの特徴があ
る。これはたとえば、第１図に示ずような横）Δのもの
である。Conventional Ii8 Commandments and their Problems Field-effect transistors (FETs) are often used in modulators and mixers. In particular, GaAs MES with excellent high frequency characteristics has recently been developed to improve high frequency characteristics.
Modulators and mixers using FETs have been developed. Among others, dual gate GaAs MES
FETs have the advantage of being easy to separate local oscillation signals from signals. This is, for example, the transverse) Δ as shown in FIG.
ＱａＡｓデュアル・ゲートＭＥＳ ＦＥＩ−１のソー
ス２を接地する。第１ゲート３に整合回路４を設け、信
号入力端５から信号を入力する。第２ゲート６にも整合
回路７を設け、局発信号入力端８から局発信号を入力す
る。ドレイン９には中間信号の整合回路１０を設け、１
１が中間信号出力端となる。Source 2 of QaAs dual gate MES FEI-1 is grounded. A matching circuit 4 is provided at the first gate 3, and a signal is input from a signal input terminal 5. A matching circuit 7 is also provided in the second gate 6, and a local oscillation signal is inputted from a local oscillation signal input terminal 8. An intermediate signal matching circuit 10 is provided at the drain 9, and 1
1 is the intermediate signal output terminal.
ａｇＪ波歪を下げるために、平衡さＶた構造のミキサー
（バランスド・ミキサー）や平衡変調器も開発されてい
る。たとえば、第２図に示すようなダブル・バランスド
・ミキサーが開発されている。In order to reduce agJ wave distortion, mixers with a balanced V structure (balanced mixers) and balanced modulators have also been developed. For example, a double balanced mixer as shown in FIG. 2 has been developed.
４つのＱａ Ａｓデュアル・ゲートＭＥＳ ＦＥＴの
ソース１２を共通接地する。第１ゲートは第２因のよう
に配線され２つの第１ゲートは位相返転回路１３を経て
、残りの２つの第１ゲートは直接に信号入力端１４に接
続される。第２ゲートは第２図のように配線され、２つ
の第２ゲートは位相反転回路１５を経て、残りの２つの
第２ゲートは直接に局発信号入力端１６に接続される。The sources 12 of the four Qa As dual gate MES FETs are commonly grounded. The first gates are wired like the second factor, two first gates are connected through the phase reversing circuit 13, and the remaining two first gates are directly connected to the signal input terminal 14. The second gates are wired as shown in FIG. 2, two of the second gates are connected to the phase inversion circuit 15, and the remaining two second gates are directly connected to the local oscillator signal input terminal 16.
ドレインは２つのドレインは位相反転回路１３．１７を
経て、他の２つのドレインは直接に中間信号出力ＩＭｉ
ａに接続される。このようにバランスド構成にＪ“るこ
とで、ｎ調波の歪を低減することができる。Two drains pass through a phase inversion circuit 13.17, and the other two drains directly output an intermediate signal IMi.
connected to a. By adopting a balanced configuration in this way, distortion of n harmonics can be reduced.
しかしながら、上記のダブル・バランスド・ミキサーあ
るいは２重平衡変調器にＪ３いては、８発信号や２次歪
等偶数次高調波歪は打ち消せるが、３次歪は打ち消すこ
とができず、特に、′Ｂ調波で一番、中間上９近くに現
われる３次歪を低減できないという問題点を有していた
。However, with J3 in the above-mentioned double balanced mixer or double balanced modulator, even-order harmonic distortion such as 8-shot signals and 2nd-order distortion can be canceled, but 3rd-order distortion cannot be canceled, especially , 'B harmonics, and the third-order distortion that appears near the middle upper 9th wave cannot be reduced.
発明の目的 本発明はこのような従来の問題に鑑み、ミキ→ノ。purpose of invention In view of such conventional problems, the present invention has been developed based on the present invention.
−や変調器の３次歪等を低減し、ミキサーや変調器とし
てもつとも望ましい特性をもつデュアル・ゲートＦＥＴ
を提供することを目的とするものである。Dual gate FET with desirable characteristics as a mixer or modulator, reducing third-order distortion of the modulator and other factors.
The purpose is to provide the following.
発明の構成
本発明は第１ゲート幅を第２ゲート幅より大きくする描
造にしたもので、これにより、３次歪を低減し、優れた
変調器又はミキ°す“−を可能とするものである。Structure of the Invention The present invention is designed to make the first gate width larger than the second gate width, thereby reducing third-order distortion and making it possible to create an excellent modulator or mixer. It is.
実施例の説明
以下本発明の一実施例を図面に暴づいて説明する。第３
図は本発明の一実施例におけるチップパターン図を示ず
。ソース２０にボンディング・パッドを設け、第１ゲー
ト２１を６００μＩのゲート幅とし、第２ゲート２２を
３００μｍのゲート幅とし、２３をドレインとする。２
４は第１ゲート２１と第２ゲート２２間のオーミック金
属である。これを第４図の従来例のものと比較すると、
ゲート幅は第１ゲート２１′、第２ゲート２２′ とも
３００μ−であったのに対し、本発明の第３図では第１
ゲート２１のゲート幅が２倍の６００μｌになっている
。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Third
The figure does not show a chip pattern diagram in one embodiment of the present invention. A bonding pad is provided on the source 20, the first gate 21 has a gate width of 600 μI, the second gate 22 has a gate width of 300 μm, and 23 is the drain. 2
4 is an ohmic metal between the first gate 21 and the second gate 22. Comparing this with the conventional example shown in Figure 4,
The gate width was 300 μ- for both the first gate 21' and the second gate 22', whereas in the case of FIG.
The gate width of the gate 21 is doubled to 600 μl.
信号入力として、周波数７００ＭＨｚ、信号強度−２０
ｄＢｍを入力し、８００ＭＨｚ 、 ＋ｌＯｄ Ｂｍの
局発信号を入力した時、１００Ｍ ＨＺの中間信号強度
を計った時の変換利得は、第５図に示づように、第１ゲ
ート幅を２倍にしてもほとんど変わらない。As signal input, frequency 700MHz, signal strength -20
dBm, input a local oscillation signal of 800 MHz, +lOd Bm, and measure the intermediate signal strength of 100 MHz, the conversion gain is calculated by doubling the first gate width, as shown in Figure 5. However, there is almost no difference.
しかし、さらに妨害信号７０１Ｍ Ｈｚ −２０ｄ Ｂ
ｍを入力した時の３次歪を測定すると、第６図のよう
に第１ゲート幅を２倍にすることによって、３次歪抑圧
比は対中間信号強度比で６０ｄ Ｂから６６ＣＩ Ｂま
でに改善される。また第１ゲートを９００μｍとして３
倍にすると、３次歪は抑圧比はざらに７０ｄＢまでに改
善される。However, in addition, the interference signal 701MHz -20dB
When measuring the third-order distortion when inputting m, by doubling the first gate width as shown in Figure 6, the third-order distortion suppression ratio increases from 60 dB to 66 CI B in terms of the intermediate signal strength ratio. Improved. In addition, the first gate is 900 μm and 3
When doubled, the third-order distortion suppression ratio is roughly improved to 70 dB.
ここで、本発明では第１グー１−幅のみ増大したが、第
２ゲート幅も増大してしまうと消費電流が大ぎくなり、
消′ｐ！電力が増大する欠点がある。ちなみに、第２ゲ
ーを１重３倍にすると、消費電流は１／１０ぼとにまで
小さくなる。つまり、第１ゲートのグー１〜幅だけを第
２ゲートのゲート幅に対して広げることは、消費電力を
小さく保ったままで、歪み特性を著しく改善することに
なる。Here, in the present invention, only the first gate width is increased, but if the second gate width is also increased, the current consumption becomes large.
Extinguish p! It has the disadvantage of increased power consumption. By the way, if the second game is multiplied by 1x3, the current consumption will be reduced to about 1/10. In other words, widening only the width of the first gate with respect to the gate width of the second gate significantly improves the distortion characteristics while keeping the power consumption small.
ところで、この実施例では単一のデュアル・ゲートＦＥ
Ｔミキサーあるいは変調器について説明したが、２次歪
などの偶数次高調彼等を低Ｍづる際は、本発明のデュア
ル・ゲートＦＥＴを用いて第２図のダブル・バランスド
・ミキサーあるいは２重平衡変調回路を（構成すること
が可能である。By the way, in this embodiment, a single dual gate FE
Although the T mixer or modulator has been explained, when even-order harmonics such as second-order distortion are to be reduced to a low M, the dual gate FET of the present invention is used to create a double balanced mixer or a double balanced mixer as shown in Figure 2. It is possible to construct a balanced modulation circuit.
発明の効果
以上のように、本発明はデュアル・ゲーｈ Ｆ ＥＴの
第１ゲート幅を第２ゲート幅より良くすることによって
、ミキサーや変調器として使用し１重時の消費電力を小
さく保ったまま、３次歪等の高調波歪を著しく低減でき
る優れたデュアル・ゲートＦＥＴを実現できるものであ
る。Effects of the Invention As described above, the present invention makes the first gate width of the dual-game hFET better than the second gate width, thereby keeping power consumption small when used as a mixer or modulator. However, it is possible to realize an excellent dual gate FET that can significantly reduce harmonic distortion such as third-order distortion.
第１図はデュアル・ゲートＦＥＴミキサーの回路図、第
２図はダブル・バランスド・デュアル・ゲートＦＥＴミ
キサーの回路図、第３図は本発明の一実施例におけるデ
ュアル・ゲートＦＥＴのチップパターン図、第４図は従
来例のデュアル・ゲートＦＥＴのチップパターン図、第
５図は変換利得特性図、第６図は３次歪特性図である。
２０・・・ソース、２１・・・第１ゲート、２２・・・
第２ゲート、２３・・・トレイン、２４・・・オーミッ
ク金属。
代理人 森 本 義 弘
第１図
第２図
第３図
第４図Figure 1 is a circuit diagram of a dual gate FET mixer, Figure 2 is a circuit diagram of a double balanced dual gate FET mixer, and Figure 3 is a chip pattern diagram of a dual gate FET in an embodiment of the present invention. , FIG. 4 is a chip pattern diagram of a conventional dual gate FET, FIG. 5 is a conversion gain characteristic diagram, and FIG. 6 is a third-order distortion characteristic diagram. 20... Source, 21... First gate, 22...
2nd gate, 23...train, 24...ohmic metal. Agent Yoshihiro Morimoto Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
ル・ゲート電界効果トランジスタ。1. A dual gate field effect transistor in which the first gate width is larger than the second gate width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16520984A JPS6142964A (en) | 1984-08-07 | 1984-08-07 | Dual gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16520984A JPS6142964A (en) | 1984-08-07 | 1984-08-07 | Dual gate field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6142964A true JPS6142964A (en) | 1986-03-01 |
Family
ID=15807912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16520984A Pending JPS6142964A (en) | 1984-08-07 | 1984-08-07 | Dual gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142964A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263249A (en) * | 1985-05-17 | 1986-11-21 | Nec Corp | Semiconductor device |
| EP0610564A2 (en) * | 1993-01-26 | 1994-08-17 | Sumitomo Electric Industries, Ltd. | Dual gate fet and circuits using dual gate fet |
| DE4444808B4 (en) * | 1993-12-17 | 2005-12-15 | Denso Corp., Kariya | Semiconductor device |
-
1984
- 1984-08-07 JP JP16520984A patent/JPS6142964A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263249A (en) * | 1985-05-17 | 1986-11-21 | Nec Corp | Semiconductor device |
| EP0610564A2 (en) * | 1993-01-26 | 1994-08-17 | Sumitomo Electric Industries, Ltd. | Dual gate fet and circuits using dual gate fet |
| EP0610564A3 (en) * | 1993-01-26 | 1995-01-25 | Sumitomo Electric Industries | Dual gate fet and circuits using dual gate fet. |
| DE4444808B4 (en) * | 1993-12-17 | 2005-12-15 | Denso Corp., Kariya | Semiconductor device |
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