JPH031842B2 - - Google Patents
Info
- Publication number
- JPH031842B2 JPH031842B2 JP57206656A JP20665682A JPH031842B2 JP H031842 B2 JPH031842 B2 JP H031842B2 JP 57206656 A JP57206656 A JP 57206656A JP 20665682 A JP20665682 A JP 20665682A JP H031842 B2 JPH031842 B2 JP H031842B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- signal input
- effect transistors
- field effect
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 claims description 17
- 230000000694 effects Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 claims 1
- 230000010355 oscillation Effects 0.000 description 14
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1441—Balanced arrangements with transistors using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1483—Balanced arrangements with transistors comprising components for selecting a particular frequency component of the output
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0001—Circuit elements of demodulators
- H03D2200/0011—Diodes
- H03D2200/0013—Diodes connected in a ring configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/0088—Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplitude Modulation (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電界効果トランジスタ回路に、特に局
発信号の低電力化を実現し、歪特性を改善した高
周波平衡ミキサ回路（以下バランスド・ミキサー
とよぶ）に係る。[Detailed Description of the Invention] Industrial Application Field The present invention applies to field-effect transistor circuits, especially high-frequency balanced mixer circuits (hereinafter referred to as balanced mixers) that realize low power consumption of local oscillator signals and improve distortion characteristics. ).
従来例の構成とその問題点
ミキサーの歪特性を良好にする方法として、従
来、バランス構成が周知である。一例としてシリ
コン・ダイオード１を４個リング状に並べたリン
グ平衡変調回路を第１図に示す。２は局発信号入
力端、４は信号入力端、３は中間周波数信号出力
端である。最近、同回路において高周波特性を向
上させるために優れた高周波特性を有する
GaAsMES・FETを用いて、第２図，第３図に
示すようなGaAs集積回路バランスド・ミキサー
が開発されている。Conventional configuration and its problems A balanced configuration is conventionally known as a method for improving the distortion characteristics of a mixer. As an example, a ring balanced modulation circuit in which four silicon diodes 1 are arranged in a ring shape is shown in FIG. 2 is a local signal input terminal, 4 is a signal input terminal, and 3 is an intermediate frequency signal output terminal. Recently, in order to improve high frequency characteristics in the same circuit, it has excellent high frequency characteristics.
GaAs integrated circuit balanced mixers as shown in Figures 2 and 3 have been developed using GaAsMES/FETs.
第２図において、７と８はそれぞれ信号入力端
と逆相信号入力端であり、９と１０はそれぞれ局
発信号入力端と逆相局発信号入力端である。そし
て、５と６はそれぞれドレイン・バイアスとソー
ス・バイアスのバイアス端、１１は中間周波数出
力端である。しかし、このバランスド・ミキサー
では中間周波数出力端１１のみが出力端で、同相
の出力しか得られないために、第２高周波歪が打
ち消されない欠点がある。 In FIG. 2, 7 and 8 are a signal input terminal and a negative phase signal input terminal, respectively, and 9 and 10 are a local oscillation signal input terminal and a negative phase local oscillation signal input terminal, respectively. Further, 5 and 6 are bias terminals for drain bias and source bias, respectively, and 11 is an intermediate frequency output terminal. However, in this balanced mixer, only the intermediate frequency output end 11 is the output end, and only the in-phase output can be obtained, so that the second high frequency distortion is not canceled out.
この第２高周波歪を打ち消すために、第３図に
示すように、４個のFETを用いたダブル・バラ
ンス構成にし、同時に変換利得を上げるため、信
号を一旦FETで増幅した後、ソースから注入す
る回路が良く用いられている。第３図で入力信号
及び逆相入力信号はそれぞれ増幅器の入力ゲート
１６，１７から入力される。１４，１５はそれぞ
れ局発信号入力端及び逆相局発信号入力端であり
１２，１３はそれぞれ中間周波数信号出力端とそ
の逆相出力端である。逆相中間周波数信号の出力
をさらに位相反転して、中間周波数信号出力と合
成することによつて、第２高周波歪は抑圧され
る。しかし、このように増幅器をつけると、ミキ
サーの変換利得は上げることができるが、歪が大
きくなる欠点がある。また、局発入力として、
10mW程度のパワーが必要であり、局発信号が大
きくなり、歪が大きくなつてしまう。 In order to cancel this second high-frequency distortion, as shown in Figure 3, a double-balanced configuration using four FETs is used.At the same time, in order to increase the conversion gain, the signal is first amplified by the FETs and then injected from the source. Circuits that do this are often used. In FIG. 3, the input signal and the negative phase input signal are input from the input gates 16 and 17 of the amplifier, respectively. Reference numerals 14 and 15 are a local oscillation signal input terminal and an opposite phase local oscillation signal input end, respectively, and 12 and 13 are an intermediate frequency signal output end and its opposite phase output end, respectively. The second high frequency distortion is suppressed by further inverting the phase of the output of the negative phase intermediate frequency signal and combining it with the intermediate frequency signal output. However, although adding an amplifier in this way can increase the conversion gain of the mixer, it has the disadvantage of increasing distortion. Also, as a local input,
A power of about 10mW is required, which increases the local oscillation signal and increases distortion.
発明の目的
本発明は以上の欠点を除去し、低歪でかつ、小
さな局発入力で、大きな変換利得が得られる高周
波平衡ミキサ回路の構造を提供することを目的と
するものである。OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a structure of a high frequency balanced mixer circuit that can obtain a large conversion gain with low distortion and a small local oscillator input.
発明の構成
本発明の高周波平衡ミキサ回路は第１，第２，
第３，第４の４個のデユアルゲート電界効果トラ
ンジスタのソース端子が共通接続され、前記第１
および第２の電界効果トランジスタのドレイン端
子、前記第３および第４の電界効果トランジスタ
のドレイン端子がそれぞれ共通接続され、前記第
１および第３の電界効果トランジスタの第１ゲー
ト、前記第２および第４の電界効果トランジスタ
の第１ゲート、前記第１および第４の電界効果ト
ランジスタの第２ゲート、前記第２および第３の
電界効果トランジスタの第２ゲートがそれぞれ共
通接続され、前記第１ゲートの２組の共通ゲート
端子にたがいに逆位相の第１信号を入力するとと
もに、前記第２ゲートの２他の共通ゲート端子に
たがいに逆位相の第２の信号を入力して、平衡変
調させるものかもしくはミキサ動作させるもので
ある。Configuration of the Invention The high frequency balanced mixer circuit of the present invention has first, second,
The source terminals of the third and fourth four dual-gate field effect transistors are commonly connected, and the first
and the drain terminals of the second field effect transistor and the drain terminals of the third and fourth field effect transistors are connected in common, and the first gate of the first and third field effect transistor, the first gate of the second and The first gates of the four field effect transistors, the second gates of the first and fourth field effect transistors, and the second gates of the second and third field effect transistors are respectively commonly connected, and the first gate of the first gate Balanced modulation is achieved by inputting first signals with opposite phases to two sets of common gate terminals, and inputting second signals with opposite phases to two other common gate terminals of the second gate. It is also possible to operate a mixer.
実施例の説明
以下図面をもとにして本発明の実施例の電界効
果トランジスタ回路について説明する。DESCRIPTION OF EMBODIMENTS Field effect transistor circuits according to embodiments of the present invention will be described below with reference to the drawings.
第４図はGaAsデユアル・ゲートFETミキサー
をダブル・バランスド構成にしたものである。こ
こで２２と２３はそれぞれ信号入力端と逆相信号
入力端、２０と２１はそれぞれ局発信号入力端と
その逆相信号入力端、１８と１９はそれぞれ中間
周波数出力端とその逆相出力端である。第３図の
ダブル・バランスド・ミキサーと同様に、２つの
出力端１８，１９のうち、出力端１９の出力をさ
らに位相反転して、出力端１８の出力と合成する
ことによつて、第２高調波歪が抑圧される。本発
明の実施例のダブル・バランスド・ミキサーはデ
ユアル・ゲートFETを用いているため、ミキサ
ーの変換利得を大きくとることができ、第３図の
回路よりも局発信号入力が小さくてすむ。また、
増幅器が付いていないので、歪特性も第３図の回
路よりも良好になるなどの特徴がある。 Figure 4 shows a GaAs dual gate FET mixer in a double balanced configuration. Here, 22 and 23 are a signal input terminal and a negative phase signal input terminal, respectively, 20 and 21 are a local oscillator signal input terminal and its negative phase signal input terminal, respectively, and 18 and 19 are an intermediate frequency output terminal and its negative phase output terminal, respectively. It is. Similar to the double balanced mixer shown in FIG. 3, of the two output ends 18 and 19, the output from the output end 19 is further phase-inverted and combined with the output from the output end 18. Second harmonic distortion is suppressed. Since the double balanced mixer of the embodiment of the present invention uses dual gate FETs, the conversion gain of the mixer can be increased, and the local oscillator signal input can be smaller than that of the circuit shown in FIG. Also,
Since it does not include an amplifier, it has features such as better distortion characteristics than the circuit shown in Figure 3.
第５図は本発明の他の実施例を示してあり、ダ
ブル・バランスド・ミキサーにGaAsMESFET
で構成した差動増幅回路を直結させた回路であ
り、１チツプ・モノリシツク化が可能である。
Vssバイアス２７でバイアス点を調整し端子２６
にドレイン・バイアスを加え、端子２８に入力す
る信号のバイアスと同じ直流バイアスを加え、端
子３０と２９にそれぞれ入力信号と局発信号を入
力すれば、左右の差動増幅回路で互いに位相が反
転された相補出力が、本発明に係るダブル・バラ
ンスド・ミキサーに入力され、端子２４と２５か
らそれぞれ中間周波数信号と逆相中間周波数信号
が得られる。 FIG. 5 shows another embodiment of the present invention, in which a double balanced mixer includes GaAs MESFETs.
This is a circuit that directly connects a differential amplifier circuit composed of the following, and can be made into a single-chip monolithic structure.
Adjust the bias point with Vss bias 27 and terminal 26
By adding a drain bias to , applying the same DC bias as the bias of the signal input to terminal 28, and inputting the input signal and local oscillation signal to terminals 30 and 29, respectively, the phases of the left and right differential amplifier circuits will be reversed. The complementary outputs thus obtained are input to the double balanced mixer according to the present invention, and an intermediate frequency signal and an opposite phase intermediate frequency signal are obtained from terminals 24 and 25, respectively.
次に、本発明の一実施例としてのGaAsMES・
FET集積回路について述べる。本実施例の平衡
変調回路のマスク・パターン図を第６図に示す。
設計したデユアル・ゲートFETは、ゲート長
1μm、ゲート幅300μmである。このときコンバー
ジヨン・ゲイン＋10dBが得られた。差動増幅回
路のゲート幅は100μmで設計した。GaAsウエハ
ーは、半絶縁性高抵抗GaAs基板上に、エピタキ
シヤル層を堆積したウエハーと、選択イオン注入
したウエハーを用いた。また、ゲート金属はCr
−Pt−Auの３層構造を用い、ソース，ドレイン
のオーミツク金属はAuGe−Auの２層構造を用
いた。第６図で、３４はソースの共通接続であ
り、３１と３５はドレインで、それぞれ中間周波
数出力とその逆位相出力である。３３と３７は第
１ゲートで、それぞれ信号入力端とその逆位相入
力端である。３２と３６は第２ゲートで、それぞ
れ局発信号入力端とその逆位相入力端である。作
製したGaAsMES・FET・集積回路によるダブ
ル・バランスド・ミキサーは小さい局発信号入力
で、十分なコンバージヨンが得られた。 Next, a GaAsMES/
Let's talk about FET integrated circuits. FIG. 6 shows a mask pattern diagram of the balanced modulation circuit of this embodiment.
The designed dual gate FET has a gate length
1μm, gate width 300μm. At this time, a conversion gain of +10 dB was obtained. The gate width of the differential amplifier circuit was designed to be 100 μm. The GaAs wafers used were a wafer with an epitaxial layer deposited on a semi-insulating high-resistance GaAs substrate, and a wafer with selective ion implantation. Also, the gate metal is Cr
A three-layer structure of -Pt-Au was used, and a two-layer structure of AuGe-Au was used for the source and drain ohmic metals. In FIG. 6, 34 is a common source connection, and 31 and 35 are drains, which are an intermediate frequency output and an opposite phase output, respectively. 33 and 37 are first gates, which are a signal input terminal and an opposite phase input terminal thereof, respectively. 32 and 36 are second gates, which are a local oscillator signal input terminal and an opposite phase input terminal thereof, respectively. The fabricated double balanced mixer using GaAsMES, FETs, and integrated circuits was able to achieve sufficient conversion with a small local oscillator signal input.
なお、以上の説明でバランスド・ミキサーで説
明したが、同様の回路を用いて、変調器として働
かせることももちろん可能である。このときは局
発信号をキヤリア信号と考えればよい。また、前
述の説明では、局発信号を第２ゲート、入力信号
を第１ゲートに入力したが、これを入れかえても
同様に動作が可能である。 Note that although the above explanation is based on a balanced mixer, it is of course possible to use a similar circuit to function as a modulator. In this case, the local signal can be considered as a carrier signal. Further, in the above description, the local oscillator signal was input to the second gate and the input signal was input to the first gate, but the same operation is possible even if these are exchanged.
また、以上はGaAsMESFETで説明したが、
他の化合物半導体FET、あるいはシリコンFET
を用いても、もちろん可能である。 Also, although the above was explained using GaAsMESFET,
Other compound semiconductor FETs or silicon FETs
Of course, it is also possible to use .
発明の効果
以上のように、本発明のダブル・バランスド・
ミキサー回路はソース共通のデユアル・ゲート
FETで構成され、コンバージヨン・ゲインが高
く、歪特性が良好で、小さい局発信号入力で働く
などの利点がある。本発明のダブル・バランス
ド・ミキサー回路を平衡変調動作させる場合も、
変換利得が高く、歪特性が良好で、小さいキヤリ
ア信号入力で働く利点がある。Effects of the invention As described above, the double balanced
Mixer circuit is dual gate with common source
It is composed of FETs and has the advantages of high conversion gain, good distortion characteristics, and the ability to work with small local oscillator signal inputs. When operating the double balanced mixer circuit of the present invention in balanced modulation mode,
It has the advantages of high conversion gain, good distortion characteristics, and works with a small carrier signal input.
第１図は従来のリング平衡変調回路図、第２
図，第３図はそれぞれ従来のバランスド・ミキサ
ー回路図、第４図は本発明の実施例におけるデユ
アル・ゲートFETを用いたダブル・バランス
ド・ミキサー回路図、第５図は本発明の他の実施
例における入力端に位相反転回路のついたダブ
ル・バランスド・ミキサー回路図、第６図は本発
明の実施例のダブル・バランスド・ミキサー回路
のマスク・パターン図である。
１……Siダイオード、２……局発信号入力端、
３……中間周波数信号出力端、４……信号入力
端、５……ドレイン・バイアス、６……ソース・
バイアス、７……信号入力端、８……逆相信号入
力端、９……局発信号入力端、１０……逆相局発
信号入力端、１１……中間周波数信号入力端、１
２……中間周波数信号出力端、１３……逆相出力
端、１４……局発信号入力端、１５……逆相局発
信号入力端、１６……信号入力端、１７……逆相
信号入力端、１８……中間周波数信号出力端、１
９……逆相中間周波数信号出力端、２０……局発
信号入力端、２１……逆相局発信号入力端、２２
……信号入力端、２３……逆相信号入力端、２４
……中間周波数信号出力端、２５……逆相中間周
波数出力端、２６……ドレイン・バイアス、２７
……ソース・バイアス、２８……ゲート・バイア
ス、２９……局発信号入力端、３０……信号入力
端、３１……中間周波数出力端ドレイン、３２…
…局発信号入力端第２ゲート、３３……信号入力
端第１ゲート、３４……ソース共通接続端、３５
……逆相中間周波数出力端ドレイン、３６……逆
相局発信号入力端第２ゲート、３７……逆相信号
入力端第１ゲート。
Figure 1 is a conventional ring balance modulation circuit diagram;
3 and 3 are respectively circuit diagrams of a conventional balanced mixer, FIG. 4 is a circuit diagram of a double balanced mixer using dual gate FETs according to an embodiment of the present invention, and FIG. 5 is a circuit diagram of a conventional balanced mixer using dual gate FETs. FIG. 6 is a diagram of a double balanced mixer circuit with a phase inversion circuit at the input end in the embodiment of the present invention. FIG. 6 is a mask pattern diagram of the double balanced mixer circuit of the embodiment of the present invention. 1...Si diode, 2...Local oscillator signal input terminal,
3...Intermediate frequency signal output terminal, 4...Signal input terminal, 5...Drain/bias, 6...Source/
Bias, 7...Signal input end, 8...Reverse phase signal input end, 9...Local oscillation signal input end, 10...Reverse phase local oscillation signal input end, 11...Intermediate frequency signal input end, 1
2...Intermediate frequency signal output end, 13...Reverse phase output end, 14...Local oscillation signal input end, 15...Reverse phase local oscillation signal input end, 16...Signal input end, 17...Reverse phase signal Input end, 18...Intermediate frequency signal output end, 1
9...Reverse phase intermediate frequency signal output end, 20...Local oscillation signal input end, 21...Reverse phase local oscillation signal input end, 22
... Signal input terminal, 23 ... Reverse phase signal input terminal, 24
...Intermediate frequency signal output end, 25...Reverse phase intermediate frequency output end, 26...Drain bias, 27
...Source bias, 28...Gate bias, 29...Local oscillation signal input terminal, 30...Signal input terminal, 31...Intermediate frequency output terminal drain, 32...
...Local signal input terminal second gate, 33...Signal input terminal first gate, 34...Source common connection terminal, 35
...Reverse phase intermediate frequency output terminal drain, 36...Reverse phase local oscillation signal input end second gate, 37...Reverse phase signal input end first gate.
Claims (1)
ート電界効果トランジスタのソース端子が共通接
続され、前記第１および第２の電界効果トランジ
スタのドレイン端子、前記第３および第４の電界
効果トランジスタのドレイン端子がそれぞれ共通
接続され、前記第１および第３の電界効果トラン
ジスタの第１ゲート、前記第２および第４の電界
効果トランジスタの第１ゲート、前記第１および
第４の電界効果トランジスタの第２ゲート、前記
第２および第３の電界効果トランジスタの第２ゲ
ートがそれぞれ共通接続され、前記第１ゲートの
２組の共通ゲート端子にたがいに逆位相の第１信
号を入力するとともに、前記第２ゲートの２組の
共通ゲート端子にたがいに逆位相の第２の信号を
入力して、平衡度変調させるかもしくはミキサ動
作させることを特徴とする電界効果トランジスタ
回路。1 The source terminals of four dual-gate field effect transistors, first, second, third, and fourth, are commonly connected, and the drain terminals of the first and second field-effect transistors, the third and fourth dual-gate field-effect transistors are connected in common. Drain terminals of the field effect transistors are each commonly connected, first gates of the first and third field effect transistors, first gates of the second and fourth field effect transistors, and first and fourth electric fields. A second gate of the effect transistor and second gates of the second and third field effect transistors are respectively commonly connected, and first signals having opposite phases are input to two sets of common gate terminals of the first gate. A field effect transistor circuit characterized in that second signals having opposite phases are inputted to two sets of common gate terminals of the second gate to perform balance modulation or mixer operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57206656A JPS5995705A (en) | 1982-11-24 | 1982-11-24 | Field effect transistor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57206656A JPS5995705A (en) | 1982-11-24 | 1982-11-24 | Field effect transistor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5995705A JPS5995705A (en) | 1984-06-01 |
| JPH031842B2 true JPH031842B2 (en) | 1991-01-11 |
Family
ID=16526957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57206656A Granted JPS5995705A (en) | 1982-11-24 | 1982-11-24 | Field effect transistor circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5995705A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2563286B2 (en) * | 1986-12-05 | 1996-12-11 | 松下電器産業株式会社 | Frequency mixing circuit |
| US4768000A (en) * | 1987-04-13 | 1988-08-30 | Texas Instruments Incorporated | Monolithic double balanced single sideband modulator |
| JPH0583040A (en) * | 1991-09-24 | 1993-04-02 | Japan Radio Co Ltd | Phase comparator |
| JPH05191151A (en) * | 1992-01-14 | 1993-07-30 | Nec Corp | Frequency mixer circuit |
| US5767726A (en) * | 1996-10-21 | 1998-06-16 | Lucent Technologies Inc. | Four terminal RF mixer device |
| DE10261388B4 (en) * | 2002-12-30 | 2012-03-01 | Infineon Technologies Ag | Circuit for setting operating point of multiple gate field effect transistors |
-
1982
- 1982-11-24 JP JP57206656A patent/JPS5995705A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5995705A (en) | 1984-06-01 |
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