JPS61263116A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61263116A
JPS61263116A JP60104644A JP10464485A JPS61263116A JP S61263116 A JPS61263116 A JP S61263116A JP 60104644 A JP60104644 A JP 60104644A JP 10464485 A JP10464485 A JP 10464485A JP S61263116 A JPS61263116 A JP S61263116A
Authority
JP
Japan
Prior art keywords
integrated circuit
pad
wafer
semiconductor chip
scribe line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60104644A
Other languages
Japanese (ja)
Inventor
Osamu Yamanada
山名田　修
Michitomo Iiyama
飯山　道朝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP60104644A priority Critical patent/JPS61263116A/en
Publication of JPS61263116A publication Critical patent/JPS61263116A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To enable the effective use of a wafer by enabling to use the area for a discriminating element for an integrated circuit since the discriminating element is on a scribe line and not in a region which is to be made a semiconductor chip and the scribe line is lost by scribing. CONSTITUTION:An integrated circuit 2 is installed on a semiconductor chip 1 and a region which is to be made the semiconductor chip on a wafer is enclosed with full lines 11-14. After scribing, the region enclosed with the full lines 11-14 is made the chip 1, the outside of the full lines 11-14 is a scribe line 3 and when the wafer is scribed, the wafer is cut at this region and the region is lost. A discriminating element 4 is formed in the scribe line 3. The element remains in the semiconductor chip 1 even after scribed but a specific pad 5 for discrimination is provided outside of the integrated circuit and an appropriate pad is selected in the integrated circuit and is made a pad 6 for measurement. The discriminating element 4 in the scribe line 3 is connected to the specific pad 5 for discrimination and the pad 6 for measurement in the integrated circuit with wirings 7, 8.

Description

【発明の詳細な説明】 例技術分野 この発明は、集積回路の種類を示すだめの識別素子を、
集積回路の外部に設け、半導体ウエハの面積の有効利用
を企るものである。DETAILED DESCRIPTION OF THE INVENTION EXAMPLE TECHNICAL FIELD This invention provides an identification element for indicating the type of integrated circuit.
It is provided outside the integrated circuit and aims to make effective use of the area of the semiconductor wafer.

（イ）従来技術 半導体ウエハには、ウエハブロセスによって、数多くの
同一の集積回路が作られる。集積回路が作製された後、
所定のスクライブラインに沿ってウエハを切断し、数多
くのチップに分割する。(a) Prior Art A large number of identical integrated circuits are fabricated on a semiconductor wafer through a wafer process. After the integrated circuit is created,
The wafer is cut along predetermined scribe lines and divided into many chips.

集積・回路にも故多くの種類があり、集積回路製造工程
に放て、どのような集積回路であるのかを容易に同定で
きるようになっているのが望ましい。There are many types of integrated circuits and circuits, and it is desirable to be able to easily identify what type of integrated circuit it is during the integrated circuit manufacturing process.

ウエハの中では、全て同じ集積回路が作られる場合は、
識別素子をウエハについてひとつ設ければよい。ところ
がウエハ１枚の上に、複数の種類の集積回路を作ること
もある。このような場合は、集積回路のそれぞれに種類
を識別するための識別用の素子を設ける必要がある。When all the same integrated circuits are made on a wafer,
One identification element may be provided per wafer. However, multiple types of integrated circuits may be fabricated on a single wafer. In such a case, it is necessary to provide each integrated circuit with an identification element for identifying its type.

半導体ウエハの上には、全く同じものを繰返して作製す
る、という事が多いので、いずれの場合でも、集積回路
のそれぞれに、集積回路識別素子を設ける事が多い。Since exactly the same circuits are often repeatedly manufactured on a semiconductor wafer, in any case, each integrated circuit is often provided with an integrated circuit identification element.

第３図は従来の半導体チップの略平面図である。FIG. 3 is a schematic plan view of a conventional semiconductor chip.

１枚のウェハ（／Ｃ１ウェハプロセスによって数多くの
集積回路を作製した後、縦横にウェハをスクライプした
後のひとつの半導体チップ２０である。A single wafer (/C1) A single semiconductor chip 20 is obtained by fabricating a large number of integrated circuits using a wafer process and then scribing the wafer in the vertical and horizontal directions.

破線で囲んだ部分が集積回路２１である。この部分が有
効に利用される。The part surrounded by the broken line is the integrated circuit 21. This part will be used effectively.

半導体チップ２０の一隅には、集積回路の一部を構成し
ない非集積回路領域２２が存在する。At one corner of the semiconductor chip 20, there is a non-integrated circuit region 22 that does not form part of the integrated circuit.

ここには、集積回路の種類を識別するための識別素子２
３と、゛その両側に、識別素子測定用バッド２４．２５
が設けである。Here, there is an identification element 2 for identifying the type of integrated circuit.
3 and 24 and 25 identification element measurement pads on both sides.
is the provision.

識別素子２３と、識別素子測定用バッド２４．２５とは
配線２７，２８によって接続されている。The identification element 23 and the identification element measurement pads 24 and 25 are connected by wirings 27 and 28.

スクライプライン２６によって囲まれた長方形の半導体
チップ２０の中に、このように、識別素子２３が設けら
れる。In this way, the identification element 23 is provided in the rectangular semiconductor chip 20 surrounded by the scribe line 26.

オートプローパを使って、識別素子測定用バッド２４．
２５をプローブ針で押え、抵抗、電流、その他の、パラ
メータを測定することによシ、それが属する集積回路の
種類を識別する。Using an autoproper, identify the identification element measurement pad 24.
25 with a probe needle and measuring resistance, current, and other parameters identifies the type of integrated circuit to which it belongs.

このような半導体チップの構造は、識別素子２３がチッ
プ内にあるので、ウェハの全面が有効に利用されていな
い、という欠点がある。This semiconductor chip structure has the disadvantage that the entire surface of the wafer is not effectively utilized because the identification element 23 is located within the chip.

り）構　成 本発明の半導体装置は、半導体チップとして残る部分で
はなく、スクライプラインの上に、識別素子を形成する
。こうすることにより、ウェハの面積金より有効に利用
する事ができる。i) Structure In the semiconductor device of the present invention, an identification element is formed not on a portion that remains as a semiconductor chip but on a scribe line. By doing so, the area of the wafer can be used more effectively.

第１図は本発明の半導体装置の一部平面図である。ウェ
ハの上には、同じものが縦横に多数製作されているわけ
であるが、ここではひとつ分の半導体チップ１とその周
辺のみを示す。FIG. 1 is a partial plan view of the semiconductor device of the present invention. On a wafer, many identical semiconductor chips are fabricated horizontally and vertically, but only one semiconductor chip 1 and its surroundings are shown here.

、半導体チップ１の上に集積回路２が設けられるのは、
従来のものと同様である。, the integrated circuit 2 is provided on the semiconductor chip 1 because
It is the same as the conventional one.

この図はウェハ上の半導体チップとなるべき領ｆｆＡを
実線１１．１２．１３．１４で囲んでいる。しかし、ス
クライプする前にこのような境界があるわけてはない。In this figure, the area ffA on the wafer that is to become a semiconductor chip is surrounded by solid lines 11, 12, 13, and 14. However, there is no such boundary before scriping.

スクライプしてしまえば、実線１１〜１４で囲まれるチ
ップ１になるのである。切断予定線ということができる
。実線１１〜１４の外側がスクライプライン３である。After scribing, the chip 1 will be surrounded by solid lines 11 to 14. It can be called the planned cutting line. The outside of the solid lines 11 to 14 is the scribe line 3.

ウェハをスクライプする時、この部分で切断され、この
部分が失われることもある。When scribing the wafer, it may be cut at this area and may be lost.

重要な事は、スクライプライン３の中に識別素子４を形
成した、という事である。What is important is that the identification element 4 is formed within the scribe line 3.

スクライプした後も、半導体チップ１の中に伐る部分で
あるが、集積回路の外部に、識別用特設バッド５を設け
る。Even after scribing, a special identification pad 5 is provided outside the integrated circuit, although this is the part cut inside the semiconductor chip 1.

また、集積回路の中の適当なバッドを選びこれを測定用
バッド６とする。Further, a suitable pad in the integrated circuit is selected and used as the measurement pad 6.

スクライプライン３の中にある識別素子４と、識別用特
設バッド５、集積回路内の測定用パッド６とを配線７．
８によって接続する。Wiring 7. connects the identification element 4 in the scribe line 3, the special identification pad 5, and the measurement pad 6 in the integrated circuit.
Connect by 8.

識別素子４の例を第２図によって説明する。An example of the identification element 4 will be explained with reference to FIG.

これは抵抗の値によって、集積回路に標識を付するもの
である。抵抗の他にも標識は存在しうるが、ここでは抵
抗標識を採用している。This tags integrated circuits by the value of their resistance. Although there may be other signs besides resistance, we use resistance signs here.

同一の単位抵抗１０が、複数個スクライプラインの中に
、拡散によって設けられている。ここでは打点を付した
領域である。単位抵抗をｒｌ　、ｒ２・・・、ｒｎとか
く。両端のｒｌ、ｒｌＫは、識別用特設バッド５と集積
回路内の測定用パッド６につながる配線７．８が設けら
れている。A plurality of identical unit resistors 10 are provided in the scribe line by diffusion. Here, it is a dotted area. Let the unit resistances be rl, r2..., rn. At both ends rl and rlK, wiring 7.8 is provided which connects to the special identification pad 5 and the measurement pad 6 in the integrated circuit.

単位抵抗１０の両端には、コンタクトホール１９．１９
がある。Contact holes 19 and 19 are provided at both ends of the unit resistor 10.
There is.

単位抵抗は中間の配線１５．１６．１７によって接続さ
れるが、単位抵抗ｒ４のように、短絡配線１８によって
短絡されている抵抗もある。The unit resistors are connected by intermediate wires 15, 16, 17, but some resistors, like the unit resistor r4, are short-circuited by the short-circuit wire 18.

結局ｎ個の単位抵抗があれば、この内適当な抵抗を短絡
させることによって、全抵抗Ｒが。、ｒ、２ｒ１・・・
、ｎｒの（ｎ＋１）種類の値をとシうることになる。そ
うすると、これによって（ｎ＋１）種類の標識ができる
ことになる。After all, if there are n unit resistors, the total resistance R can be reduced by short-circuiting appropriate resistors among them. , r, 2r1...
, nr of (n+1) types of values can be obtained. In this case, (n+1) types of labels will be created.

これは、全ての単位抵抗の値が同一である場合であるが
、ｒｌ　、ｒ２．・・・の値が異なるようにすれば、も
つと多くの区別できる標識を作る事ができる。This is the case when all unit resistors have the same value, but rl, r2 . By making the values of ... different, it is possible to create a large number of distinguishable signs.

例えば ２　ｒｉ−１＝　ｒ　ｉ　　　（１＝２、・・、ｎ）と
いうように、単位抵抗を設定することができれば２ｎ　
とおりの標識を作ることができる。For example, if a unit resistance can be set, 2n
You can make street signs.

たとえばｎ＝４　　とすると、前者の場合５とおシの標
識を作ることができる。後者の場合１６とおシの標識を
作ることができる。For example, if n=4, in the former case, a 5 and oshi sign can be made. In the latter case, you can make a 16 and Oshi sign.

に）効　果 （１）識別素子がスクライプラインの上にあって、半導
体チップとなるべき部分の中にはない。スクライプライ
ンはスクライプによって失われる部分である。識別製子
分の面積が集積回路のために使用できるよりになる。ウ
エハの有効利用ができる。(2) Effects (1) The identification element is on the scribe line and not in the part that should become the semiconductor chip. Scripe lines are the parts that are lost due to scribing. The area of the identification component becomes more available for integrated circuits. Wafers can be used effectively.

（２）従来は、第３図に示すように、識別素子測定用バ
ッド２４．２５が２つ必要であった。これらのパッドは
、プローブ針で探針するために必要である。しかも集積
回路パッド部分と絶縁されていなければならない。(2) Conventionally, as shown in FIG. 3, two identification element measurement pads 24 and 25 were required. These pads are necessary for probing with the probe needle. Moreover, it must be insulated from the integrated circuit pad portion.

本発明では、非集積回路領域９にひとつの織別用特投バ
ッド５を必要とするだけである。もうひとつの測定用の
パッドとしては集積回路の中の適当なひとつのパッド６
を兼用している。In the present invention, only one special throw pad 5 for weaving is required in the non-integrated circuit area 9. Another measurement pad is an appropriate pad 6 in the integrated circuit.
It is also used as.

後にスクライプライン３に沿ってスクライブすると、こ
の測定用バッド６と識別素子４をつなぐ配線８が切れる
。従って、測定用バッド６は、識別用特設バッド５と絶
縁される。このだめに、集積回路中のパッドを識別素子
測定用バッドとして用いることができるのである。Later, when scribing along the scribe line 3, the wiring 8 connecting the measurement pad 6 and the identification element 4 is cut. Therefore, the measurement pad 6 is insulated from the special identification pad 5. Therefore, pads in the integrated circuit can be used as pads for measuring identification elements.

第３図と第１図とを比較して、結局、集積回路として使
える面積が、識別素子ひとつ分と、識別素子測定用バッ
ドひとつ分だけ増加する。ウエハの有効利用である。Comparing FIG. 3 with FIG. 1, the area usable as an integrated circuit increases by one identification element and one identification element measurement pad. This is effective use of wafers.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の半導体装置のひとつの半導体チップの
近傍のみの拡大平面図。 第２図は識別素子の一例を説明するための拡大平面図。 第３図は従来の半導体チップの概略平面図。 １・・・・・・・・・・・・半導体チップ２・・・・・
・・・・・・・集積回路 ３・・・・・・・・・・・・スクライプライン４・・・
・・・・・・・識別素子 ５・・・・・・・・・・・・識別用特設パッド６・・・
・・・・・・・・集積回路上の測定用バッド７．８・・
・・・・・・配　　線 ９・・・・・・・・・・非集積回路領域１０・・・・・
・・・・・・単位抵抗 発　明　者　　　　両名１）　修 飯山道朝FIG. 1 is an enlarged plan view of only the vicinity of one semiconductor chip of the semiconductor device of the present invention. FIG. 2 is an enlarged plan view for explaining an example of an identification element. FIG. 3 is a schematic plan view of a conventional semiconductor chip. 1... Semiconductor chip 2...
......Integrated circuit 3...Screen line 4...
......Identification element 5...Special identification pad 6...
......Measurement pad on integrated circuit 7.8...
...Wiring 9...Non-integrated circuit area 10...
...Unit resistance inventors both 1) Docho Shueizan

Claims (2)

【特許請求の範囲】[Claims] （１）半導体ウエハの上に設けられた多数の集積回路と
、ウエハがスクライブされた後半導体チップの中に残る
が集積回路とは絶縁されている識別用特設パッドと、ス
クライブラインの上に形成された集積回路の種類を識別
するための標識となる識別素子とよりなり、識別素子の
一端は集積回路中の測定用パッドに、他端は集積回路外
の識別用特設パッドに、配線によつて接続されている事
を特徴とする半導体装置。(1) A large number of integrated circuits provided on a semiconductor wafer, a special identification pad that remains inside the semiconductor chip after the wafer is scribed but is insulated from the integrated circuits, and is formed on the scribe line. One end of the identification element is connected to a measurement pad inside the integrated circuit, and the other end is connected to a special identification pad outside the integrated circuit by wiring. A semiconductor device characterized in that the semiconductor device is connected to each other. （２）識別素子が、拡散によつて形成したｎ個の同一の
単位抵抗と、これらを結ぶ配線と、これらの抵抗を短絡
する配線とよりなつており、全抵抗Ｒが単位抵抗ｒのｉ
倍である事を検出して集積回路の種類を識別する事とし
た特許請求の範囲第（１）項記載の半導体装置。(2) The identification element consists of n identical unit resistances formed by diffusion, wiring connecting them, and wiring shorting these resistances, and the total resistance R is i of the unit resistance r.
2. A semiconductor device according to claim 1, wherein the type of integrated circuit is identified by detecting that the number of times the integrated circuit is doubled.
JP60104644A 1985-05-16 1985-05-16 Semiconductor device Pending JPS61263116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60104644A JPS61263116A (en) 1985-05-16 1985-05-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60104644A JPS61263116A (en) 1985-05-16 1985-05-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61263116A true JPS61263116A (en) 1986-11-21

Family

ID=14386159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60104644A Pending JPS61263116A (en) 1985-05-16 1985-05-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61263116A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051807A (en) * 1987-04-07 1991-09-24 Seiko Epson Corporation Integrated semiconductor structure with incorporated alignment markings
US5214657A (en) * 1990-09-21 1993-05-25 Micron Technology, Inc. Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers
JPH0888203A (en) * 1995-08-21 1996-04-02 Seiko Epson Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051807A (en) * 1987-04-07 1991-09-24 Seiko Epson Corporation Integrated semiconductor structure with incorporated alignment markings
US5214657A (en) * 1990-09-21 1993-05-25 Micron Technology, Inc. Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers
JPH0888203A (en) * 1995-08-21 1996-04-02 Seiko Epson Corp Semiconductor device

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