JPS6170732A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6170732A
JPS6170732A JP59192876A JP19287684A JPS6170732A JP S6170732 A JPS6170732 A JP S6170732A JP 59192876 A JP59192876 A JP 59192876A JP 19287684 A JP19287684 A JP 19287684A JP S6170732 A JPS6170732 A JP S6170732A
Authority
JP
Japan
Prior art keywords
metal
metal wiring
ohmic contact
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59192876A
Other languages
Japanese (ja)
Other versions
JPH0451065B2 (en
Inventor
Yuji Tanaka
裕治 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP59192876A priority Critical patent/JPS6170732A/en
Publication of JPS6170732A publication Critical patent/JPS6170732A/en
Publication of JPH0451065B2 publication Critical patent/JPH0451065B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the electric potential drop in a wiring due to a circuit current and to enable easily detecting the breaking of a metal wire by limiting the ohmic contact region of a metal wiring and a semiconductor chip. CONSTITUTION:A metal wiring 5 has no ohmic contact. That is, the metal wiring 5 has no ohmic contact with a semiconductor chip and is perfectly independent from the other metal wiring 4 so there is no current due to the voltage drop difference of the metal wirings and there is no effect between the circuits. If one wire is broken, the circuit does not operate normally and it is possible to reject a defective article by a simple test.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はグランドインピーダンスを低くする必要のある
半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device that requires low ground impedance.

従来例の構成とその問題点 半導体装置で、ボンディング用ワイヤーのインピーダン
スや半導体チップ上のメタル配線のインピーダンスと回
路電流による電圧降下が問題となる時には、第１図の平
面図に示す従来例のように、リード端子１より金属ワイ
ヤー２，３を２本に分割し、且つメタル配線５．６を独
立させて電圧降下による回路間の影響を低減させている
。この従来例において、等制約に独立であるメタル配線
４゜６間はサブストレートのオーミックコンタクト６゜
７によりＩＣチップ８に対して低抵抗な分布抵抗で接続
されている。しかるに、独立なメタル配線４．５間にそ
れぞれの電圧降下差により電流が流れ、回路間に影響が
発生する。Conventional configuration and its problems In semiconductor devices, when voltage drops due to the impedance of bonding wires, the impedance of metal wiring on semiconductor chips, and circuit currents are a problem, the conventional configuration shown in the plan view of Figure 1 is used. In addition, the metal wires 2 and 3 are divided into two from the lead terminal 1, and the metal wires 5 and 6 are made independent to reduce the influence of voltage drop between circuits. In this conventional example, the metal wiring lines 4.degree.6, which are independent under equal constraints, are connected to the IC chip 8 through ohmic contacts 6.7 of the substrate with a low distributed resistance. However, a current flows between the independent metal wirings 4.5 due to the voltage drop difference between them, causing an effect between the circuits.

また、第１図の従来例忙おいて、一方の金属ワイヤーが
断線していたとしても、残りのメタル配線により、両方
のメタル配線４，５間は、サブストレート間によってリ
ードとは接続されるため、金属ワイヤが断線している事
が判断出来なく、このような初期不良をテストにより除
く事が困難である。In addition, in the conventional example shown in Figure 1, even if one metal wire is disconnected, the remaining metal wiring connects both metal wirings 4 and 5 to the lead between the substrates. Therefore, it is impossible to determine whether the metal wire is disconnected, and it is difficult to eliminate such initial defects by testing.

発明の目的 上記のような不都合を排除し、回路電流による配線部で
の電位降下を少なくし、また、金属ワイヤの断線をも容
易に検出できる半導体集積回路装置を提供するものであ
る。OBJECTS OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device which eliminates the above-mentioned disadvantages, reduces the potential drop in wiring parts due to circuit current, and can easily detect disconnection of metal wires.

発明の構成 本発明は、上記のような目的を達成するために、外部リ
ード端子のインナーリード部に複数本の金属ワイヤーで
、それぞれ独立した同数のメタル配線とそれぞれ接続し
、かつ、前記メタル配線のうちの単一メタル配線だけを
半導体チップと直接にオーミックコンタクトをなした半
導体集積回路装置であり、これによシ、サブストレート
電流の影響軽減ならびにメタル配線部分の断線検知が容
易になる。Structure of the Invention In order to achieve the above objects, the present invention connects the inner lead portion of an external lead terminal to the same number of independent metal wires using a plurality of metal wires, and This is a semiconductor integrated circuit device in which only a single metal wiring is in direct ohmic contact with a semiconductor chip, which makes it easier to reduce the effects of substrate current and detect disconnections in metal wiring.

発明の実施例 第２図は本発明の一実施例平面図である。第１図に示し
た従来例とは、メタル配線５の側でオーミックコンタク
トのないことが相違するだけである。すなわち、第２図
示の実施例によると、メタル配線５は、半導体チップ部
とはオーミックコンタクトを取っていないので他方のメ
タル配線４とは完全に独立となシ、メタル配線の電圧降
下差による電流の流れはなぐなシ、回路間の影響がなく
なる。Embodiment of the Invention FIG. 2 is a plan view of an embodiment of the invention. The only difference from the conventional example shown in FIG. 1 is that there is no ohmic contact on the metal wiring 5 side. That is, according to the embodiment shown in the second diagram, the metal wiring 5 is not in ohmic contact with the semiconductor chip portion, so it is completely independent of the other metal wiring 4, and the current due to the difference in voltage drop between the metal wirings. The flow is smooth and there is no influence between circuits.

また、一方のワイヤーが断線していたとすると、回路は
正常に動作しないので、簡単にテストにて不良品を除去
する事が可能である。Furthermore, if one of the wires is disconnected, the circuit will not operate normally, so it is possible to easily eliminate defective products through testing.

発明の効果 以上に述べたように、本発明の半導体集積回路装置によ
れば、メタル配線と半導体チップとのオーミックコンタ
クト領域が限定されているので、グランドインピーダン
スを低くする必要性がある時、または、回路間の電圧降
下差による悪影響をなくしたい時、またワイヤーの断線
による初期不良を除去する時に有効であり、とくに、多
機能回路要素を含む半導体集積回路装置に最適である。Effects of the Invention As described above, according to the semiconductor integrated circuit device of the present invention, the ohmic contact area between the metal wiring and the semiconductor chip is limited. This is effective when it is desired to eliminate the adverse effects of voltage drop differences between circuits, and when eliminating initial failures due to wire breaks, and is particularly suitable for semiconductor integrated circuit devices including multifunctional circuit elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例装置の平面図、＄２図は本発明実施例装
置の平面図である。 １・・・・・・リード端子、２．３・・・・・・金属イ
ヤー、４゜６・・・・・・メタル配線、６，７−・・・
・・オーミックコンタクト、８・・・・・・ＩＣチップ
。。FIG. 1 is a plan view of a conventional device, and FIG. 2 is a plan view of a device according to an embodiment of the present invention. 1...Lead terminal, 2.3...Metal ear, 4゜6...Metal wiring, 6,7-...
...Ohmic contact, 8...IC chip. .

Claims (1)

【特許請求の範囲】[Claims] 外部リード端子のインナーリード部に複数本の金属ワイ
ヤーで、それぞれ独立した同数のメタル配線とそれぞれ
接続し、かつ、前記メタル配線のうちの単一メタル配線
だけを半導体チップと直接にオーミックコンタクトをな
した半導体集積回路装置。The inner lead portion of the external lead terminal is connected to the same number of independent metal wires using multiple metal wires, and only a single metal wire among the metal wires is made into direct ohmic contact with the semiconductor chip. Semiconductor integrated circuit device.
JP59192876A 1984-09-14 1984-09-14 Semiconductor integrated circuit device Granted JPS6170732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59192876A JPS6170732A (en) 1984-09-14 1984-09-14 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59192876A JPS6170732A (en) 1984-09-14 1984-09-14 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6170732A true JPS6170732A (en) 1986-04-11
JPH0451065B2 JPH0451065B2 (en) 1992-08-18

Family

ID=16298442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59192876A Granted JPS6170732A (en) 1984-09-14 1984-09-14 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6170732A (en)

Also Published As

Publication number Publication date
JPH0451065B2 (en) 1992-08-18

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