JPS63257241A - Monitoring element of semiconductor device - Google Patents
Monitoring element of semiconductor deviceInfo
- Publication number
- JPS63257241A JPS63257241A JP9140387A JP9140387A JPS63257241A JP S63257241 A JPS63257241 A JP S63257241A JP 9140387 A JP9140387 A JP 9140387A JP 9140387 A JP9140387 A JP 9140387A JP S63257241 A JPS63257241 A JP S63257241A
- Authority
- JP
- Japan
- Prior art keywords
- monitor
- monitoring
- chip
- wafer
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000012544 monitoring process Methods 0.000 title abstract description 16
- 238000000034 method Methods 0.000 abstract description 6
- 238000005259 measurement Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241000981595 Zoysia japonica Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置のウェハプロセスの良否を判定するためのモ
ニタ素子の構成を、チップが使用されない領域１例えば
スクライブライン内または周辺の使用出来ないチップ内
にモニタ素子を設け、モニタパッドは１千ツブ゛または
小数のチップ内にまとめて形成するようにすることによ
り、モニタパッドを大きく形成でき測定探針によるブロ
ービングを容易にし、しかもモニタパッドを１箇所にま
とめてモニタ素子の一括測定を可能にする。また。[Detailed Description of the Invention] [Summary] The configuration of a monitor element for determining the quality of a wafer process of a semiconductor device is described below. By forming the monitor pads together in 1,000 blocks or a small number of chips, it is possible to form a large monitor pad, making it easier to blow with a measurement probe, and also by forming the monitor pads in one place. Enables batch measurement of monitor elements. Also.
モニタ素子形成によりデバイスの高密度化を阻害するこ
となく、チップの有効数を大きく残らすこともなくなる
。The formation of the monitor element does not impede the increase in device density and does not leave a large number of effective chips remaining.
本発明は半導体装置のウェハプロセスの良否を判定する
ためのモニタ素子の構成に関する。The present invention relates to the configuration of a monitor element for determining the quality of a wafer process of a semiconductor device.
半導体装置の製造においては、その高Ｊ３．能化。In the manufacture of semiconductor devices, the high J3. Enablement.
高集積化にともない、デバイス完成前にウェハプロセス
を評価するモニタ測定がまずまず重要となってきた。As devices become more highly integrated, monitoring measurements to evaluate wafer processes before device completion has become increasingly important.
〔従来の技術と。[With conventional technology.
発明が解決しようとする問題点〕 本来、モニタ素子は基本的な素子特性（抵抗。Problems that the invention attempts to solve] Originally, a monitor element had basic element characteristics (resistance).
ダイオード、トランジスタ等の特性）を測定し。Measure the characteristics of diodes, transistors, etc.
デバイス設計の評価、製造技術の評価を行うためのもの
である。It is used to evaluate device design and manufacturing technology.
ところが、近年モニタ素子をシステマテインクに測定し
、ウェハプロセスの良否を判定することが多く行われる
ようになってきた。However, in recent years, it has become common to use a monitor element as a system to determine the quality of the wafer process.
そのために、従来のモニタ素子はウェハ内につぎ０３つ
の構成で形成されていた。For this reason, conventional monitor elements are formed in the following three configurations within a wafer.
第２図〜第４図は従来のモニタ素子の構成を説明するウ
ェハの平面図である。FIGS. 2 to 4 are plan views of a wafer explaining the structure of a conventional monitor element.
■ 第２図（１１，（２＋参照：
デバイスチップ４とモニタチップ７のバルク構造は同じ
で、モニタチップ７は配線のみをモニタ用に変えてウェ
ハ内に複数個点在させて形成されている。■ Figure 2 (Refer to 11, (2+): The bulk structure of the device chip 4 and the monitor chip 7 is the same, and the monitor chip 7 is formed by changing only the wiring for monitoring, and multiple chips are scattered within the wafer. .
この場合は、ウェハ内のデバイスチップ４の有効数が減
少し、！！造コス［・が増加する。In this case, the effective number of device chips 4 in the wafer decreases! ! Created cost increases.
■ 第３図参照ニ
スクライブライン６内にモニタ素子１．モニタパッド２
．モニタ配線３を設ける。■ Refer to Figure 3. Monitor element 1. monitor pad 2
．． A monitor wiring 3 is provided.
この場合は２幅９０°〜１５０μｍのスクライブライン
６内に設けられるモニタパッド合の大きさは７０ｐ ｍ
程度となり２通常のデバイスパッド８の約１２０μｍ角
と比較して小さく、さらにモニタバッド２がモニタ素子
１ごとにウェハ内に散在しているため、ブロービングが
困難となり、また一括測定もできない。In this case, the size of the monitor pad provided within the scribe line 6 with a width of 90° to 150 μm is 70 μm.
Since the monitor pads 2 are small compared to the approximately 120 μm square of a normal device pad 8, and the monitor pads 2 are scattered within the wafer for each monitor element 1, it is difficult to perform probing, and bulk measurement is also not possible.
■ 第４図＋１１． （２１参照：
全デバイスチップ内にモニタ素子１．モニタパッド２．
モニタ配線３を設ける。■ Figure 4 +11. (Refer to 21: Monitor element 1. Monitor pad 2.
A monitor wiring 3 is provided.
この場合は、デバイスチップ４内での高密度化が妨げら
れる。また、多種のモニタ素子を設けられない欠点をも
つ。In this case, increasing the density within the device chip 4 is hindered. Another disadvantage is that it is not possible to provide a wide variety of monitor elements.
上記問題点の解決は、半導体装置のチップを作製したウ
ェハの該チップがデバイスとして使用されない領域に設
けたモニタ素子と、該ウェハ内の少なくとも１チップに
設けた複数のモニタパッドと、該モニタ素子と該モニタ
バ・７上間を接続するモニタ配線とを有することを特徴
とする半導体装置のモニタ素子により達成される。The solution to the above problem is to provide a monitor element provided in an area of a wafer on which semiconductor device chips are fabricated, where the chips are not used as a device, a plurality of monitor pads provided on at least one chip in the wafer, and a monitor element provided on at least one chip in the wafer. This is achieved by a monitor element of a semiconductor device characterized in that it has a monitor wire that connects the monitor bar 7 and the monitor bar 7.
本発明は、モニタ素子をチップがデバイスとして使用さ
れない領域に設け、これとモニタ配線によって接続され
るモニタパットを少なくとも１チップ内に集めることに
より、デバイスチップの有効面積、高密度化を損なわず
、モニタ素子の一括測定を可能にするものである。The present invention provides a monitor element in an area where the chip is not used as a device, and collects monitor pads connected to the monitor element by monitor wiring in at least one chip, thereby maintaining the effective area and high density of the device chip. This enables batch measurement of monitor elements.
また、モニタ素子はスクライブライン内のどこに配置し
てもよく、従ってウェハ内の特性のばらつきも検出でき
る。Further, the monitor element may be placed anywhere within the scribe line, and therefore it is possible to detect variations in characteristics within the wafer.
第１図（１１，（２）は本発明のモニタ素子の構成を説
明するウェハの平面図である。FIG. 1 (11, 2) is a plan view of a wafer illustrating the configuration of the monitor element of the present invention.
第１図（１）において、複数のモニタ素子ｌをスクライ
ブライン６内に配置し、モニタパッド用チップ５上に設
けたモニタパッド２はスクライブライン６内に形成され
た゛モニタ配線３によりモニタ素子ｌの端子に接続され
ている。In FIG. 1 (1), a plurality of monitor elements l are arranged in a scribe line 6, and a monitor pad 2 provided on a monitor pad chip 5 is connected to a monitor element l by a monitor wiring 3 formed in the scribe line 6. is connected to the terminal.
このためこの実施例では、モニタパッド用チップ５のモ
ニタバッド２にプロービングを行うことにより、複数の
モニタ素子を一括して測定するこ、とができ、測定工数
を大幅に減少させることができる。Therefore, in this embodiment, by probing the monitor pad 2 of the monitor pad chip 5, a plurality of monitor elements can be measured at once, and the number of measurement steps can be significantly reduced.
また第１図（２）のように、モニタ素子１はスクライブ
ライン６内だけでなく、ウェハ周辺の使用できないデバ
イスチップ９上に設けてもよい。Further, as shown in FIG. 1(2), the monitor element 1 may be provided not only within the scribe line 6 but also on an unusable device chip 9 near the wafer.
この場合は、ウェハ周辺のデバイス特性のバラツキが測
定できる。In this case, variations in device characteristics around the wafer can be measured.
モニタパッド用チップ５の数は必要に応じてウェハ内に
複数個設けてもよい。A plurality of monitor pad chips 5 may be provided in a wafer as necessary.
（発明の効果〕
以上説明したように本発明によれば、デバイスチップの
有効数、高密度化を損なわず、モニタ素子の一括測定を
可能にすることができる。(Effects of the Invention) As described above, according to the present invention, it is possible to perform batch measurement of monitor elements without impairing the effective number of device chips or increasing their density.
また、ウェハ内の特性のばらつきも検出することができ
る。It is also possible to detect variations in characteristics within a wafer.
従って、効果的なウェハプロセスの評価ができるように
なった。Therefore, it has become possible to effectively evaluate wafer processes.
第１図（１１，（２１は本発明のモニタ素子の構成を説
明するウェハの平面図。
第２図〜第４図は従来のモニタ素子の構成を説明するウ
ェハの平面図である。
図において。
１はモニタ素子。
２はモニタパッド。
３はモニタ配線。
４はデバイスチップ。
５はモニタパッド用チップ。
６はスクライブライン。
７はモニタチップ。
８はデバイスパッド。
９は使用できないデバイスチップ
（１２峯づ６日）目め テ１１）１洞
第 １１辺
（ｚ）峯疋）３）−］の乎勧）図
イ ）１図
（１） 吃逆＄ナイ多す リ 子Ｆｐｇｒ”、凸子２
）月
（２） イ、芝、３Ｆ イブリ → 机 へｔＡ予
２１躬
促１ミ臼り の子６ｏｊ辺
穿３１辺FIG. 1 (11, (21) is a plan view of a wafer explaining the configuration of a monitor element of the present invention. FIGS. 2 to 4 are plan views of a wafer explaining the configuration of a conventional monitor element. 1 is a monitor element. 2 is a monitor pad. 3 is a monitor wiring. 4 is a device chip. 5 is a chip for monitor pad. 6 is a scribe line. 7 is a monitor chip. 8 is a device pad. 9 is an unusable device chip ( 12th 6th day) Te 11) 1st cave 11th side (z) Mineki) 3) -]'s recommendation) Figure 1) 1 Figure (1) 吃弄＄ないたす り 子Fpgr'', convex Child 2
) Month (2) I, Shiba, 3F Iburi → Desk to tA 21 輺 1 mm milling Noko 6 oj side punch 31 side
Claims (1)
イスとして使用されない領域に設けたモニタ素子と、 該ウェハ内の少なくとも１チップに設けた複数のモニタ
パッドと、 該モニタ素子と該モニタパッド間を接続するモニタ配線 とを有することを特徴とする半導体装置のモニタ素子。[Scope of Claims] A monitor element provided in a region of a wafer on which semiconductor device chips are fabricated, where the chips are not used as devices; a plurality of monitor pads provided on at least one chip in the wafer; and the monitor element. A monitor element for a semiconductor device, comprising a monitor wire connecting between the monitor pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9140387A JPS63257241A (en) | 1987-04-14 | 1987-04-14 | Monitoring element of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9140387A JPS63257241A (en) | 1987-04-14 | 1987-04-14 | Monitoring element of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63257241A true JPS63257241A (en) | 1988-10-25 |
Family
ID=14025412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9140387A Pending JPS63257241A (en) | 1987-04-14 | 1987-04-14 | Monitoring element of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63257241A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04152543A (en) * | 1990-10-16 | 1992-05-26 | Agency Of Ind Science & Technol | Integrated circuit structure body provided with self-inspection function; sorting method of good integrated circuit chip by using it |
| US5561373A (en) * | 1990-10-09 | 1996-10-01 | Fujitsu Limited | Method and device for detecting electrostatic stress applied to a product semiconductor device during each production process |
| JP2007173350A (en) * | 2005-12-20 | 2007-07-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1987
- 1987-04-14 JP JP9140387A patent/JPS63257241A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561373A (en) * | 1990-10-09 | 1996-10-01 | Fujitsu Limited | Method and device for detecting electrostatic stress applied to a product semiconductor device during each production process |
| JPH04152543A (en) * | 1990-10-16 | 1992-05-26 | Agency Of Ind Science & Technol | Integrated circuit structure body provided with self-inspection function; sorting method of good integrated circuit chip by using it |
| JP2007173350A (en) * | 2005-12-20 | 2007-07-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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