JPS61176465U - - Google Patents

Info

Publication number
JPS61176465U
JPS61176465U JP6072885U JP6072885U JPS61176465U JP S61176465 U JPS61176465 U JP S61176465U JP 6072885 U JP6072885 U JP 6072885U JP 6072885 U JP6072885 U JP 6072885U JP S61176465 U JPS61176465 U JP S61176465U
Authority
JP
Japan
Prior art keywords
read
circuit
write semiconductor
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6072885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6072885U priority Critical patent/JPS61176465U/ja
Publication of JPS61176465U publication Critical patent/JPS61176465U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のデジタル回路タイミング誤差
測定装置を示す回路図、第2図は従来の測定装置
を示す回路図、である。図において、 4は信号出力部、5は信号入力部、6は制御部
、41,51はRAM、42は出力回路、52は
入力回路、61はRAM選択回路、62はアドレ
ス選択回路、63はアドレスセレクタ、64はア
ドレスカウンタ、65はクロツク信号発振器、を
それぞれ表す。
FIG. 1 is a circuit diagram showing a digital circuit timing error measuring device of the present invention, and FIG. 2 is a circuit diagram showing a conventional measuring device. In the figure, 4 is a signal output section, 5 is a signal input section, 6 is a control section, 41 and 51 are RAMs, 42 is an output circuit, 52 is an input circuit, 61 is a RAM selection circuit, 62 is an address selection circuit, and 63 is a An address selector, 64 an address counter, and 65 a clock signal oscillator, respectively.

Claims (1)

【実用新案登録請求の範囲】 それぞれに読出し/書込み半導体記憶装置41
を具え、被測定回路に信号を出力する複数個の出
力回路42と、 それぞれ読出し/書込み半導体記憶装置51を
具え、被測定回路の出力信号を受け取る複数個の
入力回路52と、 該出力回路42と該入力回路52とを制御する
制御部6を具え、 複数個の中から1個の該読出し/書込み半導体
記憶装置41または51を選択する選択回路61
と、 該読出し/書込み半導体記憶装置41または5
1内のアドレスを選択する選択回路62とで、 該制御回路6を構成してなることを特徴とする
デジタル回路タイミング誤差測定装置。
[Claims for Utility Model Registration] Each read/write semiconductor memory device 41
a plurality of output circuits 42 which output signals to the circuit under test; a plurality of input circuits 52 each comprising a read/write semiconductor memory device 51 and which receives an output signal from the circuit under test; and the output circuit 42. a selection circuit 61 that selects one of the read/write semiconductor storage devices 41 or 51 from among the plurality of read/write semiconductor storage devices;
and the read/write semiconductor memory device 41 or 5
1. A digital circuit timing error measuring device characterized in that said control circuit 6 is constituted by a selection circuit 62 for selecting an address within 1.
JP6072885U 1985-04-23 1985-04-23 Pending JPS61176465U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6072885U JPS61176465U (en) 1985-04-23 1985-04-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6072885U JPS61176465U (en) 1985-04-23 1985-04-23

Publications (1)

Publication Number Publication Date
JPS61176465U true JPS61176465U (en) 1986-11-04

Family

ID=30588345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6072885U Pending JPS61176465U (en) 1985-04-23 1985-04-23

Country Status (1)

Country Link
JP (1) JPS61176465U (en)

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