JPS604248A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS604248A
JPS604248A JP58112024A JP11202483A JPS604248A JP S604248 A JPS604248 A JP S604248A JP 58112024 A JP58112024 A JP 58112024A JP 11202483 A JP11202483 A JP 11202483A JP S604248 A JPS604248 A JP S604248A
Authority
JP
Japan
Prior art keywords
layer
film
pad
bonding
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58112024A
Other languages
English (en)
Inventor
Kunio Kokubu
國分　邦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58112024A priority Critical patent/JPS604248A/ja
Publication of JPS604248A publication Critical patent/JPS604248A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 不発明は半導体集積回路装置に関し２％にポンディング
パッドに関する。
半導体集積回路装置の外部への電気的専用は。
通常、装置表面のボンティングパッドと称する部分にワ
イアー等を圧着して行なわれている。この圧着工程は、
熱または超音波等によってエネルギーを与え、互た、−
足の荷重音訓えてワイアー等をパッドに圧着するもので
あるが、この時の機械的衝撃によりボンデイン・ｌパッ
ド部分が破壊され、半導体基板との間が電気的ショート
状態になるという事故が従来より多く見られた。
不発明は、ボンディング時の機械的衝撃に耐え得る丈夫
なポンディングパッドを有する装置を提供しようとする
ものであり、以下、従来構造と対比して本発明の実施例
を図面を用いて説明する。
第１図に平面図（ａ図）と断面図（ｂ図）で示す如く、
従来構造では、半導体基板１　（１）表面絶縁ＩＮ２の
上に、へ１等の金属膜３によるボンティングパッドが形
成されている。この金属膜３は果槓１回路装置門の金属
配線とｔｒｓ時に形成されるのが普通でおるが、近年、
素子寸法の微細化に伴ない。
その厚さが薄くならざるを得ない傾向にある。このよう
な薄い金ハ膜３よりなるボンティングパッドに６強い衝
撃でワイヤー等を圧着すると、その＠撃が直接絶縁膜２
にかかることになり、微細なりラック等の発生により、
ポンディングパッド３と半導体基板１との間が電気的シ
ョートの状態になることが少なくない。なお１通常、集
積回路装置の最上表面は保＠膜６で被覆され、ポンディ
ングパッドのところで開口しているので、これも図示し
である。
次に第２図に、不発明の一実施例を図示する。
半導体基板１′の表面絶縁膜２′の上に、第１層のＡ１
等の金属膜３′を形成するところまでは従来信造と共通
である。しかし、その上に絶縁膜４′全形成してパッド
部分全開１」シ、第２層のＡ１等の金属５′ヲ形成して
第１ｒｇ　３　’に重ね、パッド部分の金属膜を厚くす
るのが本溌明の特徴である・こうすることによって、ワ
イヤー等を圧着する時の衝撃に対して、２層厘ねて厚く
した金属膜がクッションとして働き、絶Ａ＃、膜２′に
かかる衝撃全緩和するので、ポンディングパッド部が破
壊されることがなくなる。
なお、不発明全実施すると、絶縁膜４′と第２層金属膜
５′ヲ形成する工程が新たにつけ加わり。
製造工程が長くなるかのり）」き、印象があるが、近年
、集積回路装置のサイズ全少さくする必要からめ金属２
層配線（多層配線）が多用されつつあり。
絶縁膜４′と第２層金属膜５′は、第２層金属配線を形
成する工程で同時に形成することができることを有配し
ておく。また、表面保護膜６′　も図示しておいた。
以上の実施例に２いて、バット材料はアルミニウムに限
られないことは熱論である。
【図面の簡単な説明】
第１図はポンディングパッドの従来構ｍ　Ｙ　ｔｅわし
た平面図（ａ図）と所間、図（ｂ図）である・１・・・
・・半導体基板、２−・・・・基板表面の絶縁膜。 ３　・・・・ポンディングパッド（金属膜）、６・・・
・・表面保護膜。 第２図は本発明によるポンディングパッド構造の一実施
例を示す平面図（ａ図）と断面図（ｂ図）である。 １′・・・・・・半導体基板、２′　・・・・基板表面
の絶縁膜　３／　・・・・・ポンディングパッドの第１
層金属膜。 ４′・・・・・・パッド以外の部分で第１層金属膜と第
２層金属膜の間の絶縁膜として匿われる膜、５′　・・
・・ポンディングパッドの第２層策属１戻、６′　・・
・表面保護膜。 ′　９ 第１図

Claims (1)

    【特許請求の範囲】
  1. 半導体基板表面絶縁膜上の第１層金属膜と、該第１層金
    属膜と少なくとも１カ所の電気的接続を以って該金属膜
    の上に止ねられ１ヒ第２層金属膜とを有してなるポンデ
    ィングパッド′ｆｒ：１個以上有することを特徴とする
    半導体装置。
JP58112024A 1983-06-22 1983-06-22 半導体装置 Pending JPS604248A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58112024A JPS604248A (ja) 1983-06-22 1983-06-22 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58112024A JPS604248A (ja) 1983-06-22 1983-06-22 半導体装置

Publications (1)

Publication Number Publication Date
JPS604248A true JPS604248A (ja) 1985-01-10

Family

ID=14576079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58112024A Pending JPS604248A (ja) 1983-06-22 1983-06-22 半導体装置

Country Status (1)

Country Link
JP (1) JPS604248A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529375A (ja) * 1991-07-23 1993-02-05 Murata Mfg Co Ltd 半導体装置
US7956473B2 (en) 2007-07-23 2011-06-07 Renesas Electronics Corporation Semiconductor device
KR101116313B1 (ko) 2008-01-25 2012-03-14 주식회사 하이닉스반도체 반도체 소자의 본딩 패드부 및 그 형성 방법
CN103177973A (zh) * 2011-12-21 2013-06-26 北大方正集团有限公司 一种加厚压焊块的制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529375A (ja) * 1991-07-23 1993-02-05 Murata Mfg Co Ltd 半導体装置
US7956473B2 (en) 2007-07-23 2011-06-07 Renesas Electronics Corporation Semiconductor device
KR101116313B1 (ko) 2008-01-25 2012-03-14 주식회사 하이닉스반도체 반도체 소자의 본딩 패드부 및 그 형성 방법
CN103177973A (zh) * 2011-12-21 2013-06-26 北大方正集团有限公司 一种加厚压焊块的制作方法

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