JPS60244044A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60244044A JPS60244044A JP59099238A JP9923884A JPS60244044A JP S60244044 A JPS60244044 A JP S60244044A JP 59099238 A JP59099238 A JP 59099238A JP 9923884 A JP9923884 A JP 9923884A JP S60244044 A JPS60244044 A JP S60244044A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- substrate
- semiconductor device
- film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の技術分野）
本発明は半導体装置及びその製造方法に関し、特に相補
型ＭＯ８半導体装置の素子分動に使用されるものである
。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly used for element segmentation of a complementary MO8 semiconductor device.
従来、半導体装置の素子分離法どしては窒化シリコン膜
をＩＶＩＪｎ化性マスクとしで利用ずろ選択酸化法（Ｌ
ＯＣＯ８法）が最も一般的に使用されている。しかし、
この方法はバースビーク、ボヮイ１へリボンの発生等の
欠点を有することがら将来の高集積半導体装置の素子分
離には不適当である。Conventionally, in the element isolation method of semiconductor devices, a selective oxidation method (L
OCO8 method) is the most commonly used. but,
This method has drawbacks such as generation of birth beaks and ribbons in the void 1, and is therefore unsuitable for element isolation of future highly integrated semiconductor devices.
特に、ＣＭＯ８半導体装置においては、素子分離酸化膜
の幅を大きくしなければラッチアップを防止する効果が
ほとんどないため、高集積化を妨げる原因となっている
。In particular, in CMO8 semiconductor devices, there is little effect in preventing latch-up unless the width of the element isolation oxide film is increased, which is a cause of hindering high integration.
そこで、第１図に示されるような埋込み型の素子分離技
術（ドレンチアインレージョン）が注目されている。第
１図において、例えばＰ型シリコン基板１の主面には溝
が形成され、この溝の内部には素子分離材２が埋設され
ている。この素子分離材２によりＰ型ウェル領域３とウ
ェル領域３以外の基板１とが分離されている。ウェル領
域３以外の基板１上にはグー１〜酸化ＩＩＩ ４を介し
てゲート電極５が形成され、ゲート電極５の両側方の基
板１表面にはＰ＋型ソース、ドレイン領域６．７が形成
されてＰ’Ｊ−ｔネルＭ Ｏ８１〜ランジスタが構成さ
れている。一方、ウェル領域３上にはゲート酸化膜４を
介してグー１〜電極５が形成され、ゲート電（犯５の両
側方の基板１表面にはＮ＋＋ソース、ドレイン領域８．
９が形成されてＮヂャネルＭＯ＄１〜ランジスタが構成
されている。Therefore, a buried type element isolation technique (drench inlay) as shown in FIG. 1 is attracting attention. In FIG. 1, for example, a groove is formed in the main surface of a P-type silicon substrate 1, and an element isolation material 2 is buried inside the groove. The element isolation material 2 separates the P-type well region 3 from the substrate 1 other than the well region 3. A gate electrode 5 is formed on the substrate 1 other than the well region 3 through goo 1 to oxide III 4, and P+ type source and drain regions 6.7 are formed on the surface of the substrate 1 on both sides of the gate electrode 5. The P'J-t channel MO81 to transistor are configured. On the other hand, electrodes 1 to 5 are formed on the well region 3 via a gate oxide film 4, and N++ source and drain regions 8.
9 is formed to constitute an N channel MO$1~ transistor.
上述した埋込み型素子分離技術では基板１の主面が平坦
化され、微細な配線の断線を防止できるうえにＯＮ・Ｉ
Ｏ８におけるラッチアップも有効に防止できるという利
点かある。In the above-mentioned buried element isolation technology, the main surface of the substrate 1 is flattened, and not only can minute interconnections be prevented from breaking, but also ON/I
This has the advantage that latch-up at O8 can also be effectively prevented.
しかし、従来の埋め込み型素子分離技術では溝の内部の
素子力Ｒｕ材を介して互いに対向する基板の側壁の一方
にのみ反転防止用の拡散層を形成することができないの
で、素子力Ｆｉｌ ＋Ｊに接してＰＮ接合を形成するど
、接合リーク電流（図中矢印で表示）が大きくなるとい
う欠点がある。特に、Ｎ＋型抵拡散層例えば第２図に示
す如くＮ＋＋ソース、ドレイン領域８．９を形成した場
合には素子力ａｌｌ ｔＪ２に）０っだ接合リーク電流
が顕著どなる。However, with the conventional buried type element isolation technology, it is not possible to form a diffusion layer for preventing inversion only on one side wall of the substrate facing each other via the element force Ru material inside the groove. When they are in contact to form a PN junction, there is a drawback that the junction leakage current (indicated by an arrow in the figure) increases. In particular, when an N+ type resistive diffusion layer, for example, an N++ source and drain region 8.9 as shown in FIG.
（発明の目的〕
本発明は上記事情に鑑みてなされたちのであり、埋込み
型素子分離技術を用いた場合の接合リーク電流を低減し
得る半導体装置及びそのような半導体装置を簡便に製造
しくワる方法を提供しようとするものである。(Object of the Invention) The present invention has been made in view of the above circumstances, and provides a semiconductor device that can reduce junction leakage current when using embedded element isolation technology, and a method for easily manufacturing such a semiconductor device. It is intended to provide a method.
〔発明の概要）
本願第１の発明の半導体装置は、埋込み型素子分離技術
を用いた半導体装置において、溝の内部で素子分離材を
介して互いに対向する基板の側壁の少なくとも一方が段
差を有し、かつ基板の段差部近傍に反転防止層を設けた
ことを特数とするものである。[Summary of the Invention] A semiconductor device according to the first invention of the present application is a semiconductor device using a buried element isolation technique, in which at least one side wall of a substrate facing each other with an element isolation material in between has a step. A special feature is that an anti-inversion layer is provided near the stepped portion of the substrate.
このような半導体装置によれば、溝の内部の素子分離材
を介して互いに対向する基板のｆｆｌ！ＩＩの少なくと
も一方の段差部に反転防止層を設けることができ、素子
分離材に沿った接合リーク電流を有効に防止することが
できる。特に、反転防止層を接合リーク電流の顕著なＮ
＋型抵拡散層Ｐ型つニ５−
ル領域又はＰ型シリコン基板との接合点近傍に設けた場
合に接合リーク電流を低減する効果が大きい。According to such a semiconductor device, ffl! of the substrates facing each other with the element isolation material inside the groove interposed therebetween. An anti-inversion layer can be provided on at least one step portion of II, and junction leakage current along the element isolation material can be effectively prevented. In particular, the anti-inversion layer is
When the +-type resistive diffusion layer is provided in the P-type single region or in the vicinity of the junction with the P-type silicon substrate, it is highly effective in reducing junction leakage current.
また、本願第２の発明の半導体装置の製造方法は、半導
体基板上に間口部を有する第１の被膜を形成する工程ど
、前記開口部内の前記第１の被膜の側壁に互いに対向す
るように第２の被膜を形成する工程と、対向して形成さ
れた前記第２の被膜の一方を選択的にエツチングする工
程と、前記第１の被膜及び残存した第２の被膜をマスク
として異方性エツチングにより基板をエツチングし、溝
を形成する工程と、前記残存した第２の被膜を除去した
後、前記第１の被膜をマスクどじで異方性エツチングに
より基板をエツチングし、前記溝の内部で互いに対向す
る基板の側壁の一方に段差を形成する■稈と、前記第１
の被膜をマスクとして不純物をイオン注入することによ
り基板の段差部近傍に反転防止層を形成する工程と、前
記第１の被膜を除去した後、前記溝の内部に素子分離材
を埋設する■稈と、該素子分離材以外の素子領域に６−
半導体素子を形成する工程とを具備したことを特数とす
るものである。Further, in the method for manufacturing a semiconductor device according to the second invention of the present application, in the step of forming a first film having a frontage portion on a semiconductor substrate, side walls of the first film within the opening portion are formed so as to face each other. a step of forming a second film; a step of selectively etching one of the second films formed oppositely; and anisotropic etching using the first film and the remaining second film as a mask. A step of etching the substrate by etching to form a groove, and after removing the remaining second coating, etching the substrate by anisotropic etching using a mask, etching the inside of the groove. a culm forming a step on one side wall of the substrate facing each other;
forming an inversion prevention layer near the stepped portion of the substrate by ion-implanting impurities using the first film as a mask, and burying an element isolation material inside the groove after removing the first film. A special feature of the present invention is that it comprises the steps of 6-- forming a semiconductor element in an element region other than the element isolation material.
このような方法によれば、本願第１の発明の半導体装置
を簡便な工程で形成することができる。According to such a method, the semiconductor device of the first invention of the present application can be formed through a simple process.
〔発明の実施例）
以下、本発明をｃ ｘｉ ｏ ｓデバイスに適用した実
施例を第３図（ａ）〜（０）に示す製造方法を（ｌ−１
記して説明する。[Embodiments of the Invention] Hereinafter, an embodiment in which the present invention is applied to a cxios device will be described using a manufacturing method shown in FIGS.
Write and explain.
まず、Ｐ型シリコン基板２１上にウェル分離用の溝を形
成する際のエツチングマスク材どなる膜厚１ｐｎのＣＶ
Ｄ酸化膜（第１の被膜）２２をｊｌｔ積した後、その一
部を選択的にエツチング１ノでｆｉＩｔ的な溝分離幅を
有する開口部２３を形成する。次に、全面にウェル分離
用の溝を形成する際のエツチングマスク材となる窒化シ
リコン膜を堆積した後、異方性エツチングによりエツチ
ングし、開口部２３内のＣＶＤ酸化膜２２の側壁に窒化
シリコンＩ！（第２の被ＩＩＩ）２４を残存させる（第
３図（ａ）図示）。つづいて、Ｎチャネルの素子領域を
ホトレジストパターン２５で覆った後、Ｎウェル形成用
のリンをイオン注入し、リンドープ層２Ｇを形成する。First, when forming grooves for well isolation on the P-type silicon substrate 21, an etching mask material with a film thickness of 1 pn is used.
After the D oxide film (first film) 22 is deposited, a portion thereof is selectively etched to form an opening 23 having a trench separation width of fiIt. Next, after depositing a silicon nitride film to serve as an etching mask material when forming well isolation trenches on the entire surface, etching is performed by anisotropic etching to form a silicon nitride film on the side wall of the CVD oxide film 22 in the opening 23. I! (Second target III) 24 is left (as shown in FIG. 3(a)). Subsequently, after covering the N-channel device region with a photoresist pattern 25, ions of phosphorus for forming an N-well are implanted to form a phosphorus-doped layer 2G.
つづいて、ホトレジストパターン２５をマスクとして残
存している窒化シリコン膜２４のうちＰチャネルの素子
領ｔＪ（Ｎウェル領域）側にある部分を選択的にエツチ
ング除去する（同図（ｂ）図示）。つづいて、前記ボ１
−レジス］−パ゛ターン２５を除去した後、ＣＶＤ酸化
！ＩＩ ２２及び開口部２３内のＮチャネルの素子領域
側のＣＶ Ｄ酸化ＩＩ！ ２２の側壁に残存している窒
化シリコン膜２４をマスクとして異方性エツチングによ
り基板２１の主面をエツチングし、深さ４ 、５１＋＋
ｒノのウェル分離用のｔｇ ２７を形成する（同図（Ｃ
）図示）。Subsequently, using the photoresist pattern 25 as a mask, a portion of the remaining silicon nitride film 24 on the P channel element region tJ (N well region) side is selectively removed by etching (as shown in FIG. 3B). Next, the above-mentioned button 1
-Resist] - After removing pattern 25, CVD oxidation! CVD oxidation II on the N-channel device region side in II 22 and opening 23! Using the silicon nitride film 24 remaining on the side walls of the substrate 22 as a mask, the main surface of the substrate 21 is etched by anisotropic etching to a depth of 4,51++.
Form a tg 27 for well separation of the r no.
).
次いで、残存している窒化シリコン膜２４を除去した後
、再びＣＶＤ酸化膜２２をマスクとして基板２１の主面
を０．３μ、ｎ程度エツチングする。この結果、）筒２
７内の基板２１の互いに対向する側壁は一方（Ｎチャネ
ルの素子領域側）にのみ段差が形成される。つづいて、
１２００’Ｃで高温熱処理を行ない、前記リンイオン注
入層２６のリンを拡散させて深さ４ ｐｍのＮ型ウェル
領域２８を形成する（同図（ｄ）図示）。つづいて、Ｃ
Ｖ Ｄ 酸化［！２２をマスクとして３ Ｘ １０”
ｃＪｎ−２０ドース量でボロンをイオン注入し溝２７内
の基板２１の底部及び段差部にボロンイオン注入層２９
．２９を形成する（同図（ｅ）図示）。Next, after removing the remaining silicon nitride film 24, the main surface of the substrate 21 is etched by about 0.3μ, n using the CVD oxide film 22 as a mask again. As a result, ) cylinder 2
A step is formed only on one side (on the N-channel element region side) of the mutually opposing side walls of the substrate 21 in the substrate 7 . Continuing,
A high-temperature heat treatment is performed at 1200'C to diffuse phosphorus in the phosphorus ion-implanted layer 26 to form an N-type well region 28 with a depth of 4 pm (as shown in FIG. 4(d)). Continuing, C
V D Oxidation [! 3 x 10” with 22 as a mask
Boron is ion-implanted at a dose of cJn-20 to form a boron ion-implanted layer 29 at the bottom and step portions of the substrate 21 within the groove 27.
．． 29 (as shown in FIG. 2(e)).
次いで、前記ＣＶＤ酸化膜２２をエツチング除去した後
、全面に素子分離材であるＣＶＤ酸化膜を堆積し、更に
全面エッチバックを行なうことにより溝２６の内部にＣ
ＶＤ酸化膜３０を埋設する。Next, after removing the CVD oxide film 22 by etching, a CVD oxide film serving as an element isolation material is deposited on the entire surface, and by further etching back the entire surface, carbon is formed inside the trench 26.
A VD oxide film 30 is buried.
つづいて、熱処理を行ない、前記ボロンイオン注入層２
９．２９を活性化させてＰ−型フィールド反転防止層３
１を形成する（同図（ｆ）図示）。Subsequently, heat treatment is performed to form the boron ion implanted layer 2.
9.29 is activated to form the P-type field inversion prevention layer 3.
1 (as shown in FIG. 1(f)).
つづいて、ウェル領域２８以外の基板２１上及びウェル
領ｔｉ１２８上にゲート酸化膜３２．３２を介してゲー
ト電極３３．３３を形成する。つづいて、ゲート電極３
３をマスクとしてウェル領域２８以外の基板２１に選択
的にヒ素をイオン注入することにより深さ０．４ｔｒｍ
程度のＮ＋型ソース、ドレイン領域３４．３５を形成す
る。つづいて、ゲート電極３３をマスクとしてウェル領
域２８に選択９−
的にボロンをイオン注入することによりＰ＋型ソース、
トレイン領ｔ＊３６．３７を形成する。つづいて、仝而
に層間絶縁膜３８をｊｆｆ積した後、コンタクトホール
を開孔し、更に全面に配線金属を蒸着した後、パクーニ
ングして配線３９、・・・を形成し、０ＭＯ８を製造す
る（同図（０）図示）。Subsequently, gate electrodes 33.33 are formed on the substrate 21 other than the well region 28 and on the well region ti128 via the gate oxide film 32.32. Next, gate electrode 3
3 as a mask, arsenic is selectively implanted into the substrate 21 other than the well region 28 to a depth of 0.4 trm.
N+ type source and drain regions 34 and 35 are formed. Next, by selectively implanting boron ions into the well region 28 using the gate electrode 33 as a mask, a P+ type source is formed.
A train region t*36.37 is formed. Subsequently, after depositing the interlayer insulating film 38, contact holes are opened, and wiring metal is further deposited on the entire surface, and then the wiring 39, etc. are formed by puncturing, and 0MO8 is manufactured. (Illustrated in (0) of the same figure).
しかして第３図（０）図示のｃ ｖ ｏ ｓは、溝の内
部のＣＶＤＩ化膜（素子分離材）３０を介して互いに対
向する基板２１の側壁の一方（ＮチャネルＭ ＯＳ ｌ
−ランジスタ側）の段差部、すなわちＮ＋型ソース、ド
レイン領１１ｔ３４．３５とＰ型シリコン基板２１との
接合点近傍にＰ−型反転防止層３１が形成されているの
で、両者の間の接合リーク電流を低減することができ、
素子特性を向上することができる。Therefore, the cv o s shown in FIG.
- Since the P- type inversion prevention layer 31 is formed near the step portion of the N+ type source/drain region 11t34.35 and the P type silicon substrate 21 (on the transistor side), there is no junction leakage between the two. can reduce the current,
Device characteristics can be improved.
また、上記実施例で用いた方法では異方性エツチングを
利用することにより従来の方法に写真蝕刻法を追加する
ことなく、セルファラインで溝の内部のＣＶＤＩ化膜３
０を介して互いに対向する基板２１の側壁の一方の段差
部にＰ−型反転防止１０−
層３１を形成することができるので、極めて簡便な工程
で上）ホしたようなリーク電流を低減しｉりる素子特性
の良好なＣＮ＝Ｉ ＯＳを製造することができる。Furthermore, in the method used in the above embodiment, by using anisotropic etching, the CVDI film 3 inside the groove can be etched with self-alignment without adding photolithography to the conventional method.
Since the P-type inversion prevention layer 31 can be formed on one stepped portion of the side walls of the substrates 21 that face each other through the P-type inversion prevention layer 31, the leakage current as described in (a) above can be reduced with an extremely simple process. It is possible to manufacture a CN=IOS with good element characteristics.
なお、上記実施例ではＮチャネルＭ ＯＳ Ｉ−ラン°
ジスタ側の基＃ｉ２１側壁にのみ段差部を形成したが、
第４図に示すようにＰヂャネルＭＯ８ｔ−ランジスタ側
の基板２１側壁にも段差部を形成し、その段差部近傍に
Ｐ−型反転防止層４０を設（づ、Ｎ型ウェル領域２８と
Ｐ型シリコン基板２１どの間のリーク電流を防止するよ
うにしてもよい。なお、第４図図示のようなＣＭ ＯＳ
はシリコン基１反のエツチング詩にエツチングマスクと
なる第１及び第２の被膜以外に第３の被膜を形成してお
くことにより容易に製造することができる。Note that in the above embodiment, the N-channel MOS I-run °
Although a step portion was formed only on the side wall of base #i21 on the register side,
As shown in FIG. 4, a stepped portion is also formed on the side wall of the substrate 21 on the side of the P channel MO8t transistor, and a P-type inversion prevention layer 40 is provided near the stepped portion. The leakage current between the silicon substrates 21 may be prevented.
can be easily manufactured by forming a third coating in addition to the first and second coatings that serve as an etching mask on a single silicon base film.
また、上記実施例では溝の内部にＣＶＤＩ化膜を埋設し
たが、これに限らず溝の内部表面に熱酸化膜を形成した
後、多結晶シリコンを埋設してもよい。Further, in the above embodiment, the CVDI film is buried inside the groove, but the present invention is not limited to this, and polycrystalline silicon may be buried after forming a thermal oxide film on the inner surface of the groove.
１１−
絶縁膜、３９・・・配線、４０・・・Ｐ−型反転防止層
。11- Insulating film, 39... Wiring, 40... P- type inversion prevention layer.
以上詳述した如く本発明に」−れば、埋込み型素子分離
技術を用いた場合に接合リーク電流を有効に防止し得る
半導体装置及びそのような半導体装置を容易に製造し１
９る方法を提供できるものである。As detailed above, the present invention provides a semiconductor device that can effectively prevent junction leakage current when using a buried element isolation technique, and a method for easily manufacturing such a semiconductor device.
9.
紹１図は従来の埋込み型素子弁Ｈ１技術を用いて製造さ
れたｃ ｈ＝＋ ｏ ｓの断面図、第２図は同ＣＭＯ８
の欠点を示すｘ＋１明図、第３図（ａ ） −＝−（０
）は本発明の実施例におけるＣ Ｍ ＯＳを得るための
製造■稈を示す断面図、第４図は本発明の他の実施例に
おけるＣ〜１０Ｓの断面図である。
２１・・・Ｐ型シリコン基板、２２・・・ＣＶ Ｄ醸化
膜、２３・・・開口部、２４・・・窒化シリコン膜、２
５・・・ホ［・レジストパクーン、２６・・・リンドー
プ層、２７・・・溝、２８・・・Ｎ型ウェル領域、２９
・・・ボロンドープ層、３０・・・ＣＶ Ｄ Ｍ’ｌ化
膜、３１・・・Ｐ−型反転防止層、３２・・・グーｌ−
酸化膜、３３・・・グー１〜電極、３４．３５・・・Ｎ
＋型ソース、ドレイン領域、３６．３７・・・Ｐ＋型ソ
ース、ドレイン領域、３８・・・層間＝１２−
出願人代理人 弁理士 鈴江武彦
−１３−１Introduction Figure 1 is a cross-sectional view of ch = + o s manufactured using the conventional embedded element valve H1 technology, and Figure 2 is a cross-sectional view of the same CMO8.
x+1 clear diagram showing the defects in Figure 3 (a) -=-(0
) is a cross-sectional view showing a culm manufactured to obtain CMOS in an embodiment of the present invention, and FIG. 4 is a cross-sectional view of C to 10S in another embodiment of the present invention. DESCRIPTION OF SYMBOLS 21... P-type silicon substrate, 22... CVD fermentation film, 23... Opening part, 24... Silicon nitride film, 2
5... Resist pattern, 26... Phosphorus doped layer, 27... Groove, 28... N-type well region, 29
...Boron doped layer, 30...CV D M'l film, 31...P- type inversion prevention layer, 32...Glue l-
Oxide film, 33...Goo 1~electrode, 34.35...N
+ type source, drain region, 36. 37...P+ type source, drain region, 38... interlayer = 12- Applicant's agent Patent attorney Takehiko Suzue -13-1
Claims (4)
れた素子分離材と、該素子分離材以外の素子領域に形成
された半導体素子とを有する半導体装置において、前記
溝の内部の素子分前４イを介して互いに対向するＭ板の
側壁の少なくとも一方が段差を有し、かつ基板の段差部
近傍に反転防止層を設けたことを特徴とする半導体装置
。(1) In a semiconductor device having an element isolation material buried inside a groove formed in the main surface of a semiconductor substrate, and a semiconductor element formed in an element region other than the element isolation material, the inside of the groove is 1. A semiconductor device characterized in that at least one of the side walls of the M-plates facing each other with an element width 4a in between has a step, and an inversion prevention layer is provided in the vicinity of the step portion of the substrate.
された素子分離材を相補型ＭＯ８半導体装置のウェル領
域の分離に用いる特許請求の範囲第１項記載の半導体装
置。(2) A semiconductor device according to claim 1, in which an element isolation material buried inside a groove formed in a main surface of a semiconductor substrate is used to isolate a well region of a complementary MO8 semiconductor device.
Ｐ型シリコンＮ板との接合点近傍に設ける特許請求の範
囲第２項記載の半導体装置。(3) The semiconductor device according to claim 2, wherein the inversion prevention layer is provided in the vicinity of the junction between the N+ type resistive diffusion layer P type well region or the P type silicon N plate.
成する工程と、前記開口部内の前記第１の被膜の劃−壁
に亙いに対向するように第２の液賎を形成する工程と、
対向して形成された前記第２の被膜の一方を選択的にエ
ツチングする工程と、前記第１の被膜及び残存した第２
の被Ｉｉ髪をマスクどして異方性エツチングにより雄板
をエツチングし、溝を形成する工程と、前記残存した第
２の？ｉ！ｊ ＩＮを除去した後、前記第１の被膜をン
スクとして異方性エツチングによりＭ板をエツチングし
、前記溝の内部でｎいに対向する基板の側壁の一方に段
差を形成する工程と、前記第１の被膜をマスクどして不
純物をイオン注入することにより基板の段差部近傍に反
転防止層を形成する工程と、前記第１の被膜を除去した
後、前記）背の内部に素子分ｌ１ｌｌＩ材を埋設する工
程と、該素子分離材以外の素子ｉｉｉ′ｉ域に半導体素
子を形成する工程とを川幅したことを特１敦とする半導
体装置の製造方法。(4) Forming a first film having an opening on a semiconductor substrate, and forming a second liquid droplet so as to face the wall of the first film within the opening. process and
a step of selectively etching one of the second coatings formed opposite to each other; and a step of etching the first coating and the remaining second coating.
etching the male plate by anisotropic etching using the masked hair of Ii to form a groove; and a step of forming a groove on the remaining second hair. i! After removing the IN, etching the M plate by anisotropic etching using the first film as a mask to form a step on one of the side walls of the substrate facing each other inside the groove; A step of forming an inversion prevention layer near the stepped portion of the substrate by ion-implanting impurities using the first film as a mask, and after removing the first film, forming an element layer inside the back A method of manufacturing a semiconductor device characterized in that the step of embedding a material and the step of forming a semiconductor element in an element iii'i region other than the element isolation material are separated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59099238A JPS60244044A (en) | 1984-05-17 | 1984-05-17 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59099238A JPS60244044A (en) | 1984-05-17 | 1984-05-17 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60244044A true JPS60244044A (en) | 1985-12-03 |
Family
ID=14242106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59099238A Pending JPS60244044A (en) | 1984-05-17 | 1984-05-17 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60244044A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5612242A (en) * | 1996-03-11 | 1997-03-18 | United Microelectronics Corp. | Trench isolation method for CMOS transistor |
-
1984
- 1984-05-17 JP JP59099238A patent/JPS60244044A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5612242A (en) * | 1996-03-11 | 1997-03-18 | United Microelectronics Corp. | Trench isolation method for CMOS transistor |
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