JPS60226168A - Complementary mos semiconductor device - Google Patents
Complementary mos semiconductor deviceInfo
- Publication number
- JPS60226168A JPS60226168A JP59083120A JP8312084A JPS60226168A JP S60226168 A JPS60226168 A JP S60226168A JP 59083120 A JP59083120 A JP 59083120A JP 8312084 A JP8312084 A JP 8312084A JP S60226168 A JPS60226168 A JP S60226168A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- well layer
- parts
- type well
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、相補型ＭＯ８Ｏ８半導体装置し１％に集積度
を向上できる分離構造を有する相補型ＭＯ８半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a complementary MO8O8 semiconductor device having an isolation structure capable of increasing the degree of integration to 1%.
従来の相補型ＭＯＳ半導体装置（以下ＣＭＯ８と称すン
は１通常第１図に示すよ５ＫＮ型シリコン基板１に選択
的ＫＰ型タウエルを形成し、該Ｎ型基板１およびＰ型ウ
ェル２上に選択的にフィールド酸化膜３を形成し、該Ｎ
型基板１およびＰ型ウェル２上にゲート酸化膜５．およ
び６を介して的えは多結晶シリコンからなるゲート電極
７および８を形成し、該ゲート電極７および８で自己整
合法によシ、Ｐ型拡散層であるソース轡ドレイン領域９
，１０．１１およびＮ型拡散層であるソース・ドレイン
領域１２．１３．１４を形成した構造になっている。In a conventional complementary MOS semiconductor device (hereinafter referred to as CMO8), a selective KP type well is formed on a 5K N type silicon substrate 1 as shown in FIG. A field oxide film 3 is formed, and the N
A gate oxide film 5. is formed on the type substrate 1 and the P-type well 2. Gate electrodes 7 and 8 made of polycrystalline silicon are formed through the gate electrodes 7 and 6, and the source and drain regions 9, which are P-type diffusion layers, are formed by a self-alignment method using the gate electrodes 7 and 8.
, 10.11 and source/drain regions 12, 13, and 14, which are N-type diffusion layers, are formed.
しかしながら、従来の０ＭＯ８ではＮ型拡散層であるソ
ース・ドレイン領域１２．１’３．１４とＮ型シリコン
基板１の間、およびＰ型ウェル２とＰ型拡散層であるソ
ースドレイン領域９，１０゜１】の間の各々におけるパ
ンチヌル−やラッチアップによる異常な消費電流の増加
、および製造工程におけるマスク合せの余裕をもたせる
ために。However, in the conventional 0MO8, between the source/drain region 12.1'3.14, which is an N-type diffusion layer, and the N-type silicon substrate 1, and between the P-type well 2 and the source-drain regions 9, 10, which are P-type diffusion layers, In order to prevent an abnormal increase in current consumption due to punch nulls and latch-up in each case between ゜1], and to provide margin for mask alignment in the manufacturing process.
Ｎ型シリコン基板１０Ｐ型拡散−１１とＰ型ウェル２の
Ｎ型拡散層１４との距離を１０μｍ以上とらなければな
らず、その結果集積度が低くなるという欠点があった。The distance between the N-type silicon substrate 10P-type diffusion -11 and the N-type diffusion layer 14 of the P-type well 2 must be at least 10 .mu.m, which has the disadvantage of lowering the degree of integration.
また、ＮｉＭシリコン基板１内の能動素子領域１ｏ、ｉ
ｔ間の絶縁分離の為に、選択酸化法によりフィールド酸
化膜３を厚く形成してフィールド領域の基板表面での反
転防止を行なっているが。In addition, active element regions 1o and i in the NiM silicon substrate 1
In order to insulate and separate the area between t and t, a thick field oxide film 3 is formed by a selective oxidation method to prevent inversion of the field region on the substrate surface.
選択酸化法では、フィールド酸化膜を厚くすればするほ
どフィールド酸化膜の横方向への拡がりも大きくなって
素子領域部が減少することになるので、設計上あらかじ
めその減少量を考慮して、素子領域幅を大きくとらなけ
ればならず、その結果集積度が低くなるという欠点があ
った。これは。In the selective oxidation method, the thicker the field oxide film is, the more the field oxide film spreads in the lateral direction, reducing the device area. This has the disadvantage that the area width must be increased, resulting in a lower degree of integration. this is.
Ｐウェル内の素子領域１２．１４間の絶縁分離について
も同様である。さらに、素子領域間の基板表面の反転防
止効果を強化する為１ｃ、フィールド領域下部に基板濃
度より高い濃度め拡散層を設けることがある。第１図で
はＰ型つェル内のフィールド領域下部に、Ｐ型ウェルよ
シ高濃度のＰ十拡散層４を設けた例を示している。この
場合、素子領域内に設けられたＭＯＳトランジスタのチ
ャンネル幅が狭くなるに従い、フィールド領域下部の高
濃度拡散層の横方向への拡がシが無視できなくなシ、狭
チャンネル効果と言われるＭＯＳ）ランジスタのしきい
値電圧が高くなる欠点が生じる為ＭＯ８）ランジスタの
チャンネル幅をある程度太きくしなければならず、その
結果集積度が低くなるという欠点があった。The same applies to the insulation isolation between the element regions 12 and 14 in the P-well. Furthermore, in order to strengthen the effect of preventing inversion of the substrate surface between the element regions, a diffusion layer with a concentration higher than the substrate concentration may be provided below the field region 1c. FIG. 1 shows an example in which a P-type diffusion layer 4 with a higher concentration than the P-type well is provided below the field region in the P-type well. In this case, as the channel width of the MOS transistor provided in the element region becomes narrower, the lateral expansion of the highly doped diffusion layer at the bottom of the field region becomes impossible to ignore, which is called the narrow channel effect. ) Since the threshold voltage of the transistor becomes high, MO8) The channel width of the transistor must be increased to some extent, which results in a low degree of integration.
本発明の目的は、上記欠点を除去し、素子分離領域を改
善し、拡散層間距離を短くしてもパンチスルーやラッチ
アップを防止でき、集積度を向上できる相補型ＭＯＳ半
導体装置を提供することにある。It is an object of the present invention to provide a complementary MOS semiconductor device that eliminates the above-mentioned drawbacks, improves the element isolation region, prevents punch-through and latch-up even when the distance between diffusion layers is shortened, and improves the degree of integration. It is in.
本発明の相補型ＭＯＳ半導体装置は、第１導電型の半導
体基板と、該基板上に設けられた第２導電型の半導体領
域と、前記基板上に設けられた第２導電型のウェル領域
と、該ウェル領域に設けられた第１導電型の半導体領域
とからなる相補型ＭＯＳ半導体装置において、前記基板
と前記ウェル領域の境界部分には該ウェル領域の深さよ
シ深い第１の溝を有し、少なくとも前記ウェル領域内の
前記第１導電型の半導体領域間の素子分離領域部分には
前記第１導電型の半導体領域の深さよシ深く前記ウェル
領域の深さより浅い第２の溝を有し前記第１および第２
の溝は絶縁物層で埋めこまれていることによシ構成され
る。A complementary MOS semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, a semiconductor region of a second conductivity type provided on the substrate, and a well region of a second conductivity type provided on the substrate. , a complementary MOS semiconductor device comprising a semiconductor region of a first conductivity type provided in the well region, a boundary portion between the substrate and the well region having a first groove deeper than the depth of the well region. At least in the element isolation region portion between the semiconductor regions of the first conductivity type in the well region, a second groove deeper than the depth of the semiconductor region of the first conductivity type and shallower than the depth of the well region is provided. and said first and second
The grooves are constructed by being filled with an insulating layer.
次ＶＣ，本発明の実施例について、図面を参照して説明
する。Next, embodiments of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例の断面図である。第２図にお
いて１．２１はＮ型シリコン基板、２２はＰＩウェル層
、３０け基板２１とウェル層２２との境界部分にウェル
層よシ深く形成された絶縁物層、２７は、前記境界部分
の絶縁物層３０下部に形成された基板２１よシ高濃度の
Ｎ型拡散層で。FIG. 2 is a sectional view of one embodiment of the present invention. In FIG. 2, 1.21 is an N-type silicon substrate, 22 is a PI well layer, 30 is an insulating layer formed deeper than the well layer at the boundary between the substrate 21 and the well layer 22, and 27 is the boundary portion. An N-type diffusion layer with a higher concentration than the substrate 21 is formed below the insulator layer 30.
３１は基板２１およびＰ型ウェル層２２Ｖｃおける素子
分離領域部分に素子領域となるＰおよびＮ型拡散層よシ
深く形成された絶縁物層％ ３４は基板２１上に形成さ
れたゲート酸化膜、３５はＰ型ウェル層２２上に形成さ
れたゲート酸化膜、３６はゲート酸化膜３４を介して基
板２１上に形成された多結晶シリコンからなるゲート電
極、３７はゲート酸化膜３５を介してＰ型ウェル層２２
上に形成された多結晶シリコンからなるゲート霜゛、極
。31 is an insulating layer formed deeper than the P- and N-type diffusion layers which become element regions in the element isolation region of the substrate 21 and the P-type well layer 22Vc; 34 is a gate oxide film formed on the substrate 21; 35 is a gate oxide film formed on the P-type well layer 22, 36 is a gate electrode made of polycrystalline silicon formed on the substrate 21 through the gate oxide film 34, and 37 is a P-type well layer formed on the gate oxide film 35. Well layer 22
A gate frost made of polycrystalline silicon is formed on top of the electrode.
３８．３９．４０はゲート電極３６で自己整合法により
形成されたＰ型拡散啼であるソース・ドレイン領域、４
１，４２．４３はゲート電極３７で自己整合法により形
成されたＮ型拡散層であるソース・ドレイン領域である
。38, 39, and 40 are source/drain regions, which are P-type diffusion regions formed by the self-alignment method in the gate electrode 36;
1, 42, and 43 are source/drain regions which are N-type diffusion layers formed by the self-alignment method in the gate electrode 37.
ここで重要なことは、Ｎ型基板２１とＰ型ウェル層２２
との境界に形成された絶縁物層３０は、Ｐ型ウェル層２
２より十分に深いこと、および素予分離領域に形成され
た絶縁物層３１は、ソース・ドレイン領域であるＰ型お
よびＮ型拡散層３８゜３９．４０，４１，４２．４３よ
シ十分に深いことである。これらの絶縁物層が深く形成
されていることにより、素子領域間の距離を縮めても、
ラッチアップやパンチスルーの発生を防止できるので集
積度の高い０ＭＯ８となる。What is important here is that the N type substrate 21 and the P type well layer 22
The insulating layer 30 formed at the boundary with the P-type well layer 2
2, and that the insulating layer 31 formed in the preliminary isolation region is sufficiently deeper than the P-type and N-type diffusion layers 38° 39.40, 41, 42.43, which are the source/drain regions. It's a deep thing. Because these insulator layers are formed deeply, even if the distance between element regions is shortened,
Since the occurrence of latch-up and punch-through can be prevented, 0MO8 has a high degree of integration.
また１本実施例構造によれば、フィールド領域の反転防
止の為に用いられるフィールド領域下部の基板濃度よシ
高濃度の拡散層は、素子領域内に設けられたＭＯＳ）ラ
ンジスタのチャンネル部より十分遠く離れることになり
、そのためチャンネル幅を狭くしていっても狭チャンネ
ル効果が生じないという利点も得られる。Furthermore, according to the structure of this embodiment, the diffusion layer at the lower part of the field region, which is higher in concentration than the substrate concentration and used to prevent inversion of the field region, has a higher concentration than the channel part of the MOS transistor provided in the element region. Since they are far apart, there is also the advantage that narrow channel effects do not occur even if the channel width is narrowed.
次に上記第２図に示した本実施例の作成方法を説明する
。Next, a method of creating the present embodiment shown in FIG. 2 above will be explained.
第３図（ａ）〜（２））は本発明の一実施例の作成方法
を説明するために工程順に示した断面図である。FIGS. 3(a) to 3(2) are cross-sectional views shown in the order of steps to explain the manufacturing method of an embodiment of the present invention.
まず、第３図（ａ）に示すように、Ｎ型シリコン基板２
１１Ｃ基板２１と逆導電型の不純物であるホウ素を選択
的にイオン注入して深さ６μｍのＰウェル層２２を形成
する。First, as shown in FIG. 3(a), an N-type silicon substrate 2
A P well layer 22 having a depth of 6 μm is formed by selectively implanting ions of boron, which is an impurity of a conductivity type opposite to that of the 11C substrate 21.
次に、第３図（ｂ）に示すように、シリコン基板２１及
びＰウェル層２２上に光蝕刻技術によシ素子分離領域が
除去されたレジストパターン２３（耐エツチング性マス
ク材）を形成し１反応性イオンエツチングによシレジス
トパターン２３がら露出するシリコン基板２１及びＰウ
ェル層２２表面を異方性エツチングして、深さがこの後
形成される素子領域の拡散層よりも２．５μｍ深い３μ
ｍのエツチング部２４を形成する。なおレジストパター
ン２３の除去部の巾は、従来の素子分離領域中よりも狭
い２μｍにした。Next, as shown in FIG. 3(b), a resist pattern 23 (etching-resistant mask material) from which the isolation region has been removed is formed on the silicon substrate 21 and the P-well layer 22 by photolithography. 1. The surfaces of the silicon substrate 21 and P well layer 22 exposed through the resist pattern 23 are anisotropically etched by reactive ion etching to a depth of 2.5 μm deeper than the diffusion layer of the element region to be formed later. 3μ
An etched portion 24 of m is formed. Note that the width of the removed portion of the resist pattern 23 was set to 2 μm, which is narrower than that in the conventional element isolation region.
次に第３図（ｅ）に示すように、レジストパターン２３
を除去して新たにシリコン基板２１及びＰウェル層２２
上に光蝕刻技術にょシ、シリコン基板２１とＰウェル層
２２の境界部分が除去されたレジストパターン２５（耐
エツチング性マスク材）を形成し、その後反応性イオン
エツチングによシレジストパターン２５から露出するシ
リコン基板２１及びＰウェル層２２の境界部公金異方性
エツチングして、深さがＰウェル層２２よシ３μｍ深い
９μｍのエツチング部２６を形成し、フィールド反転防
止用のリンをイオン注入して、エツチング部２６の底に
イオン注入層２７を形成した。なおレジストパターン２
５の除去部の幅は、従来の素子分離領域幅よりも狭い２
μｍにした。Next, as shown in FIG. 3(e), the resist pattern 23
is removed and a new silicon substrate 21 and P well layer 22 are formed.
A resist pattern 25 (etching-resistant mask material) is formed on the silicon substrate 21 and the P-well layer 22 by a photoetching technique, and then exposed from the resist pattern 25 by reactive ion etching. The boundary between the silicon substrate 21 and the P-well layer 22 is anisotropically etched to form an etched portion 26 with a depth of 9 μm, which is 3 μm deeper than the P-well layer 22, and phosphorus is ion-implanted to prevent field reversal. Then, an ion implantation layer 27 was formed at the bottom of the etched portion 26. Furthermore, resist pattern 2
The width of the removed portion 5 is narrower than the width of the conventional element isolation region 2.
It was set to μm.
次に、第３図（ｄ）に示すように、レジストパターン２
５を除去した後、９５０℃のスチーム雰囲気中で熱酸化
を施し約１０００人の熱酸化膜２８を形成し、さらに気
相成長法による醇化膜２９を１μｍ堆積して、前記エツ
チング部２４および２６内を熱酸化膜２８及び気相成長
法による酸化膜２９からなる絶縁物層で埋めつくした。Next, as shown in FIG. 3(d), the resist pattern 2
After removing 5, thermal oxidation is performed in a steam atmosphere at 950° C. to form a thermal oxide film 28 of approximately 1000 layers, and a 1 μm thick liquefied film 29 is deposited by vapor phase growth to form the etched portions 24 and 26. The inside was completely filled with an insulating layer consisting of a thermal oxide film 28 and an oxide film 29 formed by vapor phase growth.
次に、第３図（ｅ）に示すように、弗化アンモニウム液
による全面エツチングで、シリコン基板２１及びＰウェ
ル層２２上の酸化物膜の厚さ分だけエツチングし、素子
分離領域３０及び３１を形成し。Next, as shown in FIG. 3(e), the entire surface is etched using an ammonium fluoride solution, and the oxide film on the silicon substrate 21 and the P well layer 22 is etched by the thickness of the oxide film, and the element isolation regions 30 and 31 are etched. form.
その後、従来法によりＮ型シリコン基板２１及びＰウェ
ル層２２の上面にゲート酸化膜３２を形成し、さらに多
結晶シリコン層３３を形成した。Thereafter, a gate oxide film 32 was formed on the upper surfaces of the N-type silicon substrate 21 and the P-well layer 22 by a conventional method, and a polycrystalline silicon layer 33 was further formed.
次に、第３図（ｆ）ｖｃ示すように、Ｎ型シリコン基板
２１及びＰウェル層２２の上面にそれぞれゲート酸化膜
３４．３５を介して多結晶シリコンからなるゲート電極
３６．３７を形成し、さらにイオン注入法によシＮ型シ
リコン基板２１上にはソースΦドレイン領域となるＰ型
拡散層領域３８ 、３９゜４０をＰウェル層２２上には
、ソース・ドレイン領域となるＮ型拡散層領域４１，４
２．４３を形成した。拡散層深さは、それぞれ０．５μ
ｍである。Next, as shown in FIG. 3(f)vc, gate electrodes 36 and 37 made of polycrystalline silicon are formed on the upper surfaces of the N-type silicon substrate 21 and the P well layer 22 through gate oxide films 34 and 35, respectively. Furthermore, by ion implantation, P-type diffusion layer regions 38 and 39° 40, which will become source/drain regions, are formed on the N-type silicon substrate 21, and N-type diffusion layer regions 38 and 39° 40, which will become source/drain regions, are formed on the P-well layer 22. Layer regions 41, 4
2.43 was formed. The depth of the diffusion layer is 0.5μ each.
It is m.
次に、第３図（ｇ）に示すように、気相成長法によシリ
ンガラス層４４を全面に被着し、Ｐチャンネル、Ｎチャ
ンネル側のゲート、ソース、ドレインと接続する取出し
電極４５を形成すると相補型ＭＯ８半導体装置が完成す
る。Next, as shown in FIG. 3(g), a silicone glass layer 44 is deposited on the entire surface by vapor phase growth, and lead-out electrodes 45 are formed to connect to the gate, source, and drain on the P-channel and N-channel sides. Once formed, a complementary MO8 semiconductor device is completed.
なお、上記実施例ではＮ型半導体基板ＫＰウェル層を形
成する場合について説明したが、Ｐ型半導体基板にＮウ
ェル層を形成する場合にも適用することができる。In the above embodiments, the case where a KP well layer is formed on an N-type semiconductor substrate has been described, but the present invention can also be applied to a case where an N-well layer is formed on a P-type semiconductor substrate.
また、上記実施例では、絶縁分離用の絶縁分離用の絶縁
物層として、シリコン酸化膜を用いたが絶縁物はこれＶ
Ｃ′、限定されず、窒化膜やノンドープのシリコン層や
リンガラス層などを適用してもよい。In addition, in the above embodiment, a silicon oxide film was used as an insulator layer for insulation isolation, but this insulator was
C' is not limited, and a nitride film, a non-doped silicon layer, a phosphorus glass layer, or the like may be applied.
さらに、上記実施例では、フィールド反転防止用の拡散
層を、基板とウェル層の境界部分に設けられた絶縁物下
部のみに設けたが、素子分離領域に設けられた絶縁物層
下部に設けてもよい。Furthermore, in the above embodiment, the diffusion layer for preventing field reversal was provided only under the insulator provided at the boundary between the substrate and the well layer, but it was also provided under the insulator layer provided in the element isolation region. Good too.
以上説明したとおシ、本発明により得られた相補型ＭＯ
８半導体装置は、半導体基板とウェル層の境界部にウェ
ル層よシも深い絶縁物層が存在するばかシでなく、素子
分離領域にも素子として使用される拡散層よりも深い絶
縁物層が存在する構造となっているので、拡散層間距離
を従来より著しく短くしても、パンチスルーやラッチア
ップを防止できるため、集積度を向上させることができ
る。As explained above, complementary MO obtained by the present invention
8 Semiconductor devices do not simply have an insulating layer deeper than the well layer at the boundary between the semiconductor substrate and the well layer, but also have an insulating layer deeper than the diffusion layer used as the element in the element isolation region. Because of this structure, punch-through and latch-up can be prevented even if the distance between the diffusion layers is made significantly shorter than in the past, and the degree of integration can be improved.
第１図は従来の相補型ＭＯ８半導体装置の断面図、第２
図は本発明の一実施例の断面図、第３図（ａ）〜（ｇ＞
は第２図の本発明の一実施例の製造方法を説明するため
に工程順に示した断面図である。
１・・・・・・Ｎ型シリコン基板、２・・・・・・Ｐ型
ウェル、３・・・・・・フィールド酸化膜、４・・・・
・・Ｐ 拡散層、５゜６・・・・・・ゲート酸化膜、７
，８・・・・・・ゲート電極、９゜１０．１１・・・・
・・Ｐ型拡散層のソース・ドレイン領域、、１２，１３
．１４・・・・・・Ｎ型拡散層のソース・ドレイン、２
１・・・・・・Ｎ型シリコン基板、２２・・・・・・Ｐ
ウェル、２３・−・・・・レジメトパターン、２４・・
・・・・エツチング部、２５・・・・・・レジストパタ
ーン、２６・・・・・・エツチング部、２７・・・・・
・反転防止用のイオン注入層、２８・・・・・・熱酸化
膜、２９・・・・・・気相成長酸化膜、３０．３１・・
・・・・素子分離領域、３２・・・・・・ゲート酸化膜
、３３・・・・・・多結晶シリコン層、３４゜３５・・
・・・・ゲート酸化膜、３６．３７・・・・・・ゲート
電極、３８．３９，４０・・・・・・Ｐ型拡散層である
ソース・ドレイン、４１，４２，４３・・・・・・Ｎ型
拡散層であるソース・ドレイン、４４・・・・・・リン
ガラス層。
４５・・・・・・電極金属。
警１耐
殆２圀Figure 1 is a sectional view of a conventional complementary MO8 semiconductor device, Figure 2 is a cross-sectional view of a conventional complementary MO8 semiconductor device;
The figure is a sectional view of one embodiment of the present invention, and FIGS. 3(a) to (g>
3A and 3B are cross-sectional views shown in the order of steps for explaining the manufacturing method of the embodiment of the present invention shown in FIG. 2. FIG. 1... N-type silicon substrate, 2... P-type well, 3... field oxide film, 4...
...P diffusion layer, 5゜6...gate oxide film, 7
, 8... Gate electrode, 9°10.11...
・Source/drain region of P-type diffusion layer, 12, 13
．． 14... Source/drain of N-type diffusion layer, 2
1...N-type silicon substrate, 22...P
Well, 23... Regimen pattern, 24...
...Etching part, 25...Resist pattern, 26...Etching part, 27...
- Ion implantation layer for preventing reversal, 28... thermal oxide film, 29... vapor phase growth oxide film, 30.31...
...Element isolation region, 32...Gate oxide film, 33...Polycrystalline silicon layer, 34°35...
...Gate oxide film, 36.37... Gate electrode, 38.39, 40... Source/drain which is P type diffusion layer, 41, 42, 43... . . . Source/drain which is an N-type diffusion layer, 44 . . . Phosphorous glass layer. 45... Electrode metal. Police 1 hours almost 2 hours
Claims (1)
導電型の半導体領域と、前記基板上に設けられた第２導
電型のウェル領域と、該ウェル領域に設けられた第１導
電型の牛纏体飴域とからなる相補型ＭＯ８＃−碑体装置
において、前記基板と前記ウェル領域の境界部分には該
ウェル領域の深さよシ深い第１の溝を有し、少なくとも
前記ウェル領域内の前記第１４電型の半導体領域間の素
子分離領域部分には、前記第１導電型の半導体領域の深
さよシ深く前記ウェル領域の深さよシ浅い第２の溝を有
し、前記第１および第２の溝は絶縁物層で埋めこまれて
いることを特徴とする相補型ＭＯ８半導体装置。a first conductivity type semiconductor substrate; a second conductivity type semiconductor substrate provided on the substrate;
Complementary type MO8#- monument consisting of a conductivity type semiconductor region, a second conductivity type well region provided on the substrate, and a first conductivity type cow wrap area provided in the well region. In the device, a first groove deeper than the depth of the well region is provided at a boundary between the substrate and the well region, and at least a portion of an element isolation region between the semiconductor regions of the fourteenth voltage type in the well region is provided. has a second trench that is deeper than the depth of the semiconductor region of the first conductivity type and shallower than the depth of the well region, and the first and second trenches are filled with an insulating layer. A complementary MO8 semiconductor device characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59083120A JPS60226168A (en) | 1984-04-25 | 1984-04-25 | Complementary mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59083120A JPS60226168A (en) | 1984-04-25 | 1984-04-25 | Complementary mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60226168A true JPS60226168A (en) | 1985-11-11 |
Family
ID=13793341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59083120A Pending JPS60226168A (en) | 1984-04-25 | 1984-04-25 | Complementary mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60226168A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100434333B1 (en) * | 2002-06-28 | 2004-06-04 | 주식회사 하이닉스반도체 | method for manufacturing semiconductor device and the same |
| JP2012160652A (en) * | 2011-02-02 | 2012-08-23 | Fujitsu Semiconductor Ltd | Semiconductor device and method of manufacturing the same |
| US20150279879A1 (en) * | 2013-03-12 | 2015-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varied STI Liners for Isolation Structures in Image Sensing Devices |
-
1984
- 1984-04-25 JP JP59083120A patent/JPS60226168A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100434333B1 (en) * | 2002-06-28 | 2004-06-04 | 주식회사 하이닉스반도체 | method for manufacturing semiconductor device and the same |
| JP2012160652A (en) * | 2011-02-02 | 2012-08-23 | Fujitsu Semiconductor Ltd | Semiconductor device and method of manufacturing the same |
| US20150279879A1 (en) * | 2013-03-12 | 2015-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varied STI Liners for Isolation Structures in Image Sensing Devices |
| US10008531B2 (en) * | 2013-03-12 | 2018-06-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varied STI liners for isolation structures in image sensing devices |
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