JPS5940563A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5940563A JPS5940563A JP57150960A JP15096082A JPS5940563A JP S5940563 A JPS5940563 A JP S5940563A JP 57150960 A JP57150960 A JP 57150960A JP 15096082 A JP15096082 A JP 15096082A JP S5940563 A JPS5940563 A JP S5940563A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- well
- forming
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係υ、特にＣＭＯ８
型半導体装置の製造方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, particularly a CMO8
The present invention relates to a method for manufacturing a type semiconductor device.
ＣＭＯ８型半導体装置は、消費電力が小さく大きなノイ
ズマージンが得られる等の特長を有し、将来の超ＬＳＩ
形成のための重要な技術として注目されている。しかし
、この装置では１つのチップの上にｎ型の基板とｐ型の
基板金持ち、それぞれの基板に形成されたｐチャネル及
びｎチャネルトランジスタを相互に接続して回路が構成
されるため、高集積化には解決すべき数々の問題が残っ
ている。特に問題となるのは、ウェルの形成方法とその
分離であシ、ウェルの微細化が困難であるばかシか、ウ
ェル境界部近くに形成するとＰｎＰｎの寄生構造でのス
イッチング（所謂ラッチアッフ０現象）が生じ、回路が
破壊される等の不都合があった。The CMO8 type semiconductor device has features such as low power consumption and large noise margin, and will be used in future VLSIs.
It is attracting attention as an important technology for formation. However, in this device, a circuit is constructed by interconnecting an n-type substrate and a p-type substrate on one chip, and interconnecting p-channel and n-channel transistors formed on each substrate, so it is highly integrated. There are still many problems that need to be resolved. Particular problems arise in the method of forming wells and their separation.Not only is it difficult to miniaturize the well, but if it is formed near the well boundary, switching occurs due to the PnPn parasitic structure (the so-called latch-up phenomenon). This caused problems such as damage to the circuit.
以下、この問題’ｉ ＣＭＯＳインバータを例にとり説
明する。第１図（ａ）〜（ｃ）は従来のＣＭＯＳインバ
ータ製造工程を示す断面図である。まず、第１図（８）
に示す如く、ｎ型半導体基板１上に５１０２膜からなる
マスク層２を形成し、その開口部を通してポロ／（Ｂ）
を、例えば１００〔ｋｖ〕の加速電圧、２〜３ｘｔｏ［
ｃｍ：］のドーズ量でイオン注入する。ここで、図中３
がイオン注入領域である。次いで１２００〔℃〕約８時
間の熱処理を行い、第１図（ｂ）に示す如くポロンを拡
散させ、接合深さが５〜６〔μｍ〕となるようにする。This problem will be explained below using an example of a CMOS inverter. FIGS. 1(a) to 1(c) are cross-sectional views showing a conventional CMOS inverter manufacturing process. First, Figure 1 (8)
As shown in FIG. 1, a mask layer 2 consisting of a 5102 film is formed on an n-type semiconductor substrate 1, and a Porro/(B) film is formed through the opening of the mask layer 2.
For example, an accelerating voltage of 100 [kv], 2 to 3xto[
Ion implantation is performed at a dose of cm:]. Here, 3 in the figure
is the ion implantation region. Next, a heat treatment is performed at 1200° C. for about 8 hours to diffuse the poron as shown in FIG. 1(b), so that the bonding depth becomes 5 to 6 μm.
このようにして形成されたＰ型拡散層ｐ−ウェル４であ
る。This is the P-type diffusion layer p-well 4 formed in this manner.
次に、上記マスク層２ｆ：、除去し、第１図（ｃ）に示
す如くフィールド酸化膜５、ダート酸化膜６ ａ。Next, the mask layer 2f is removed, and a field oxide film 5 and a dirt oxide film 6a are formed as shown in FIG. 1(c).
６ｂ、ダート電極７ａ 、７ｂを形成し、さらにソース
・ドレインとなるＰ拡散層８＊、９ｇ及びＮ＋拡散層ｓ
ｂ ｔ ９ｂ等を形成し、ｐ−チャネルトランジスタ
１０ａ及びｎ−チャネルトランジスタ１０ｂを形成する
。その後、絶縁膜を介してＡｔの配線等を形成し、必要
な電気的接続を施すことによって、ＣＭＯＳインバータ
が作成されることになる。6b, dirt electrodes 7a, 7b are formed, and P diffusion layers 8*, 9g and N+ diffusion layer s, which become sources and drains.
p-channel transistor 10a and n-channel transistor 10b are formed. Thereafter, a CMOS inverter is created by forming At wiring and the like through an insulating film and making necessary electrical connections.
このような従来の方法によると、イオン注入されたゾロ
ンを熱拡散させ５〜６〔μｍ〕の接合深さを持つｐ−ウ
ェル４を形成する際、ポロンが＋１へ方向にも約４〜５
〔μｍ〕拡散するため、ｐウニ、領域も横方向に拡がる
。しだがって、小さなエルを精度よく形成することは困
難であった。According to such a conventional method, when the p-well 4 having a junction depth of 5 to 6 [μm] is formed by thermally diffusing the ion-implanted zolon, the poron also spreads in the +1 direction by about 4 to 5 μm.
[μm] Due to the diffusion, the p region also expands laterally. Therefore, it has been difficult to form small ells with high precision.
また、第１図（ｃ）に示したようにｐチャネルトランジ
スタ１０ａのドレイン９ａ％ ｎ型基板１、ｐ−ウェル
４及びｎチャネルトランジスタ１０ｂのソー７８ｂの間
にｐｎｐｎの寄生構造が形成され、これが回路動作中に
ＯＮすると回路が破壊されるという、所謂ラッチ・アッ
プ現象が生じる。これを防止するためには１層９ａ（ド
レイン）と一層８ｂ（ソース）との間隔を十分に離す必
要があシ、これがＣＭＯ８ＩＣの微細化を妨げる大きな
要因となっていた。なお、上述した問題はＣＭＯＳイン
バータに限らず各種のＣＭＯ８型半導体装置についても
同様に云えることである。Further, as shown in FIG. 1(c), a pnpn parasitic structure is formed between the drain 9a% of the p-channel transistor 10a, the n-type substrate 1, the p-well 4, and the source 78b of the n-channel transistor 10b. If turned on during circuit operation, a so-called latch-up phenomenon occurs in which the circuit is destroyed. In order to prevent this, it is necessary to provide a sufficient distance between the first layer 9a (drain) and the first layer 8b (source), and this has been a major factor hindering the miniaturization of CMO8 ICs. Note that the above-mentioned problem is not limited to CMOS inverters, but also applies to various CMO8 type semiconductor devices.
〔発明の目的〕
本発明の目的は、小さなウェルを精度良く形成すること
ができ、かつラッチ・アップ等の発生を未然に防止する
ことができ、ＣＭＯ８型半導体装置の微細化及び信頼性
向上に害毒し得る半導体装置の製造方法を提供すること
にある。[Object of the Invention] An object of the present invention is to be able to form small wells with high precision, to prevent latch-up, etc., and to contribute to the miniaturization and reliability improvement of CMO8 type semiconductor devices. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be harmful.
本発明の骨子は、ウェルと基板との間或いはウェル間に
溝を設け、この溝に絶縁膜を埋め込むことにある。The gist of the present invention is to provide a groove between a well and a substrate or between wells, and to fill this groove with an insulating film.
すなわち本発明は、半導体基板上の一部に該基板と逆導
電型のウェルを形成し、このウェル及び基板上にそれぞ
れ能動素子を形成して半導体装置を製造するに際し、上
記基板上のウェル形成領域外に１層以上の第１の被膜を
形成したのち、この被膜の周辺部の基板を選択エツチン
グして溝部を形成し、次いで上記溝部に絶縁膜を埋め込
み、しかるのち上記被膜及び絶縁膜をマスクとし前記基
板に該基板と逆導電型の不純物をドーピングするように
した方法である。That is, the present invention provides a method for manufacturing a semiconductor device by forming a well of a conductivity type opposite to that of the substrate in a part of the semiconductor substrate, and forming active elements on the well and the substrate, respectively. After forming one or more layers of the first coating outside the area, selectively etching the substrate around the coating to form a groove, filling the groove with an insulating film, and then removing the coating and the insulating film. In this method, the substrate is doped with an impurity of a conductivity type opposite to that of the substrate using a mask.
また本発明は、半導体基板上に第１導電型の第１ウエル
及び第２導電型の第２ウエルを形成し、これらのウェル
上にそれぞれ能動素子を形成して半導体装置を製造する
に際し、上記基板の第２ウエル形成領域上に１層以上の
第１の被膜を形成したのち、この被膜の周辺部の基板全
選択エツチングして溝部を形成し、次いで上記溝部に絶
縁膜を埋め込み、次いで上記第１の被膜及び絶縁膜をマ
スクとして第１ウエル形成領域上に第１導電型の不純物
をドーピングし、次いで上記第１ウエル形成領域上に第
３の被膜を形成し、次いで前記第１の被膜を除去し、し
かるのち上記第３の被膜をマスクとして前記第２ウエル
形成領域上に第２導電型の不純物をドーピングするよう
にした方法である。Further, the present invention provides a method for manufacturing a semiconductor device by forming a first well of a first conductivity type and a second well of a second conductivity type on a semiconductor substrate, and forming active elements on these wells, respectively. After forming one or more first layers on the second well formation region of the substrate, etching the entire substrate around the periphery of this film to form a groove, then filling the groove with an insulating film, and then A first conductivity type impurity is doped onto the first well formation region using the first film and the insulating film as a mask, and then a third film is formed on the first well formation region, and then the first film is doped with a first conductivity type impurity. In this method, the second conductive type impurity is doped onto the second well formation region using the third film as a mask.
本発明によれば、溝部に埋め込んだ絶縁膜によりウェル
の横方向の拡がシが規定されるため、小さなウェルを精
度良く形成することができる。According to the present invention, since the lateral expansion of the well is defined by the insulating film embedded in the trench, a small well can be formed with high precision.
さらに、溝部に埋め込んだ絶縁膜によシ各素子間が確実
に分離されるため、ラッチアップ現象等を招くこともな
い。したがって、ＣＭＯ８半導体装置の微細化及び信頼
性向上に絶大なる効果を発揮する。Furthermore, since each element is reliably isolated by the insulating film embedded in the groove, latch-up phenomena and the like are not caused. Therefore, it is extremely effective in miniaturizing and improving reliability of CMO8 semiconductor devices.
第２図（ａ）〜（ｈ）は本発明の第１の実施例に係わる
ＣＭＯＳインバータ製造工程を示す断面図である。FIGS. 2(a) to 2(h) are cross-sectional views showing the CMOS inverter manufacturing process according to the first embodiment of the present invention.
まず、第２図（、）に示す如くｎ型シリコン基板（半導
体基板）１ノ上に、熱酸化膜（５ｉｎ２膜）１２及びＳ
ｉ 、Ｎ４膜１３からなる第１の被膜をそれぞれ例え
ば１０００［Ｘ）形成する。続いて、例えばフォトレジ
スト１４を選択的に形成し、とのレジスト１４をマスク
として８１．Ｎ４膜１３及び５ｉｎ２膜１２をエツチン
グ除去する。次いで、第２図（ｂ）に示す如く全面に例
えばプラズマ５１０２膜（第２の被膜）１５を約１０〔
μｍ〕形成する。その後この試料を例えばＮＨ４Ｆで約
２０〜３０秒エツチングし、第２図（ｃ）に示す如く段
差部においてのみグラズマ５ｉｎ２１５をエツチング除
去する。First, as shown in FIG. 2(,), a thermal oxide film (5in2 film) 12 and an S
i, and a first film consisting of the N4 film 13 is formed at a thickness of, for example, 1000 [X]. Subsequently, for example, a photoresist 14 is selectively formed, and the resist 14 is used as a mask to form 81. The N4 film 13 and the 5in2 film 12 are removed by etching. Next, as shown in FIG. 2(b), for example, a plasma 5102 film (second coating) 15 is applied over the entire surface for about 10 minutes.
[μm] is formed. Thereafter, this sample is etched with, for example, NH4F for about 20 to 30 seconds, and the glazma 5in215 is etched away only at the stepped portion, as shown in FIG. 2(c).
次に、フォトレジスト膜１４を除去すると共にレジスト
１４上のプラズマ８１０□膜１５をリフトオフによシ除
去する。次いで、第２図（ｄ）に示す如くＳｉ３Ｈ４膜
１３及び残置されたプラズマ５１０２膜１５をマスクと
して、シリコン基板１１を方向性エツチング法により選
択エツチングし、前記第１の被膜のパターン周辺に溝部
１６を５〜１０〔μｍ〕の深さに形成する。続いて、プ
ラズマ８１０□膜１５をエツチング除去したのち、第２
図（、）に示す如く全面に例えばＣｖＤＳＩ０２膜（絶
縁膜）１７を約２０００［Ｘ）堆積させ、前記溝部１６
を埋めると同時に全面を覆う。次いで、方向性エツチン
グ法によシ全面エツチングを施し、ＳｉＯ２膜１７全１
７０００［Ｘ］除去すると第２図（ｆ）に示す如く、溝
部１６が５ＩＯ２膜１７で充填された構造となる。続い
て、Ｓ ｉ ３Ｎ４膜１３及び５ｌｏ２膜１７をマスク
として、ボロ７（Ｂ）を拡散しｐウェル１８を形成する
。ここで、上記ポロンの拡散はポロンナイトライドを用
いた気相拡散で吃よいし、ポロンのイオン注入とドライ
ブイン拡散とを組み合わせたものでもよい。Next, the photoresist film 14 is removed and the plasma 810□ film 15 on the resist 14 is removed by lift-off. Next, as shown in FIG. 2(d), using the Si3H4 film 13 and the remaining plasma 5102 film 15 as masks, the silicon substrate 11 is selectively etched by a directional etching method to form grooves 16 around the pattern of the first film. is formed to a depth of 5 to 10 [μm]. Subsequently, after removing the plasma 810□ film 15 by etching, the second
As shown in FIG.
Fill in the area and cover the entire surface at the same time. Next, the entire surface of the SiO2 film 17 is etched using a directional etching method.
When 7000[X] is removed, the groove 16 is filled with the 5IO2 film 17, as shown in FIG. 2(f). Subsequently, using the S i 3N4 film 13 and the 5lo2 film 17 as a mask, the boro 7 (B) is diffused to form a p-well 18. Here, the diffusion of poron may be accomplished by vapor phase diffusion using poron nitride, or may be achieved by a combination of poron ion implantation and drive-in diffusion.
次に、第２図（ｇ）に示す如くＳｉ３Ｈ４膜１３及び５
ｉｎ２膜１２′ｔ−除去する。そして、第２図（ｈ）に
示す如くフィールド酸化膜１９、ケ゛−ト酸化膜２０ｍ
１２０ｂ、ダート電極２１ ａ ＊ ２ ｌ ｂ −ソ
ース・ドレインとなるＰ拡散層２２ ａ 、 ２３ｍ及
びＮ拡散層２２ｂ、２３ｂ等全形成する。その後、従来
方法と同様に層間絶縁膜やＡｔ配線等を形成することに
よってＣＭＯＳインバータが作製されることになる。Next, as shown in FIG. 2(g), the Si3H4 films 13 and 5
in2 film 12't-removed. Then, as shown in FIG. 2(h), a field oxide film 19 and a gate oxide film 20m are formed.
120b, the dirt electrode 21a*2lb - P diffusion layers 22a, 23m which will become the source/drain, and N diffusion layers 22b, 23b, etc. are all formed. Thereafter, a CMOS inverter is manufactured by forming an interlayer insulating film, At wiring, etc. in the same manner as in the conventional method.
かくして本実施例方法によれば、ｎウェル１８を形成す
るだめの拡散工程に際し、両側が５ｌｏ２膜１７で囲ま
れているためポロンは横方向には拡散しない。このため
、微細なｐ−ウェル領域を容易に形成することができる
。また、ｐチャネルトランジスタのソース若しくはドレ
イン２３ｇ及びｎチャネルトランジスタのソース若しく
はドレイン２２ｂｆ：第２図（ｈ）に示した如く近接さ
せても、溝部１６に充填された５１０２膜１７によって
各トランジスタが隔られているため、ラッチアップ現象
を、従来法によって十分能した構造をとった場合と同じ
かそれ以上に起こし難くすることができる。したがって
、ＣＭＯＳインバータの微細化を極めて容易に実現する
ことができた。なお、前述した溝部１６を形成すること
によって、ウェルの分離を実現する方法はこれまでにも
いろいろ試みられているが、溝を形成するだめのマスク
形成工程とｐウェル拡散を行うためのマスク形成工程が
それぞれ別々に行われていたため、工程も複雑になシ、
さらに微細なｐ−ウェルを形成することにおいても不利
であった。これに対し、本実施例では溝を形成するため
のマスク形成工程をセルファラインで行うことができ、
さらにｐウェル拡散のだめのマスクを溝形成のだめのマ
スクとしても用いているので、その工程が極めて容易に
なる等の利点もある。Thus, according to the method of this embodiment, during the diffusion step for forming the n-well 18, poron does not diffuse laterally because both sides are surrounded by the 5lo2 film 17. Therefore, a fine p-well region can be easily formed. Furthermore, even if the source or drain 23g of the p-channel transistor and the source or drain 22bf of the n-channel transistor are placed close to each other as shown in FIG. Therefore, the latch-up phenomenon can be made as difficult as or more difficult to occur than in the case of a structure that is sufficiently effective by the conventional method. Therefore, miniaturization of the CMOS inverter could be realized extremely easily. Various methods have been tried to achieve well isolation by forming the trenches 16 described above, but the mask formation process for forming the trenches and the mask formation for p-well diffusion are difficult. The process was complicated because each process was performed separately.
Furthermore, it was disadvantageous in forming a fine p-well. In contrast, in this embodiment, the mask forming process for forming the groove can be performed on the self-line,
Furthermore, since the mask for p-well diffusion is also used as a mask for trench formation, there is an advantage that the process becomes extremely easy.
第３図（ａ）、（ｂ）は第２の実施例に係わる工程断面
図である。この実施例が先に説明した第１の実施例と異
なる点は、前記半導体基板としてπ型基板３１を用いた
ことにある。すなわち、π型基板３１を用い前記第２図
（ｆ）までは先の実施例と同様の工程とし、その後５１
３Ｎ４膜１３をマスクとして選択酸化を行い第３図（、
）に示す如く酸化膜（５ｔＯ２膜）３２を形成する。次
いで、Ｓｔ Ｎ膜１３及びＳｉＯ２膜１２全１２したの
ち、４
第３図（ｂ）に示す如くヒ素（Ａｓ ）等のｎ型の不純
物を選択酸化によって形成された５ｉｏ２１摸（第３の
被膜）３２をマスクに基板３ノに導入しｎウェル３３を
形成する。これによシ、π型基板３１上にｎ−ウェル３
３及びｐ−ウェル１８を同時に形成することができ、か
つこれらｆ：５ｉｏ２膜３２で分離した構造が実現され
ることになる。FIGS. 3(a) and 3(b) are process cross-sectional views relating to the second embodiment. This embodiment differs from the first embodiment described above in that a π-type substrate 31 is used as the semiconductor substrate. That is, using the π-type substrate 31, the steps up to the step shown in FIG.
Selective oxidation is performed using the 3N4 film 13 as a mask as shown in FIG.
), an oxide film (5tO2 film) 32 is formed. Next, after removing the StN film 13 and the SiO2 film 12, a 5io21 sample (third film) formed by selective oxidation of n-type impurities such as arsenic (As) is formed as shown in FIG. 3(b). 32 is introduced into the substrate 3 using a mask to form an n-well 33. With this, the n-well 3 is placed on the π-type substrate 31.
3 and p-well 18 can be formed at the same time, and a structure separated by these f:5io2 films 32 is realized.
したがって、この実施例によっても先の第１の実施例と
同様の効果が得られるのは勿論のことである。なお、前
記ｐウェルとｎウェルとの形成順序は逆に行ってもよい
。また、基板として先の実施例と同じくｎ型の基板１１
を用いて酸化膜３２をマスクに行うイオン注入を、例え
ばｎ型基板１ノにおけるフィールド反転防止及びチャネ
ル部の閾値コントロールを目的に行ってもよい。この場
合、例えばＡｓのイオン注入が用イられ５０ｋｖ〜１０
０Ｋｖで、５×１♂１〜１ｏ１３の範囲のドーズ景で・
イオン注入すればよい。Therefore, it goes without saying that this embodiment also provides the same effects as the first embodiment. Note that the formation order of the p-well and n-well may be reversed. Also, as a substrate, an n-type substrate 11 is used as in the previous embodiment.
Ion implantation using the oxide film 32 as a mask may be performed, for example, for the purpose of preventing field inversion in the n-type substrate 1 and controlling the threshold value of the channel portion. In this case, for example, As ion implantation is used to
At 0Kv, with a dose range of 5×1♂1 to 1o13.
All you need to do is implant ions.
第４図は第３図の実施例に係わる工程断面図である。こ
の実施例は先の第１の実施例の改良であシ、前記第２図
（ｄ）の段階で溝部１６の底部にｎ型の不純物をイオン
注入し、ｎ型不純物の高濃度不純物層４１をｎ型基板１
１内に形成した場合を示す。この様な構造をとるとｐ−
ウェル１８の界面における空気層のｎ基板１ノ側におけ
る空気層の形状は第４図中に破線で示す如くなっている
。すなわち、空気層の拡がシが高濃度層４１によってお
きかとられるため、ラッチアップやパンチスルーの耐圧
をさらに筒くすることができる。FIG. 4 is a cross-sectional view of the process related to the embodiment of FIG. 3. This embodiment is an improvement on the first embodiment, in which n-type impurity ions are implanted into the bottom of the trench 16 in the step shown in FIG. The n-type substrate 1
1 is shown. With this structure, p-
The shape of the air layer on the n-substrate 1 side of the air layer at the interface of the well 18 is as shown by the broken line in FIG. That is, since the expansion of the air layer is prevented by the high concentration layer 41, the withstand pressure for latch-up and punch-through can be further increased.
なお、本発明は上述した各実施例に限定されるものでは
ない。前記第１の本実施例では、プラズマ５１０２膜１
５をリフト・オフによって除去してからシリコン基板１
１の選択エツチングを行ったが、これは必ずしも行わな
くてもよい。Note that the present invention is not limited to the embodiments described above. In the first embodiment, the plasma 5102 film 1
5 is removed by lift-off, and then silicon substrate 1 is removed.
1 selective etching was performed, but this need not necessarily be performed.
すなわち、第２図（ｃ）の状態でシリコン基板１１のエ
ツチングを行うようにしてもよい。また、前記溝部への
絶縁膜の充填としてＣｖＤＳＩＯ２膜１５の堆積全１５
たが、この代シに熱酸化を行ってもよい。さらに、残置
されたプラズマ５１０２膜１７を除去してから溝部１６
への絶縁物の充填を行っているが、５ｉ０２膜１５の除
去前、すなわち第２図（ｄ）の段階で行ってもよい。ま
た、前記第１の被膜としてレジスト／５１３Ｎ４／５Ｉ
Ｏ２を用いて説明したが、これ以外のいかなる組合せで
もよい。例えばレジストのかわりにＡｔを用いてもよい
し、５ｔＯ２膜或いはＳ ｉ ３Ｎ、膜単独であっても
よい。また、段差部でのエツチング速度が平坦部でのエ
ツチング速度よシも速い膜としてプラズマ５１０２膜の
場合についてのみ述べたが、これ以外のもの例えばプラ
ズマ８１３Ｎ４、プラズマＰＳＧ膜或いはスパッタリン
グで堆積されたＳｉ０ 、８１．Ｎ４． ＰＳＧ膜等
でもよい。さらに、Ａｔの蒸着を用いて段差部で薄くな
った膜を等方エツチングで除去して、残った）、ｔｔＪ
？タンを用いても同様の効果が得られる。また、このよ
うな性質の膜を一切用いずマスク合せ工程を用いてマヌ
ク材を第２図（ｄ）に示す如く残置しても本発明の主旨
を逸脱するものではない。また、第２図（ｈ）では図示
されたｎチャネルトランジスタとドチャネルトランジス
タとの分離はウェルの分離用酸化膜１７をそのまま用い
てい、るが、これに加えフィールド酸化膜で分離を行っ
てもよい。That is, the silicon substrate 11 may be etched in the state shown in FIG. 2(c). In addition, a CvDSIO2 film 15 is deposited to fill the trench with an insulating film.
However, thermal oxidation may be performed instead. Furthermore, after removing the remaining plasma 5102 film 17, the groove portion 16
Although the insulator is filled with the insulator, it may be filled with the insulator before the removal of the 5i02 film 15, that is, at the stage shown in FIG. 2(d). Further, as the first coating, resist/513N4/5I
Although the explanation has been made using O2, any other combination may be used. For example, At may be used instead of the resist, or a 5tO2 film, a Si 3N film, or a film alone may be used. In addition, only the case of the plasma 5102 film has been described as a film in which the etching rate at the stepped portion is faster than the etching rate at the flat portion, but other films such as plasma 813N4, plasma PSG film, or Si0 deposited by sputtering are also used. , 81. N4. A PSG film or the like may also be used. Furthermore, by using At vapor deposition, the film that became thinner at the step part was removed by isotropic etching, and the remaining), ttJ
? A similar effect can be obtained using tongue. Further, it does not depart from the spirit of the present invention even if the mask-aligning process is used without using any film having such properties and the manuku material is left as shown in FIG. 2(d). In addition, in FIG. 2(h), the illustrated n-channel transistor and do-channel transistor are separated using the isolation oxide film 17 of the well as is, but in addition to this, isolation may be performed using a field oxide film. good.
さらに、フィールド酸化膜の形成はいかなる方法を用い
て形成してもよく、いわゆる従来のＬＯＣＯ８法、埋め
込み酸化膜による方法など何を用いてもよいことは言う
までもない。要するに本発明は、その要旨を逸脱しない
範囲で、種々変形して実施することができる。Furthermore, it goes without saying that the field oxide film may be formed using any method, including the so-called conventional LOCO8 method, a buried oxide film method, and the like. In short, the present invention can be implemented with various modifications without departing from the gist thereof.
第１図（、）〜（ｃ）は従来のＣＭＯＳインバータ製工
程を示す断面図、第２図（、）〜（ｈ）は本発明の第１
の実施例に係わるＣＭＯＳインバータ製造工程を示す断
面図、第３図（、）〜（ｂ）は第２の実施例に係わる工
程断面図、第４図は第３の実施例に係わる工程断面図で
ある。
１１・・・ｎ型シリコン基板、１２・・・熱酸化膜（Ｓ
１０２膜）、１３・・・５１３Ｎ４膜、１４・・・レジ
スト、１５・・・グラズマＳｉＯ□膜、１６・・・溝部
、１７・・・ＣＶＤ ５ｉ０２膜（絶縁膜）、１ Ｂ
・・・ウェル、２０ａ。
２０ ｂ ・・・ダート酸化膜、２１ ａ 、 ２ ｌ
ｂ −ダート電極、２２ ａ 、 ２２ ｂ 、 ２
．９ ａ 、 ２３ ｂ−’ソース・ドレイン、３ Ｊ
’・・・π型基板、３２・・・酸化膜（ＳＩＯ２膜）、
３３・・・ｎウェル、４１・・・高濃度不純物層。
出願人代理人 弁理士 鈴 江 武 彦第２図
ＩＱ ＩＩ
第３図
第４図
３０５−Figures 1 (,) to (c) are cross-sectional views showing the conventional CMOS inverter manufacturing process, and Figures 2 (,) to (h) are
3(a) to (b) are process sectional views of the second embodiment, and FIG. 4 is a process sectional view of the third embodiment. It is. 11... N-type silicon substrate, 12... Thermal oxide film (S
102 film), 13...513N4 film, 14...Resist, 15...Grazma SiO□ film, 16...Groove portion, 17...CVD 5i02 film (insulating film), 1 B
...Well, 20a. 20 b...dirt oxide film, 21 a, 2 l
b - dart electrode, 22 a , 22 b , 2
．． 9 a, 23 b-' source/drain, 3 J
'...π-type substrate, 32... Oxide film (SIO2 film),
33...n well, 41...high concentration impurity layer. Applicant's agent Patent attorney Takehiko Suzue Figure 2 IQ II Figure 3 Figure 4 305-
Claims (5)
ェルを形成し、このウェル及び上記基板上にそれぞれ能
動素子を形成する半導体装置の製造方法において、前記
基板上のウェル形成領域外に１層以上の第１の被膜含形
成する工程と、上記被膜の周辺部の基板を選択エツチン
グして溝部を形成する工程と、上記溝部に絶縁膜を埋め
込む工程と、上記被膜及び絶縁膜をマスクとし前記基板
に該基板と逆導電型の不純物をドーピングする工程とを
具備したことを特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device, in which a well of a conductivity type opposite to that of the substrate is formed in a part of a semiconductor substrate, and active elements are formed respectively on this well and the substrate, the area outside the well formation area on the substrate is a step of forming a first coating of one or more layers on the substrate; a step of selectively etching the substrate in a peripheral area of the coating to form a groove; a step of embedding an insulating film in the groove; 1. A method of manufacturing a semiconductor device, comprising the step of doping the substrate with an impurity of a conductivity type opposite to that of the substrate, using the substrate as a mask.
程は、前記被膜が形成された基板上の全面に段差部にお
けるエツチング速度が平坦部におけるエツチング速度よ
り速い第２の被膜を形成したのち、全面エツチングを施
し上記第２の被膜の段差部を除去し、次いで残存した第
２の被膜をマスクの一部として前記基板を選択エツチン
グすることである特許請求の範囲第１項記載の半導体装
置の製造方法。(2) The step of forming grooves by selectively etching the substrate includes forming a second coating on the entire surface of the substrate on which the coating is formed, the etching rate of which is higher in the stepped portions than in the flat portions; The semiconductor device according to claim 1, wherein the entire surface is etched to remove the stepped portion of the second film, and then the remaining second film is used as a part of a mask to selectively etch the substrate. Production method.
導電型の第２ウエルを形成し、これらのウェル上にそれ
ぞれ能動素子を形成する半導体装置の製造方法において
、前記基板の第２ウエル形成領域上に１層以上の第１の
被膜を形成する工程と、上記第１の被膜の周辺部の基板
を選択エツチングして溝部を形成する工程と、上記溝部
に絶縁膜を埋め込む工程と、上記第１の被膜及び絶縁膜
をマスクとして第１ウエル形成領域上に第１導電型の不
純物をドーピングする工程と、上記第１ウエル形成領域
上に第３の被膜を形成する工程と、次いで前記第１の被
膜全除去する工程と、次いで上記第３の被膜をマスクと
して前記第２ウエル形成領域上に第２導電型の不純物を
ドーピングする工程とを具備したことを特徴する半導体
装置の製造方法。(3) A first well of the first conductivity type and a second well of the first conductivity type on the semiconductor substrate.
In a method of manufacturing a semiconductor device in which second wells of a conductive type are formed and active elements are formed on these wells, a step of forming one or more layers of a first film on a second well formation region of the substrate. a step of forming a groove by selectively etching the substrate in a peripheral area of the first coating; a step of embedding an insulating film in the groove; and a step of forming a first well forming region using the first coating and the insulating film as a mask. a step of doping an impurity of a first conductivity type on the top, a step of forming a third film on the first well formation region, a step of completely removing the first film, and then a step of removing the third film. A method of manufacturing a semiconductor device, comprising the step of doping an impurity of a second conductivity type onto the second well formation region using as a mask.
程は、前記第１の被膜が形成された基板上の全面に段差
部におけるエツチング速度が平坦部におけるエツチング
速度よシ速い第２の被膜を形成したのち、全面エツチン
グを施し上記第２の被膜の段差部を除去し、次いで残存
した第２の被膜をマスクの一部として前記基板を選択エ
ツチングすることである特許請求の範囲第３項記載の半
導体装置の製造方法。(4) The step of selectively etching the substrate to form grooves includes etching a second film on the entire surface of the substrate on which the first film is formed, the etching speed of which is faster in the step portions than in the flat portions. After forming the second film, the entire surface is etched to remove the stepped portion of the second film, and then the remaining second film is used as a part of a mask to selectively etch the substrate. A method for manufacturing a semiconductor device.
成されたものであシ、前記第１の被膜は耐酸化性膜を含
むものである特許請求の範囲第３項又は第４項記載の半
導体装置の製造方法。(5) The semiconductor according to claim 3 or 4, wherein the third coating is formed by selective oxidation of the substrate, and the first coating includes an oxidation-resistant film. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57150960A JPS5940563A (en) | 1982-08-31 | 1982-08-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57150960A JPS5940563A (en) | 1982-08-31 | 1982-08-31 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5940563A true JPS5940563A (en) | 1984-03-06 |
| JPH0481339B2 JPH0481339B2 (en) | 1992-12-22 |
Family
ID=15508191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57150960A Granted JPS5940563A (en) | 1982-08-31 | 1982-08-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5940563A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61500140A (en) * | 1983-10-11 | 1986-01-23 | アメリカン テレフオン アンド テレグラフ カムパニ− | Semiconductor circuits including complementary metal-oxide-semiconductor devices |
| JPS6252957A (en) * | 1985-09-02 | 1987-03-07 | Toshiba Corp | Cmos semiconductor device |
| US4656730A (en) * | 1984-11-23 | 1987-04-14 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method for fabricating CMOS devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55148466A (en) * | 1979-05-10 | 1980-11-19 | Nec Corp | Cmos semiconductor device and its manufacture |
| JPS55154748A (en) * | 1979-05-23 | 1980-12-02 | Toshiba Corp | Complementary mos semiconductor device |
| JPS55154770A (en) * | 1979-05-23 | 1980-12-02 | Toshiba Corp | Manufacture of complementary mos semiconductor device |
-
1982
- 1982-08-31 JP JP57150960A patent/JPS5940563A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55148466A (en) * | 1979-05-10 | 1980-11-19 | Nec Corp | Cmos semiconductor device and its manufacture |
| JPS55154748A (en) * | 1979-05-23 | 1980-12-02 | Toshiba Corp | Complementary mos semiconductor device |
| JPS55154770A (en) * | 1979-05-23 | 1980-12-02 | Toshiba Corp | Manufacture of complementary mos semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61500140A (en) * | 1983-10-11 | 1986-01-23 | アメリカン テレフオン アンド テレグラフ カムパニ− | Semiconductor circuits including complementary metal-oxide-semiconductor devices |
| US4656730A (en) * | 1984-11-23 | 1987-04-14 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method for fabricating CMOS devices |
| JPS6252957A (en) * | 1985-09-02 | 1987-03-07 | Toshiba Corp | Cmos semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0481339B2 (en) | 1992-12-22 |
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