JPS59956A - Semiconductor device with polysilicon fuse - Google Patents

Semiconductor device with polysilicon fuse

Info

Publication number
JPS59956A
JPS59956A JP57108437A JP10843782A JPS59956A JP S59956 A JPS59956 A JP S59956A JP 57108437 A JP57108437 A JP 57108437A JP 10843782 A JP10843782 A JP 10843782A JP S59956 A JPS59956 A JP S59956A
Authority
JP
Japan
Prior art keywords
film
polysilicon
oxide film
field oxide
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57108437A
Other languages
Japanese (ja)
Inventor
Katsuhiro Shimohigashi
下東　勝博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57108437A priority Critical patent/JPS59956A/en
Publication of JPS59956A publication Critical patent/JPS59956A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To strengthen a field oxidized film against contamination of an impurity and to enhance the reliability by forming a heat resistance insulating film between the field oxidized film and a polysilicon, thereby preventing the field oxidized film from damaging at the time of cutting the polysilicon. CONSTITUTION:A field oxidized film 2 is formed on a silicon substrate 1. A heat resistant insulating film (nitrided film) 4 is formed between the film 2 and a polysilicon 3. An electrode 9 is contacted with the polysilicon 3, and covered on an interlayer insulating film 7. The film 4 prevents the polysilicon 3 from cracking due to the heat of the film 2 at the time of cutting the polysilicon 3. An impurity which has infiltrated from a hole 8 is gettered to the film 4 on the film 2.

Description

【発明の詳細な説明】 本発明は、ポリシリコンヒユーズを用いた半導体装置の
改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor devices using polysilicon fuses.

ポリシリコンを電気的に切断する言わゆるヒ、ユーズＲ
ＯＭとして使用する場合、従来は第１図に示すようにフ
ィールド酸化膜２上に直接ポリシリコンを被着していた
。ポリシリコンに過大電流を流すとジュール熱でヒユー
ズ部８が融点（〜１４２゜Ｃ）に達し溶けて切断する。The so-called "Use R" that electrically cuts polysilicon
When used as an OM, conventionally polysilicon was deposited directly on the field oxide film 2 as shown in FIG. When an excessive current is applied to polysilicon, the fuse portion 8 reaches its melting point (~142° C.) due to Joule heat, melts, and breaks.

このように−瞬（＜　１５ｅｃ）ではめるが、ヒユーズ
部８のポリシリコン３直下のフィールド酸化膜２は高熱
にさらされるわけで、クジツクなどの損傷を受は信頼性
上の問題を生じる恐れがある。将来フィールド酸化膜２
を薄くしようとする場合、ますます大きな問題となる可
能性がある。Although it is installed in an instant (<15 ec), the field oxide film 2 directly under the polysilicon 3 in the fuse section 8 is exposed to high heat, and if it is damaged by scratches or the like, it may cause reliability problems. be. Future field oxide film 2
If you try to make it thinner, this may become an even bigger problem.

本発明の目的は、上記フィールド酸化膜の熱的損傷をな
くシ、信頼性の高いポリシリコンヒユーズを用いた半導
体装置を提供するととＫある。An object of the present invention is to provide a semiconductor device using a highly reliable polysilicon fuse that eliminates thermal damage to the field oxide film.

本発明によれば、とシわけ半導体メモリの欠陥救済に効
果がアシ、特にプログラマブルＲＯＭとして用いるポリ
シリコンヒユーズＲＯＭの信頼性を著しく高めるもので
ある。The present invention is particularly effective in relieving defects in semiconductor memories, and in particular, significantly increases the reliability of polysilicon fuse ROMs used as programmable ROMs.

上記、本発明の目的を達成するために、本発明、におい
ては、ポリシリコン３とフィールド酸化膜２との間に熱
的により強固な絶縁材料を介在させたところに特徴があ
る。この材料としては、チップのパッシベーションなど
に用いられるナイトライド膜（８７，Ｎ、）、タンタル
酸化膜が利用できる。とシわけこのナイトライド膜は、
はとんどの半導体プロセスで使われているものでプロセ
ス的的にも容易に使うことができる利点がある。In order to achieve the above object of the present invention, the present invention is characterized in that a thermally stronger insulating material is interposed between the polysilicon 3 and the field oxide film 2. As this material, a nitride film (87,N,) and a tantalum oxide film, which are used for chip passivation, etc., can be used. This nitride film is
It is used in most semiconductor processes and has the advantage of being easy to use from a process standpoint.

以下、実施例によシ、本発明を具体的に説明する。Hereinafter, the present invention will be specifically explained with reference to Examples.

第２図に本発明の一つの実施例を示す。また第３図にそ
の製造方法を示す。第２図に示すようにポリシリコン３
の下にナイト２イド膜４を敷き、ポリシリコン３とフィ
ールド酸化膜２が直接接触しない構造となっておシ、ナ
イトライド膜はフィールド酸化膜２の熱によるクランク
を防止する。FIG. 2 shows one embodiment of the present invention. Further, FIG. 3 shows its manufacturing method. As shown in Figure 2, polysilicon 3
A nitride film 4 is placed under the polysilicon 3 to prevent direct contact between the polysilicon 3 and the field oxide film 2, and the nitride film prevents the field oxide film 2 from cranking due to heat.

なお、第２図では、ポリシリコン３の下だけ選択的にナ
イトライド膜４を残しているが、フィールド酸化膜上全
体にナイトライド膜４を残したままでもよい。ナイトラ
イド膜の他の効用は、重膜がチップのパッシベーション
として用いられることかられかるように機械的、熱的に
強いことの他に不純物の汚染のストッパーとなることで
ある。In FIG. 2, the nitride film 4 is left selectively only under the polysilicon 3, but the nitride film 4 may be left on the entire field oxide film. Other benefits of the nitride film are that it is mechanically and thermally strong, as is known from the fact that the heavy film is used as passivation for chips, and that it also serves as a stopper for impurity contamination.

第２図から明らかなように開口部８よシ侵入した不純物
はフィールド酸化膜２上のナイトライド膜４にゲッタリ
ングされることになシ、本構造はこの点からも信頼性の
高い構造となっている。As is clear from FIG. 2, impurities entering through the opening 8 are gettered to the nitride film 4 on the field oxide film 2, and this structure is highly reliable from this point of view as well. It has become.

以下第３図を参照して製造方法を詳述する。The manufacturing method will be described in detail below with reference to FIG.

（ａ）Ｓｉ基板１上にフィールド酸化膜２を形成し、ナ
イトライド膜４およびポリシリコン３を被着する。(a) A field oxide film 2 is formed on a Si substrate 1, and a nitride film 4 and polysilicon 3 are deposited thereon.

Φ）　ポリシリコンをパターニングしたあと、ポリシリ
コンをマスクにナイトライドを切る。その後ポリシリコ
ン３を酸化し、比較的厚い酸化膜５を形成する。その後
ポリシリコン３に電極（Ａｔ）９を接着する部分６の酸
化膜５を除去する。Φ) After patterning the polysilicon, cut the nitride using the polysilicon as a mask. Thereafter, polysilicon 3 is oxidized to form a relatively thick oxide film 5. Thereafter, the oxide film 5 on the portion 6 where the electrode (At) 9 is bonded to the polysilicon 3 is removed.

（ｃ）ＰＳＧ、（層間絶縁膜）７を被着し、電極９との
接触部６と開口部８のＰＳＧを除去する。(c) PSG (interlayer insulating film) 7 is deposited, and the PSG in the contact portion 6 with the electrode 9 and the opening 8 is removed.

（ｄ）　　電極９を被着しパターニングする。(d) Deposit and pattern the electrode 9.

（ｅ）　　ｓ　ｉ　ｏｓ等のファイナルパッシベーショ
ン膜１０を被着する。(e) A final passivation film 10 such as sios is deposited.

後ハ、開口部８のファイナルパッシベーション膜を除去
すれば第２図の構造となる。前述のように工程（ｂ）で
ポリシリコン３をマスクにしてナイトライド膜４を除去
したが、他のマスクを用いてフィールド酸化膜２上全体
にナイトライド膜４を残してもよい。Afterwards, if the final passivation film in the opening 8 is removed, the structure shown in FIG. 2 will be obtained. As described above, in step (b), the nitride film 4 was removed using the polysilicon 3 as a mask, but the nitride film 4 may be left on the entire field oxide film 2 using another mask.

以上説明したように本発明によれば、ポリシリコン切断
時のフィールド酸化膜の損傷が防止できかつ汚染に強く
信頼性の高いポリシリコンヒユーズＲＯＭが実現できる
。As described above, according to the present invention, it is possible to realize a polysilicon fuse ROM that can prevent damage to the field oxide film during cutting of polysilicon, is resistant to contamination, and is highly reliable.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来のポリシルコンヒユーズＲＯＭの断面図
、第２図は、本発明による一実施例の断面図、第３図は
第２図の製作方法を示す図である。FIG. 1 is a cross-sectional view of a conventional polysilicone fuse ROM, FIG. 2 is a cross-sectional view of an embodiment of the present invention, and FIG. 3 is a diagram showing the manufacturing method of FIG. 2.

Claims (1)

【特許請求の範囲】 １、　フィールド酸化膜とポリシリコンとの間に耐熱性
絶縁膜を設けたことを特徴とするポリシリコンヒユーズ
を有する半導体装置。 ２　上記耐熱性絶縁膜として、シリコンナイトライド膜
を用いたことを特徴とする特許請求の範囲第１項記載の
半導体装置。[Claims] 1. A semiconductor device having a polysilicon fuse, characterized in that a heat-resistant insulating film is provided between a field oxide film and polysilicon. 2. The semiconductor device according to claim 1, wherein a silicon nitride film is used as the heat-resistant insulating film.
JP57108437A 1982-06-25 1982-06-25 Semiconductor device with polysilicon fuse Pending JPS59956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57108437A JPS59956A (en) 1982-06-25 1982-06-25 Semiconductor device with polysilicon fuse

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57108437A JPS59956A (en) 1982-06-25 1982-06-25 Semiconductor device with polysilicon fuse

Publications (1)

Publication Number Publication Date
JPS59956A true JPS59956A (en) 1984-01-06

Family

ID=14484744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57108437A Pending JPS59956A (en) 1982-06-25 1982-06-25 Semiconductor device with polysilicon fuse

Country Status (1)

Country Link
JP (1) JPS59956A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6350498U (en) * 1986-09-19 1988-04-05
JPH0563091A (en) * 1991-09-04 1993-03-12 Fujitsu Ltd Semiconductor device
EP2551901A1 (en) * 2011-07-29 2013-01-30 Infineon Technologies AG Semiconductor device and method for manufacturing a semiconductor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5762544A (en) * 1980-10-03 1982-04-15 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5762544A (en) * 1980-10-03 1982-04-15 Fujitsu Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6350498U (en) * 1986-09-19 1988-04-05
JPH0563091A (en) * 1991-09-04 1993-03-12 Fujitsu Ltd Semiconductor device
EP2551901A1 (en) * 2011-07-29 2013-01-30 Infineon Technologies AG Semiconductor device and method for manufacturing a semiconductor
US8659118B2 (en) 2011-07-29 2014-02-25 Infineon Technologies Ag Semiconductor device comprising a fuse structure and a method for manufacturing such semiconductor device
US9165828B2 (en) 2011-07-29 2015-10-20 Infineon Technologies Ag Semiconductor device comprising a fuse structure and a method for manufacturing such semiconductor device

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