JPH0529376A - Bonding pad of semiconductor device - Google Patents

Bonding pad of semiconductor device

Info

Publication number
JPH0529376A
JPH0529376A JP18284291A JP18284291A JPH0529376A JP H0529376 A JPH0529376 A JP H0529376A JP 18284291 A JP18284291 A JP 18284291A JP 18284291 A JP18284291 A JP 18284291A JP H0529376 A JPH0529376 A JP H0529376A
Authority
JP
Japan
Prior art keywords
bonding pad
interlayer dielectric
dielectric film
aluminum
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18284291A
Other languages
Japanese (ja)
Inventor
Nobuaki Yamamori
信彰 山盛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18284291A priority Critical patent/JPH0529376A/en
Publication of JPH0529376A publication Critical patent/JPH0529376A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To manufacture a highly reliable semiconductor device using an interlayer dielectric film, which is made of an organic material having insufficient impact resistance, by covering the edge of the interlayer dielectric film surrounding the outer periphery of a bonding pad with a metal film, which is composed of the same material as the bonding pad, without a contact between the bonding pad and the metal film. CONSTITUTION:A bonding pad 5, made of aluminum, is kept apart from an interlayer dielectric film 3, made of polyimide siloxane, at a distance of more than 10mum. The edge of the interlayer dielectric film 3 is also covered with aluminum 6. As a result of this, there is eliminated a possibility of cracks occurring in the interlayer dielectric film. In addition, it is possible to prevent the exfoliation of the interlayer dielectric film, in the following processes, due to the aluminum remaining on the side surface of the edge of the interlayer dielectric film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置のボンディン
グパッドに関し、特に有機系薄膜を層間絶縁膜とする半
導体装置のボンディングパッドに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding pad for a semiconductor device, and more particularly to a bonding pad for a semiconductor device using an organic thin film as an interlayer insulating film.

【０００２】[0002]

【従来の技術】従来技術によるボンディングパッドにつ
いて、図３（ａ）〜（ｃ）を参照して説明する。2. Description of the Related Art A conventional bonding pad will be described with reference to FIGS.

【０００３】図３（ａ）は最も一般的なボンディングパ
ッドである。アルミニウムからなるボンディングパッド
５の下には、ポリイミドシロキサンからなる層間絶縁膜
３が形成されている。この構造ではボンディング工程で
の衝撃が直に層間絶縁膜３に伝わって、耐衝撃力の不充
分な有機系の層間絶縁膜３にクラックが発生して、ボン
ディグパッド３が剥れるなどの不良が発生する。FIG. 3A shows the most general bonding pad. An interlayer insulating film 3 made of polyimide siloxane is formed under the bonding pad 5 made of aluminum. In this structure, the impact in the bonding process is directly transmitted to the interlayer insulating film 3, and a crack is generated in the organic interlayer insulating film 3 having insufficient impact resistance, so that the bonding pad 3 is peeled off. Occurs.

【０００４】この問題を改良するため、図３（ｂ）に示
すようにボンディグパッド５の下の層間絶縁膜３を除去
した構造がある。ボンディングパッド５の下は酸化膜２
なのでクラックは発生しないが、ボンディングパッド５
の周囲が層間絶縁膜３の縁に乗り上げているので、ボン
ディングがセンターずれると、側面のポリイミドシロキ
サンに衝撃が加わってクラックが発生する。In order to improve this problem, there is a structure in which the interlayer insulating film 3 under the bonding pad 5 is removed as shown in FIG. 3 (b). The oxide film 2 is under the bonding pad 5.
So no cracks occur, but the bonding pad 5
Since the periphery of the substrate runs on the edge of the interlayer insulating film 3, if the bonding is decentered, the polyimide siloxane on the side surface is impacted and cracks occur.

【０００５】さらに改良されたのが、図３（ｃ）に示す
ように、層間絶縁膜３を大きく除去してボンディングパ
ッド５と接触しない構造である。この場合、層間絶縁膜
３にクラックは発生しないが、ボンディングパッド５の
アルミニウムをフォトリソグラフィにより選択エッチン
グするとき、層間絶縁膜３の端部の側面にアルミニウム
残り６ａが発生する。このアルミニウム残り６６ａが、
表面保護膜となるポリイミド４を形成するとき層間絶縁
膜３端部の側面から剥離してボンディングパッド間のシ
ョート不良が発生する。A further improvement is a structure in which the interlayer insulating film 3 is largely removed so as not to come into contact with the bonding pad 5, as shown in FIG. 3 (c). In this case, cracks do not occur in the interlayer insulating film 3, but when aluminum of the bonding pad 5 is selectively etched by photolithography, an aluminum residue 6a is generated on the side surface of the end portion of the interlayer insulating film 3. The remaining aluminum 66a is
When the polyimide 4 serving as the surface protective film is formed, the interlayer insulating film 3 is peeled off from the side surface of the end portion thereof to cause a short circuit between bonding pads.

【０００６】[0006]

【発明が解決しようとする課題】従来技術による製造方
法では、層間絶縁膜のクラックまたはアルミニウム残り
が発生するので、耐衝撃力の不充分な有機系材料からな
る層間絶縁膜を用いて高信頼度の半導体装置を製造する
ことができなかった。In the manufacturing method according to the prior art, since cracks or residual aluminum are generated in the interlayer insulating film, an interlayer insulating film made of an organic material having insufficient impact resistance is used to achieve high reliability. Could not be manufactured.

【０００７】[0007]

【課題を解決するための手段】本発明の半導体装置のボ
ンディングパッドの外周を囲む層間絶縁膜の端部は、前
記ボンディングパッドと接することなく、前記ボンディ
ングパッドと同一材質の金属膜によって覆われている。An end portion of an interlayer insulating film surrounding an outer periphery of a bonding pad of a semiconductor device of the present invention is covered with a metal film made of the same material as the bonding pad without being in contact with the bonding pad. There is.

【０００８】[0008]

【実施例】本発明の第１の実施例について、図１（ａ）
の平面図およびその断面図である図１（ｂ）を参照して
説明する。EXAMPLE FIG. 1A shows a first example of the present invention.
Will be described with reference to a plan view and a sectional view of FIG.

【０００９】本実施例ではアルミニウムからなるボンデ
ィングパッド５とポリイミドシロキサンからなる層間絶
縁膜３とは１０μｍ以上離すことにより、ボンディング
がセンターずれしてもクラックが発生することはなくな
った。また層間絶縁膜３の端部はアルミニウムで覆われ
ているので、側面に余分なアルミニウム残りが発生する
ことはない。In this embodiment, the bonding pad 5 made of aluminum and the interlayer insulating film 3 made of polyimide siloxane are separated by 10 μm or more, so that even if the bonding is displaced from the center, no crack is generated. Further, since the end portion of the interlayer insulating film 3 is covered with aluminum, no excess aluminum remains on the side surface.

【００１０】つぎに本発明の第２の実施例について、図
２（ａ）の平面図およびその断面図である図２（ｂ）を
参照して説明する。Next, a second embodiment of the present invention will be described with reference to the plan view of FIG. 2A and its sectional view, FIG.

【００１１】アルミニウムからなるボンディングパッド
５の下にさらにアルミニウム７が形成された２層構造
に、本発明を適用したものである。The present invention is applied to a two-layer structure in which aluminum 7 is further formed under the bonding pad 5 made of aluminum.

【００１２】層間絶縁膜３端部を覆うアルミニウム６が
ボンディングパッド５の下のアルミニウム７に接続され
ている。そのため第１の実施例よりもさらに、層間絶縁
膜３端部のアルミニウム６が剥れにくいという利点があ
る。Aluminum 6 covering the end of interlayer insulating film 3 is connected to aluminum 7 under bonding pad 5. Therefore, there is an advantage that the aluminum 6 at the end portion of the interlayer insulating film 3 is less likely to peel off than in the first embodiment.

【００１３】本実施例では下層のアルミニウム７とポリ
イミドシロキサンからなる層間絶縁膜３との重なりを３
μｍとし、上層のボンディングパッド５とポリイミドシ
ロキサンからなる層間絶縁膜３とを１０μｍ離して良好
な結果が得られた。In this embodiment, the lower layer aluminum 7 and the interlayer insulating film 3 made of polyimide siloxane are overlapped by 3 times.
A good result was obtained by separating the upper bonding pad 5 and the interlayer insulating film 3 made of polyimide siloxane by 10 μm.

【００１４】[0014]

【発明の効果】層間絶縁膜からボンディングパッドを離
したうえ、層間絶縁膜端部をボンディングパッドと同一
材料で覆った。その結果層間絶縁膜にクラックが発生す
ることはなくなった。また層間絶縁膜端部の側面にアル
ミニウムが残って、後工程で剥れるという問題も解消す
ることができた。The bonding pad is separated from the interlayer insulating film, and the edge portion of the interlayer insulating film is covered with the same material as the bonding pad. As a result, no crack was generated in the interlayer insulating film. Further, it was possible to solve the problem that aluminum remained on the side surface of the end portion of the interlayer insulating film and was peeled off in a later step.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）は本発明の第１の実施例を示す平面図で
ある。 （ｂ）は（ａ）の断面図である。FIG. 1A is a plan view showing a first embodiment of the present invention. (B) is sectional drawing of (a).

【図２】（ａ）は本発明の第２の実施例を示す平面図で
ある。 （ｂ）は（ａ）の断面図である。FIG. 2A is a plan view showing a second embodiment of the present invention. (B) is sectional drawing of (a).

【図３】従来技術によるボンディングパッドを示す断面
図である。FIG. 3 is a cross-sectional view showing a conventional bonding pad.

【符号の説明】[Explanation of symbols]

１ シリコン基板 ２ 熱酸化膜 ３ 層間絶縁膜 ４ ポリイミド ５ ボンディングパッド ６ アルミニウム ６ａ アルミニウム残り ７ アルミニウム 1 Silicon Substrate 2 Thermal Oxide Film 3 Interlayer Insulating Film 4 Polyimide 5 Bonding Pad 6 Aluminum 6a Aluminum Remaining 7 Aluminum

Claims (1)

【特許請求の範囲】 【請求項１】 ボンディングパッドの外周を囲む層間絶
縁膜の端部が、前記ボンディングパッドと接することな
く、前記ボンディングパッドと同一材質の金属膜によっ
て覆われている半導体装置のボンディングパッド。Claim: What is claimed is: 1. A semiconductor device in which an end portion of an interlayer insulating film surrounding an outer periphery of a bonding pad is covered with a metal film made of the same material as the bonding pad without contacting with the bonding pad. Bonding pad.
JP18284291A 1991-07-24 1991-07-24 Bonding pad of semiconductor device Pending JPH0529376A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18284291A JPH0529376A (en) 1991-07-24 1991-07-24 Bonding pad of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18284291A JPH0529376A (en) 1991-07-24 1991-07-24 Bonding pad of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0529376A true JPH0529376A (en) 1993-02-05

Family

ID=16125414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18284291A Pending JPH0529376A (en) 1991-07-24 1991-07-24 Bonding pad of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0529376A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829182A (en) * 1994-11-14 1998-11-03 Okamoto; Toshihisa Intra-line fishing rod
KR100413760B1 (en) * 2001-04-05 2003-12-31 삼성전자주식회사 Bonding pad structures for semiconductor devices
JP2006303238A (en) * 2005-04-21 2006-11-02 Sharp Corp Semiconductor chip, manufacturing method thereof and semiconductor device
CN100382253C (en) * 2003-05-09 2008-04-16 友达光电股份有限公司 Welding pad structure and producing method thereof
US8492763B2 (en) 2010-09-22 2013-07-23 Kabushiki Kaisha Toshiba Semiconductor device including an edge seal and plural pad pieces

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731844B2 (en) * 1974-10-26 1982-07-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731844B2 (en) * 1974-10-26 1982-07-07

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829182A (en) * 1994-11-14 1998-11-03 Okamoto; Toshihisa Intra-line fishing rod
KR100413760B1 (en) * 2001-04-05 2003-12-31 삼성전자주식회사 Bonding pad structures for semiconductor devices
CN100382253C (en) * 2003-05-09 2008-04-16 友达光电股份有限公司 Welding pad structure and producing method thereof
JP2006303238A (en) * 2005-04-21 2006-11-02 Sharp Corp Semiconductor chip, manufacturing method thereof and semiconductor device
US8492763B2 (en) 2010-09-22 2013-07-23 Kabushiki Kaisha Toshiba Semiconductor device including an edge seal and plural pad pieces

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