JPH0520902B2 - - Google Patents
Info
- Publication number
- JPH0520902B2 JPH0520902B2 JP59068416A JP6841684A JPH0520902B2 JP H0520902 B2 JPH0520902 B2 JP H0520902B2 JP 59068416 A JP59068416 A JP 59068416A JP 6841684 A JP6841684 A JP 6841684A JP H0520902 B2 JPH0520902 B2 JP H0520902B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- fuse
- fuse medium
- medium
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 34
- 230000001681 protective effect Effects 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 13
- 230000002950 deficient Effects 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims 2
- 238000001514 detection method Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 27
- 229920005591 polysilicon Polymers 0.000 description 27
- 239000011521 glass Substances 0.000 description 8
- 238000007664 blowing Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910019655 synthetic inorganic crystalline material Inorganic materials 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- JNDMLEXHDPKVFC-UHFFFAOYSA-N aluminum;oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Y+3] JNDMLEXHDPKVFC-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000013102 re-test Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910019901 yttrium aluminum garnet Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は大規模集積回路装置（VLSI）の製
造方法に関し、特に、同一チツプ内に冗長回路を
作成し、VLSIの製造段階において不良回路部が
発生した場合、その部分を上記冗長回路で電気的
に接ぎ換える方法の改良に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing large-scale integrated circuit devices (VLSI), and in particular, a method for creating redundant circuits within the same chip and eliminating defective circuit sections during the VLSI manufacturing stage. The present invention relates to an improvement in a method of electrically connecting the affected portion with the above-mentioned redundant circuit when this occurs.
従来より、VLSIの製造において、不良回路部
が発生した場合に冗長回路で置き換える方式は、
VLSIの製造歩留りの大幅な向上が期待できるも
ので、この方式は256キロビツト以上のダイナミ
ツクRAM（Random Access Memory）に主と
して採用されている。
Conventionally, in VLSI manufacturing, when a defective circuit section occurs, the method of replacing it with a redundant circuit is as follows.
This method is expected to significantly improve VLSI manufacturing yields, and is mainly used for dynamic RAM (Random Access Memory) of 256 kilobits or more.
第１図Ａ〜Ｃは従来方法の工程別断面図であ
り、先ず、第１図Ａに示すように、半導体基板１
の非活性領域上に酸化膜２を介して、切換ヒユー
ズの役割をする媒体、例えばポリシリコン線３を
形成し、その上に表面平坦化、接合特性の安定化
のためのリンガラス（PSG）またはボロンリン
ガラス（BPSG）からなる保護膜４を形成する。
これに対して第１図Ｂに示すようにネオジム：イ
ツトリウム・アルミニウム・ガーネツト（Nb：
YAG）レーザ、アルゴン（Ar）イオンレーザな
どによつて、保護膜４に開孔５を形成し、その部
分においてポリシリコン線３を溶断する。次に、
第１図に示すような、プラズマ窒化膜のようなパ
ツシベーシヨン膜６によつて上部を覆つて表面を
保護し、不純物や水分の侵入を防止する。 FIGS. 1A to 1C are cross-sectional views of each step of the conventional method. First, as shown in FIG. 1A, a semiconductor substrate 1 is
A medium, for example, a polysilicon line 3, which acts as a switching fuse is formed on the non-active region of the oxide film 2 through an oxide film 2, and phosphor glass (PSG) is formed on it to flatten the surface and stabilize the bonding characteristics. Alternatively, a protective film 4 made of borophosphorus glass (BPSG) is formed.
On the other hand, as shown in Figure 1B, neodymium: yttrium aluminum garnet (Nb:
An opening 5 is formed in the protective film 4 using a YAG (YAG) laser, an argon (Ar) ion laser, or the like, and the polysilicon line 3 is fused at that portion. next,
As shown in FIG. 1, the upper part is covered with a passivation film 6 such as a plasma nitride film to protect the surface and prevent impurities and moisture from entering.
上記の工程では、レーザ光Ｉによつて保護膜４
も同時に除去したが、保護膜４はクラツク等のダ
メージを与えるに止め、ポリシリコン線３を部分
的に除去する場合もある。これはレーザ光Ｉのパ
ロー、波長、保護膜４の厚さに依存する。 In the above process, the protective film 4 is
Although the polysilicon line 3 is also removed at the same time, the protective film 4 only causes damage such as cracks, and the polysilicon line 3 may be partially removed. This depends on the intensity and wavelength of the laser beam I and the thickness of the protective film 4.
第３図は上記第１図に示した従来のポリシリコ
ン線の溶断工程を用いた場合のVSLI製工程を示
すフロー図で、「ウエハ工程」において、第１
図Ａの形態とし、その後に「回路テスト工程」
によつて不良部を検出し、「レーザ溶断」によつ
てヒユーズの役割をするポリシリコン３を溶断し
て接ぎ換える工程が入る。 Figure 3 is a flow diagram showing the VSLI manufacturing process using the conventional polysilicon line fusing process shown in Figure 1 above.
The form is as shown in Figure A, and then the "circuit test process"
A process is then started in which a defective part is detected by ``laser blowing'' and the polysilicon 3, which functions as a fuse, is fused and replaced.
ところで、第２図は、保護膜４にPSG膜を用
いた場合の、PSG膜４の膜厚とそのレーザ光反
射係数との関係を示す図で、PSG膜４下のポリ
シリコン線３の光吸収はPSG膜４の膜厚によつ
て大きく変化する。このため、上記従来の工程で
は、PSG膜４の膜厚の変化によつてポリシリコ
ン線３の溶断が再現性良く行うことができないと
いう問題点があつた。 By the way, FIG. 2 is a diagram showing the relationship between the film thickness of the PSG film 4 and its laser beam reflection coefficient when a PSG film is used as the protective film 4. Absorption varies greatly depending on the thickness of the PSG film 4. Therefore, in the conventional process described above, there was a problem in that the polysilicon line 3 could not be blown out with good reproducibility due to changes in the thickness of the PSG film 4.
一方、上記工程とは異なり、PSG膜からなる
保護膜４を堆積する前に、ポリシリコン線３をレ
ーザで溶断する方法も一部で行なれているが、こ
の方法では、ポリシリコンの溶断の再現性は向上
するものの、溶断時にポリシリコンの飛散が生
じ、この飛散したポリシリコンによつて不要部分
に短絡が生じたり、飛散ポリシリコンの付着部分
に盛り上がり段差を生じ、その後の工程、即ち、
PSG膜からなる保護膜４の形成等に悪影響を与
えるという問題点があつた。 On the other hand, unlike the above process, some methods involve cutting the polysilicon line 3 with a laser before depositing the protective film 4 made of a PSG film. Although the reproducibility is improved, polysilicon scatters during fusing, and this scattered polysilicon causes short circuits in unnecessary parts, and bumps and steps are created in the areas where the scattered polysilicon is attached, resulting in problems in subsequent processes, i.e.
There was a problem in that it adversely affected the formation of the protective film 4 made of the PSG film.
また、前述した第１図Ａに示す状態、即ち、半
導体基板１の非活性領域上に酸化膜２を介して、
ポリシリコン線３を形成し、その上に表面平坦
化、接合特性の安定化のためのリンガラス
（PSG）またはボロンリンガラス（BPSG）から
なる保護膜４を形成した後、後述する図４Ｂに示
すように、リンガラス（PSG）またはボロンリ
ンガラス（BPSG）からなる保護膜４の一部除去
した後、ポリシリコン線３をレーザで溶断する方
法も提案されているが、この場合も、上記の方法
と同様に、ポリシリコンの溶断の再現性は向上す
るものの、リンガラス（PSG）またはボロンリ
ンガラス（BPSG）からなる保護膜４とポリシリ
コン線３との界面や保護膜４上に溶断時に飛散し
たポリシリコンが付着し、やはり不要部分に短絡
を生じ、装置特性が安定しないという問題点があ
つた。 In addition, in the state shown in FIG.
After forming a polysilicon line 3 and forming a protective film 4 made of phosphorus glass (PSG) or boron phosphorus glass (BPSG) on it for surface flattening and stabilization of bonding characteristics, the process is shown in FIG. 4B, which will be described later. As shown, a method has also been proposed in which the polysilicon line 3 is fused with a laser after removing a portion of the protective film 4 made of phosphorus glass (PSG) or boron phosphorus glass (BPSG). Similar to the method described above, although the reproducibility of polysilicon melting is improved, melting may occur at the interface between the polysilicon wire 3 and the protective film 4 made of phosphorus glass (PSG) or boron phosphorus glass (BPSG) or on the protective film 4. At times, the scattered polysilicon adhered to the device, causing short circuits in unnecessary parts, resulting in unstable device characteristics.
上記のように、従来の半導体集積回路装置の製
造において、不良回路部が発生した場合に、ヒユ
ーズ媒体の所要部分をレーザー光で溶断し、冗長
回路で置き換える方式では、溶断が再現性良く行
え、かつ、溶断後の装置内に不要な短絡等のない
信頼性の高い半導体装置を得ることができないと
いう問題点があつた。
As mentioned above, in the conventional manufacturing of semiconductor integrated circuit devices, when a defective circuit section occurs, the required portion of the fuse medium is fused with a laser beam and replaced with a redundant circuit, which allows the fusing to be performed with good reproducibility. Another problem is that it is impossible to obtain a highly reliable semiconductor device that is free from unnecessary short circuits within the device after blowing out.
この発明は、上記点に鑑みてなされたものであ
り、ヒユーズ媒体が再現性良く溶断でき、しか
も、溶断時の装置特性を安定化した信頼性の高い
半導体集積回路装置が得られる半導体集積回路装
置の製造方法を提供することを目的とする。 The present invention has been made in view of the above points, and provides a semiconductor integrated circuit device in which a highly reliable semiconductor integrated circuit device in which a fuse medium can be blown out with good reproducibility and the device characteristics at the time of blown out are stabilized is obtained. The purpose is to provide a manufacturing method for.
この発明にかかる半導体集積回路装置の製造方
法は、ヒユーズ媒体の所要部分を溶断するに際
し、溶断部以外のヒユーズ媒体及びPSG膜等か
らなる保護膜の全面をプラズマ窒化膜からなるパ
ツシベーシヨン膜にて覆い、この状態で上記所要
部分にレーザ光を照射するようにしたものであ
る。
In the method for manufacturing a semiconductor integrated circuit device according to the present invention, when blowing out a required portion of a fuse medium, the entire surface of the fuse medium other than the blown portion and a protective film made of a PSG film or the like is covered with a passivation film made of a plasma nitride film. In this state, the required portions are irradiated with laser light.
この発明にかかる半導体集積回路装置の製造方
法では、レーザ光にてヒユーズ媒体を溶断する際
に周囲に飛散するヒユーズ媒体がヒユーズ媒体及
びPSG膜等からなる保護膜を覆うプラズマ窒化
膜からなるパツシベーシヨン膜上に付着するた
め、飛散したポリシリコンが装置内部には全く侵
入せず、また、ヒユーズ媒体に直接レーザ光が照
射されるため、溶断の再現性も良好となる。
In the method for manufacturing a semiconductor integrated circuit device according to the present invention, when the fuse medium is fused with a laser beam, the fuse medium scattered around is a passivation film made of a plasma nitride film that covers the fuse medium and a protective film made of a PSG film, etc. Since the polysilicon adheres to the top, the scattered polysilicon does not enter the inside of the device at all, and since the fuse medium is directly irradiated with laser light, the reproducibility of fusing is also good.
以下、この発明の一実施例を図について説明す
る。
An embodiment of the present invention will be described below with reference to the drawings.
第４図Ａ〜Ｅは、この発明の一実施例を示す半
導体集積回路装置のヒユーズ媒体の溶断工程を示
す工程別断面図であり、第５図はこの工程からア
ツセンブリ工程に到る製造フローを示す図であ
る。 4A to 4E are cross-sectional views showing each step of the fuse medium blowing process of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 5 shows the manufacturing flow from this step to the assembly step. FIG.
先ず、まず第４図Ａに示すように第１図Ａと同
様に、半導体基板１の非活性領域上に酸化膜２、
ヒユーズ媒体としてポリシリコン線３及び保護膜
としてのSPG膜４を順次形成する。次いで、
PSG膜４は通常回路部ではコンタクトと呼ばれ、
パターニングとエツチングとが行われるため、本
実施例ではこの工程を利用して第４図Ｂに示すよ
うにPSG膜４のみに開孔７を形成する。次に、
第４図Ｃに示すように開孔７の内部を含めプラズ
マ窒化膜からなるパツシベーシヨン膜６を堆積
し、続いて第４図Ｄに示すように上述の開孔７内
のパツシベーシヨン膜６に開孔７より径の小さい
開孔８を形成し、その底部にポリシリコン線３を
露出させる。以上の工程は通常の半導体装置の製
造における金属配線後のワイヤボンデイングのパ
ツド部の取出し開孔の形成工程と一致し、第５図
のフロー図での「ウエハ工程」に相当する。これ
ではウエハはほぼその加工工程を終え、「テスト
工程」にまわされる。このテストで回路機能が調
べられ、不良部に対しては「レーザ溶断」の工程
で、ヒユーズ媒体であるポリシリコン線３の溶断
を行い、冗長回路との置換を行う。この実施例で
は第４図Ｅに示すように、レーザ光Ｉを開孔８か
らポリシリコン線３に照射して溶断部９を形成し
て、この工程段階は完了する。以下、第５図に示
すように「溶断部チツプ再テスト」を経て「アセ
ンブリ工程」に移される。 First, as shown in FIG. 4A, similar to FIG. 1A, an oxide film 2,
A polysilicon line 3 as a fuse medium and an SPG film 4 as a protective film are sequentially formed. Then,
The PSG film 4 is usually called a contact in the circuit section,
Since patterning and etching are performed, in this embodiment, this process is utilized to form openings 7 only in the PSG film 4, as shown in FIG. 4B. next,
As shown in FIG. 4C, a passivation film 6 made of a plasma nitride film is deposited on the inside of the opening 7, and then, as shown in FIG. 4D, a hole is opened in the passivation film 6 inside the opening 7. An opening 8 having a smaller diameter than 7 is formed, and the polysilicon line 3 is exposed at the bottom thereof. The above process corresponds to the process of forming an opening for taking out the pad portion of the wire bonding after metal wiring in the manufacturing of a normal semiconductor device, and corresponds to the "wafer process" in the flowchart of FIG. In this case, the wafer has almost completed its processing process and is sent to the "test process." This test examines the circuit function, and for defective parts, the polysilicon wire 3, which is the fuse medium, is blown out in a "laser blowing" process and replaced with a redundant circuit. In this embodiment, as shown in FIG. 4E, the polysilicon line 3 is irradiated with laser light I through the opening 8 to form a fusing portion 9, and this process step is completed. Thereafter, as shown in FIG. 5, the process proceeds to the "assembly process" after a "retest of the chip at the fused part".
このような本実施例の半導体集積回路装置の製
造方法では、ポリシリコン線３の溶断のためのレ
ーザ光の照射はポリシリコン線３に直接行われ
るので、従来方法におけるようにPSG膜の膜厚
の影響を受けることなく、溶断は再現性よく確実
に行うことができ、更に、レーザ光の照射をす
べきポリシリコン線３の部分を除いて全上面がパ
ツシベーシヨン膜６で覆われているため、溶融に
よつて飛散する物質はポリシリコン線３とPSG
膜からなる保護膜４との界面や保護膜４の上部に
は付着せず、付着があつてもそれはすべてパツシ
ベーシヨン膜６の上に付着するため、装置内部で
の不要部分の短絡等の不具合は全く生じない。ま
た、溶断後の溶断部及びパツシベーシヨン膜６を
更にパツシベーシヨン膜で覆うと外部から溶断部
への水分や不純物の進入を防止することができ
る。 In the method for manufacturing a semiconductor integrated circuit device of this embodiment, the laser beam irradiation for fusing the polysilicon line 3 is performed directly on the polysilicon line 3, so that the thickness of the PSG film can be reduced as in the conventional method. The fusing can be reliably performed with good reproducibility without being affected by the effects of laser beam irradiation, and furthermore, since the entire top surface is covered with the passivation film 6 except for the portion of the polysilicon line 3 that should be irradiated with laser light, The substances scattered by melting are polysilicon wire 3 and PSG.
It does not adhere to the interface with the protective film 4 or the upper part of the protective film 4, and even if it does, it all adheres to the passivation film 6, so there are no problems such as short circuits in unnecessary parts inside the device. It doesn't happen at all. Furthermore, if the fused portion and the passivation film 6 are further covered with a passivation film after the fused portion is fused, it is possible to prevent moisture and impurities from entering the fused portion from the outside.
以上のように、この発明によれば、ヒユーズ媒
体の所要部分を溶断するに際し、溶断部以外のヒ
ユーズ媒体及びPSG膜等からなる保護膜の全面
をプラズマ窒化膜からなるパツシベーシヨン膜に
覆い、この状態で上記所要部分にレーザ光を照射
するようにしたので、ヒユーズ媒体の溶断を再現
性よく行うことができ、しかも、溶断時にヒユー
ズ媒体が飛散しても回路部等の装置内部に全く影
響がなく、信頼性の高い半導体集積回路装置をえ
ることができる効果がある。
As described above, according to the present invention, when blowing out a required portion of a fuse medium, the entire surface of the fuse medium other than the blown portion and a protective film made of a PSG film, etc. is covered with a passivation film made of a plasma nitride film, and this state Since the laser beam is irradiated to the above-mentioned necessary parts, the fuse medium can be blown with good reproducibility, and even if the fuse medium is scattered during the blowing, there is no effect on the inside of the device such as the circuit section. This has the advantage that a highly reliable semiconductor integrated circuit device can be obtained.
第１図Ａ〜Ｃは従来方法の主要段階での状態を
示す断面図、第２図はヒユーズ媒体上のPSG保
護膜の膜厚とレーザ光反射係数との関係を示す
図、第３図はこの従来方法を用いた場合のVLSI
の製造工程を示すフロー図、第４図Ａ〜Ｅはこの
発明の一実施例の主要工程段階での状態を示す断
面図、第５図はその工程のフロー図である。
図において、１は半導体基板、２は酸化膜、３
はヒユーズ媒体（ポリシリコン線）、４は保護膜
（PSG膜）、６はパツシベーシヨン膜である。な
お図中同一符号は同一又は相当部分を示す。
Figures 1A to C are sectional views showing the main stages of the conventional method, Figure 2 is a diagram showing the relationship between the thickness of the PSG protective film on the fuse medium and the laser beam reflection coefficient, and Figure 3 is a diagram showing the relationship between the thickness of the PSG protective film on the fuse medium and the laser beam reflection coefficient. VLSI using this conventional method
FIGS. 4A to 4E are sectional views showing states at main process steps of an embodiment of the present invention, and FIG. 5 is a flow diagram of the process. In the figure, 1 is a semiconductor substrate, 2 is an oxide film, and 3 is a semiconductor substrate.
4 is a fuse medium (polysilicon line), 4 is a protective film (PSG film), and 6 is a passivation film. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
の不良部を検出し、該検出結果に基づいて上記半
導体集積回路装置の内部に形成されたヒユーズ媒
体の所要部位にレーザ光を照射してこの部分のヒ
ユーズ媒体を溶断し、上記不良部を上記冗長回路
にて置換する半導体集積回路装置の製造方法にお
いて、 上記ヒユーズ媒体上にPSG膜を形成した後、
このPCG膜の一部を除去し、上記ヒユーズ媒体
の所要部位とその周辺のヒユーズ媒体とを表面露
出する工程と、 上記ヒユーズ媒体及び上記保護膜上の全面にプ
ラズマ窒化膜からなるパツシベーヨン膜を形成す
る工程と、 上記ヒユーズ媒体の所要部位の上部にあるパツ
シベーシヨン膜を除去し、この状態で該所要部に
レーザ光を照射する工程とを含むことを特徴とす
る半導体集積回路装置の製造方法。[Scope of Claims] 1. A defective part of a semiconductor integrated circuit device in which a redundant circuit part is formed is detected, and based on the detection result, a laser beam is applied to a desired part of a fuse medium formed inside the semiconductor integrated circuit device. In the method of manufacturing a semiconductor integrated circuit device, the method comprises: irradiating the fuse medium to blow out the fuse medium in this part, and replacing the defective part with the redundant circuit, after forming a PSG film on the fuse medium,
A step of removing a part of this PCG film to expose the surface of a required part of the fuse medium and the fuse medium around it, and forming a passivation film made of a plasma nitride film on the entire surface of the fuse medium and the protective film. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: removing a passivation film above a required portion of the fuse medium, and irradiating the required portion with a laser beam in this state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6841684A JPS60210850A (en) | 1984-04-04 | 1984-04-04 | Manufacture of semiconductor ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6841684A JPS60210850A (en) | 1984-04-04 | 1984-04-04 | Manufacture of semiconductor ic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60210850A JPS60210850A (en) | 1985-10-23 |
| JPH0520902B2 true JPH0520902B2 (en) | 1993-03-22 |
Family
ID=13373052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6841684A Granted JPS60210850A (en) | 1984-04-04 | 1984-04-04 | Manufacture of semiconductor ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60210850A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6246542A (en) * | 1985-08-26 | 1987-02-28 | Toshiba Corp | Wafer test system |
| US4853758A (en) * | 1987-08-12 | 1989-08-01 | American Telephone And Telegraph Company, At&T Bell Laboratories | Laser-blown links |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5641898B2 (en) * | 1973-08-17 | 1981-10-01 | ||
| JPS56146268A (en) * | 1980-04-15 | 1981-11-13 | Fujitsu Ltd | Manufacture of semiconductor memory unit |
| JPS5762544A (en) * | 1980-10-03 | 1982-04-15 | Fujitsu Ltd | Semiconductor device |
| JPS5928374A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5847596Y2 (en) * | 1979-09-05 | 1983-10-29 | 富士通株式会社 | semiconductor equipment |
-
1984
- 1984-04-04 JP JP6841684A patent/JPS60210850A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5641898B2 (en) * | 1973-08-17 | 1981-10-01 | ||
| JPS56146268A (en) * | 1980-04-15 | 1981-11-13 | Fujitsu Ltd | Manufacture of semiconductor memory unit |
| JPS5762544A (en) * | 1980-10-03 | 1982-04-15 | Fujitsu Ltd | Semiconductor device |
| JPS5928374A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60210850A (en) | 1985-10-23 |
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