JPS595624A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS595624A JPS595624A JP11471682A JP11471682A JPS595624A JP S595624 A JPS595624 A JP S595624A JP 11471682 A JP11471682 A JP 11471682A JP 11471682 A JP11471682 A JP 11471682A JP S595624 A JPS595624 A JP S595624A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- drain
- source
- laser beams
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 238000005224 laser annealing Methods 0.000 abstract description 7
- 230000001681 protective effect Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- JNDMLEXHDPKVFC-UHFFFAOYSA-N aluminum;oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Y+3] JNDMLEXHDPKVFC-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910019901 yttrium aluminum garnet Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置の製造方法にかかり、特にＡ文マス
クを用いてイオン注入部へのレーザアニールを行う半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which an ion implantation portion is laser annealed using an A-pattern mask.
（２）技術の背景
近年、例えば電卓、デジタル腕時計、各種家庭用電気機
器、自動車等の日常生活に広汎に使用され始めている各
種］Ｃは、最近の製造技術の発展によるコストダウン、
高密度化、高性能化等によりますますその用途が広がっ
てきている。(2) Technology background In recent years, various products that have begun to be widely used in daily life, such as calculators, digital watches, various household electrical appliances, and automobiles, etc.]C are cost reductions due to recent developments in manufacturing technology.
Due to higher density, higher performance, etc., its uses are expanding more and more.
これら製造技術の発展により、前述の高密度化半導体装
置の各種開発が行われてきており、さらにまた同時に高
性能化の要請も一層高まってきている。With the development of these manufacturing techniques, various developments have been made in the aforementioned high-density semiconductor devices, and at the same time, the demand for higher performance has also increased.
（３）従来技術と問題点
従来ＭＯ３集積回路の製作工程として代表的な方法とし
ては、例えばＡ又−ゲート構造、３ｉ−ゲート構造が標
準的である。(3) Prior Art and Problems Typical manufacturing processes for conventional MO3 integrated circuits include, for example, the A-gate structure and the 3i-gate structure.
前者の製造工程は、第１図（８）乃至（ｄｌの如くまず
フィールド反転防止層（囲路）を形成後にＰ型半導体基
板１に酸化膜例えばＳ １ｏ２２を所定の厚さに形成す
る。ソース、ドレイン領域形成のため５ｉＯ２２に穴を
開ける。次に、５ｉＯ２２をマスクにしてｎ型不純物３
の拡散を行う。（同図（ａ））次に半導体形成領域から
５ｉ０２２の厚い酸化膜を除去し新たに薄いゲート酸化
膜４を成長する。In the former manufacturing process, as shown in FIGS. 1(8) to (dl), a field inversion prevention layer (encircle) is first formed, and then an oxide film, such as S1O22, is formed to a predetermined thickness on the P-type semiconductor substrate 1. Source , a hole is made in 5iO22 to form a drain region.Next, using 5iO22 as a mask, an n-type impurity 3 is added.
to spread the word. ((a) in the same figure) Next, the thick oxide film 5i022 is removed from the semiconductor formation region, and a new thin gate oxide film 4 is grown.
（同図（ｂ））
さらにソース、ドレインとなる領域に穴開けを行う。（
同図（Ｃ））
次に金属薄膜（Ａ文）５を蒸着し、バターニングを行い
ソース６、ゲート７、ドレイン８の電極を形成する。（
同図（ｄ））
後者の製造工程は、第２図（ａｌ乃至Ｔｄｌの如くまず
フィールド反転防止層（囲路）を形成し基板１′上に酸
化膜５ｔＯ２２′を形成しトランジスタ領域の部分は除
去し５ｉＯ２２′をマスクとして窓開けを行った後薄い
ゲート酸化膜４′を成長させる。（同図（ａ））
その後、多結晶シリコン９を用いてゲート部分を形成す
る。（同図（ｂ））
次に多結晶シリコン９よりなるゲート部分をマスクにし
て薄い酸化膜を除去し上から例えばｎ型不純物のイオン
注入若しくは拡散を行う。そしてこのｎ型不純物による
ソース、ドレイン領域３′を形成させる。（同図（Ｃ）
）
次に例えば気相成長法で厚い酸化膜１０を成長させソー
ス、ドレインの電極用の穴を開ける。((b) in the same figure) Furthermore, holes are made in the regions that will become the source and drain. (
(C)) Next, a metal thin film (text A) 5 is deposited and patterned to form the source 6, gate 7, and drain 8 electrodes. (
(d) of the same figure) The latter manufacturing process is as shown in FIG. After removal and opening a window using 5iO22' as a mask, a thin gate oxide film 4' is grown. (Figure (a)) After that, a gate portion is formed using polycrystalline silicon 9. (Figure (b) )) Next, the thin oxide film is removed using the gate portion made of polycrystalline silicon 9 as a mask, and ions of, for example, n-type impurities are implanted or diffused from above.Then, source and drain regions 3' are formed using this n-type impurity. (Figure (C)
) Next, a thick oxide film 10 is grown by, for example, vapor phase growth, and holes for source and drain electrodes are formed.
（同図（ｄ））
その上に例えばＡ交１１の金属蒸着を行い、パターニン
グしてソース、ドレイン電極１２．１３以上、Ａ又−ゲ
ート、Ｓｔ−ゲートともに何れも欠点を有している。す
なわち前者はＡ文電極がソース、ドレインの形成に必要
な高温処理に耐えないので、Ｓｔゲート構造の場合のよ
うな自己整合でのソース、ドレインの形成が困難なため
にソース、ドレインのｎ型領域にオーバラップするゲー
ト電極部領域３１．３２は例えば約１．５μｍ程度の位
置合せ余裕分だけ幅広に形成される必要があるため半導
体装置の高密度化には不適である。((d) in the same figure) For example, a metal evaporation of A-cross 11 is carried out and patterned, and the source and drain electrodes 12, 13 and above, the A-gate, and the St-gate all have defects. In other words, in the former case, the A-type electrode cannot withstand the high-temperature treatment required to form the source and drain, so it is difficult to form the source and drain in self-alignment as in the case of the St gate structure, so the n-type source and drain are difficult to form. The gate electrode portion regions 31 and 32 that overlap the regions need to be formed wide by an alignment margin of about 1.5 μm, for example, and are therefore unsuitable for increasing the density of semiconductor devices.
また、後者は第２図ｔｅｌに示すようにソース、トレイ
ンの領域にオーバラップするゲート電極領域Ｓ１．Ｓ２
は例えば約０．５μｍ程度で高密度には適するもののゲ
ート部に多結晶シリコンを用いであるので高抵抗性を有
するため動作速度が遅いという欠点を有している。In addition, the latter is a gate electrode region S1. which overlaps the source and train regions as shown in FIG. S2
For example, it has a thickness of about 0.5 μm and is suitable for high-density applications, but since the gate portion is made of polycrystalline silicon, it has high resistance and has the disadvantage of slow operation speed.
上記第２図の従来例のように多結晶シリコンをゲートマ
スクとして用いたたときに生ずる高抵抗性を除去するた
めに第１図に示すようにＡ文をマスクとすることが考え
られる。この場合にソース。In order to eliminate the high resistance that occurs when polycrystalline silicon is used as a gate mask as in the conventional example shown in FIG. 2, it is conceivable to use pattern A as a mask as shown in FIG. 1. Source in this case.
ドレインのｎ型拡散層を作るためにイオン注入を行った
後にレーザアニールを行うとＡ文に対するレーザ光の反
射率が高いために、シリコン部分の熱の発生は大きくＡ
又電極部分の熱の発生は小さくできる。しかし、この際
に、例えばＡ又マスクの長手方向に対してレーザ光を蛇
行するように照射するとＡ又マスクパターンの辺をレー
ザ光が照射時間が長いため、シリコン部分で発生した熱
が熱伝導により人文部分へ伝わるために、Ａ又パターン
の辺が熔は出してパターンの形状が崩れたり、極端な場
合にはゲートと基板間に短絡のおこることがあった。上
衣乙の問題はＡ又パターン幅が４μｍ以上であるときは
顕著ではないが、それより細幅のパターンでは大きな問
題となることが判った。If laser annealing is performed after ion implantation to create the n-type diffusion layer of the drain, the heat generation in the silicon part will be large due to the high reflectivity of the laser beam for pattern A.
Furthermore, the generation of heat in the electrode portion can be reduced. However, at this time, for example, if the laser beam is irradiated in a meandering manner in the longitudinal direction of the A-mask pattern, the laser light will irradiate the sides of the A-mask pattern for a long time, so the heat generated in the silicon part will be transferred. As a result, the sides of the A-pattern may melt and the shape of the pattern may collapse, or in extreme cases, a short circuit may occur between the gate and the substrate. It has been found that the problem of the upper part (B) is not noticeable when the pattern width of the pattern (A) is 4 μm or more, but becomes a serious problem with a narrower pattern.
（４）発明の目的
本発明は上記欠点に鑑み、幅４μｍ以下のアルミニウム
パターンよりなるマスク性を要求される部分に対し損傷
を与えることなく、レーザ光を走査し照射することによ
って、イオン注入層に受けたダメージに効果的なアニー
ルを行う方法を提供することを目的とする。(4) Purpose of the Invention In view of the above-mentioned drawbacks, the present invention provides an ion-implanted layer by scanning and irradiating a laser beam without causing damage to the part that requires maskability, which is made of an aluminum pattern with a width of 4 μm or less. The purpose of this invention is to provide a method for effective annealing for damage sustained by
（５）発明の構成
本発明の上記目的とするところは、 マスクとする細長
いアルミニウム（Ａ又）パターンを基体上に形成し、該
Ａ文パターンの長手方向に対し直交してレーザ光を走査
し照射して基体ヘアニールを施すことを特徴とする半導
体装置の製造方法を提供することによって達成される。(5) Structure of the Invention The above object of the present invention is to form an elongated aluminum (A) pattern as a mask on a substrate, and scan a laser beam orthogonally to the longitudinal direction of the A pattern. This is achieved by providing a method for manufacturing a semiconductor device, which is characterized in that hair annealing is performed on a substrate by irradiation.
（６）発明の実施例 以下本発明の実施例について図面と共に説明する。(6) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.
第３図（ａｌ乃至（８１は本発明のＭＯ３半導体装置の
製造工程図である。FIG. 3 (al to (81) are manufacturing process diagrams of the MO3 semiconductor device of the present invention.
Ｐ型基板１′上にフィールド反転防止層（囲路）を形成
の後、トランジスタ領域１４の例えば５ｉ０２からなる
厚い酸化膜２′を除去し、そこに例えば５ｉ０２からな
る薄いゲート酸化膜４′を再度成長させる。（同図（ａ
ｌ ）
次に本発明の特徴とするレーザアニールに対する保護を
兼ねたＡ文膜をゲート部１５に形成し、ゲート電極１５
′を作る。（同図（ｂ））このＡ文をマスクとして薄い
ＳｉＯ２の酸化膜４′を除去する。この領域に例えば
自己整合で上からイオン注入を行ってソース、ドレイン
のイオン注入層３′を形成する。（同図（Ｃ））ここで
、イオン注入時の損傷を除去するために例えば出力０．
３５Ｗ 、パルス５ Ｋ Ｈｚ、 ２０μ／ ５ｔｅｐ
で窩部にてＹＡＧ （イツトリウム・アルミニウム・ガ
ーネット）レーザによりトランジスタ領域１４全体に亘
り、第４図に示すようにゲート電極１５′の長手方向の
辺と直交する方向に連続的に走査１８する。この場合ゲ
ート電極パターンが第４図のようにＬ字状に折れ曲って
いるような場合は短辺１５ａが４μｍ以上であれば長手
方向に沿って走査しても特に問題なくアニールすること
ができる。すなわち、４μｍ以上の太いパターンの場合
には、長手方向に沿って走査してもシリコン部分より伝
わる熱が長手方向だけでなく、短手方向にもかなりの大
きさで拡散するため、Ａ文パクーンの端部の温度上昇が
抑えられるためである。After forming a field inversion prevention layer (surrounding circuit) on the P-type substrate 1', the thick oxide film 2' made of, for example, 5i02 in the transistor region 14 is removed, and a thin gate oxide film 4' made of, for example, 5i02 is formed thereon. Let it grow again. (Same figure (a)
l) Next, an A pattern film that also serves as protection against laser annealing, which is a feature of the present invention, is formed on the gate portion 15, and the gate electrode 15 is
'make. (Figure (b)) Using this pattern A as a mask, the thin SiO2 oxide film 4' is removed. Ion implantation is performed in this region from above in a self-aligned manner, for example, to form source and drain ion implantation layers 3'. ((C) of the same figure) Here, in order to remove damage during ion implantation, for example, the output is set to 0.
35W, pulse 5KHz, 20μ/5tep
At the cavity, a YAG (yttrium aluminum garnet) laser is used to continuously scan 18 the entire transistor region 14 in a direction perpendicular to the longitudinal sides of the gate electrode 15', as shown in FIG. In this case, if the gate electrode pattern is bent in an L-shape as shown in Figure 4, annealing can be performed without any particular problem even if the short side 15a is 4 μm or more, even if the gate electrode pattern is scanned along the longitudinal direction. . In other words, in the case of a thick pattern of 4 μm or more, even when scanning along the longitudinal direction, the heat transmitted from the silicon part is diffused not only in the longitudinal direction but also in the lateral direction to a considerable extent. This is because the temperature rise at the end of the tube can be suppressed.
なお、この場合Ａ又保護１！ｔ１５′は表面が人文によ
って形成されており、レーザ光を反射するためレーザ光
線から保護されている。従ってＡ支保護膜１５′下部の
ゲート領域はかかるレーザ光線の影響は何等受けること
がないが、残りの領域すなわちソース、ドレインとなる
イオン注入層３′はレーザ光線の照射を受けてアニール
される。通常注入イオンは、その運動エネルギーを失う
前に格子の原子と衝突してその原子を格子点から移動さ
せる。この結果、多くの空位が生じて非晶質層等に変化
する。従って、イオン注入後にアニールを行って再び結
晶構造を持つようにすることが必要となる。アニールに
よりイオン注入層のソース。In this case, A also protects 1! The surface of t15' is formed by humanities and is protected from the laser beam because it reflects the laser beam. Therefore, the gate region under the A-supporting protective film 15' is not affected by the laser beam at all, but the remaining region, that is, the ion-implanted layer 3' which becomes the source and drain, is irradiated with the laser beam and annealed. . Typically, implanted ions collide with atoms in the lattice, displacing them from lattice points, before losing their kinetic energy. As a result, many vacancies are generated and the layer changes to an amorphous layer or the like. Therefore, it is necessary to perform annealing after ion implantation to restore the crystal structure. Anneal the source of the ion implantation layer.
ドレイン両部の比抵抗は低減されトランジスタとしての
動作機能が回復される。次に気相成長法で例えば３ｉ０
２の厚い酸化膜１０′を成長させソース１６．ドレイン
１７用の穴開けを行う。（同図（ｄ））
この上に例えばＡ又により金属蒸着を行い、パターニン
グしてソース、ドレインの電極１２′。The specific resistance of both the drain parts is reduced and the operational function as a transistor is restored. Next, by vapor phase growth method, for example, 3i0
A thick oxide film 10' of source 16.2 is grown. Drill a hole for the drain 17. ((d) in the same figure) On top of this, metal is deposited using, for example, A or the like, and patterned to form source and drain electrodes 12'.
１３′を作る。（同図（ｅ））
すなわち本発明によれば半導体基板１゛上のフィールド
反転層内のトランジスタ領域１４にソース、ドレインと
なるイオン注入層３′が設けられ、また中央部には絶縁
層４′が形成され、さらにその上に本発明の特徴であり
レーザアニールの際の保護膜となるゲート部のＡ支保護
膜１５′が設けられ、レーザアニールに際するレーザ光
の照射をＡ支保護膜１５′の長辺とほぼ直交する方向に
行うのでＡ支保護膜１５′の辺が受けとるレーザパワー
は少ないのでこの辺部分が熔けてしまうことがなく、一
方ではソース、ドレイン領域には有効なレーザアニール
を行えるだけのレーザパワーを与えることができる。Make 13'. ((e) in the same figure) That is, according to the present invention, an ion-implanted layer 3' serving as a source and a drain is provided in the transistor region 14 in the field inversion layer on the semiconductor substrate 1, and an insulating layer 4 is provided in the center. ' is formed, and furthermore, an A-supporting protective film 15' of the gate portion, which is a feature of the present invention and serves as a protective film during laser annealing, is provided on the A-supporting film 15', which protects the A-supporting film from being irradiated with laser light during laser annealing. Since the laser power is applied in a direction almost perpendicular to the long side of the film 15', the side of the A-supporting protective film 15' receives less laser power, so this side does not melt.On the other hand, the laser power is effective for the source and drain regions. Laser power sufficient to perform annealing can be provided.
上述の如く本発明は、ＭＯ３半導体装置でのレーザアニ
ールに実施した場合を説明したが、上記以外においても
Ａ又のマスキングにて選択的にレーザ照射を行う場合
であれば何れの用途でも使用可能である。As mentioned above, the present invention has been described for the case where it is applied to laser annealing in an MO3 semiconductor device, but it can be used for any purpose other than the above as long as laser irradiation is performed selectively by masking A or the like. It is.
（７）発明の効果
本発明は例えば半導体装置製造工程において、Ａ又金属
薄膜を選択マスクとして用いて、該Ａ又金属薄膜パター
ンに対して９０′前後をなす角度でレーザ光の走査を行
い照射させることにより、良好な自己整合が可能となり
ゲート−ソース及びゲート−ドレイン間のオーバラップ
領域Ｓ１及びＳ２を短縮できるためトランジスタの高密
度化が可能となり、結局ゲート幅を短くすることが可能
であり、またゲート部に電気伝導性の高いＡ文を使用し
であるためにゲート部の抵抗を低くおさえることができ
、更にＡ文金属薄膜パターンに沿ってレーザアニールす
る場合に比べ、より強いレーザパワーを照射してもＡ文
金属薄膜パターンに変化をおこさせないので、ソース、
ドレインの抵抗をより小さくすることができ、従ってト
ランジスタとしての動作速度を高めることが可能となる
特徴を有する。(7) Effects of the Invention The present invention is applied, for example, in a semiconductor device manufacturing process, by using an A or metal thin film as a selective mask and scanning and irradiating the A or metal thin film pattern with a laser beam at an angle of about 90'. This enables good self-alignment and shortens the gate-source and gate-drain overlap regions S1 and S2, making it possible to increase the density of transistors and ultimately shorten the gate width. In addition, since the gate part uses A pattern with high electrical conductivity, the resistance of the gate part can be kept low, and the laser power is stronger than when laser annealing is performed along the A pattern metal thin film pattern. The source,
It has a feature that the resistance of the drain can be lowered, and therefore the operating speed of the transistor can be increased.
第１図（ａ）乃至（ｄ）は従来のアルミニウムゲート構
造のＭＯ３半導体装置の製造工程図、第２図（ａｌ乃至
（ｅ）は同じ〈従来のシリコンゲート構造のＭＯ３集積
装置の製造工程図、第３図（ａｌ乃至（ｅ）は本発明の
半導体を取り入れたＭＯ３半導体装置の工程図、第４図
は本発明のＡ文マスク上の走査方法を説明する路線図で
ある。
１．１′・・・Ｐ型基板、 ３・・・イオン注入層（ガ
ス拡散層）、 ４．４′・・・ゲート酸化膜、 ５・
・・金属薄膜、 ６，１６・・・ソース、 ７・・・
ゲート、 ８．１７・・・ドレイン、 ９・・・多
結晶シリコン、 １２・・・ソース電極、 １３・
・・ドレイン電極、 １４・・・トランジスタ領域、
１５′・・・Ａ文ゲート電極。
夙 ２Ｉ２Ｉｌ
第 ３ 図
−１８
）
〉
）Figures 1 (a) to (d) are manufacturing process diagrams of a conventional MO3 semiconductor device with an aluminum gate structure, and Figures 2 (al to (e) are the same) (manufacturing process diagrams of a conventional MO3 integrated device with a silicon gate structure) , Fig. 3 (al to e) are process diagrams of an MO3 semiconductor device incorporating the semiconductor of the present invention, and Fig. 4 is a route diagram explaining the scanning method on the A pattern mask of the present invention. 1.1 '... P-type substrate, 3... Ion implantation layer (gas diffusion layer), 4.4'... Gate oxide film, 5.
...metal thin film, 6,16...source, 7...
Gate, 8.17...Drain, 9...Polycrystalline silicon, 12...Source electrode, 13.
...Drain electrode, 14...Transistor region,
15'...A gate electrode.夙 2I2Il Figure 3-18 ) 〉 )
Claims (1)
体上に形成し、該Ａ文パターンの長手方向に対し直交し
てレーザ光を走査し照射して基体ヘアニールを施すこと
を特徴とする半導体装置の製造方法。Manufacture of a semiconductor device characterized by forming an elongated aluminum (A-shaped) pattern as a mask on a substrate, and performing hair annealing on the substrate by scanning and irradiating laser light perpendicular to the longitudinal direction of the A pattern. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11471682A JPS595624A (en) | 1982-07-01 | 1982-07-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11471682A JPS595624A (en) | 1982-07-01 | 1982-07-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS595624A true JPS595624A (en) | 1984-01-12 |
Family
ID=14644828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11471682A Pending JPS595624A (en) | 1982-07-01 | 1982-07-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS595624A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5817548A (en) * | 1995-11-10 | 1998-10-06 | Sony Corporation | Method for fabricating thin film transistor device |
| US6054739A (en) * | 1994-12-16 | 2000-04-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having channel refractive index in first and second directions |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5681973A (en) * | 1979-12-06 | 1981-07-04 | Toshiba Corp | Manufacture of mos type semiconductor device |
| JPS5745246A (en) * | 1980-08-30 | 1982-03-15 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1982
- 1982-07-01 JP JP11471682A patent/JPS595624A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5681973A (en) * | 1979-12-06 | 1981-07-04 | Toshiba Corp | Manufacture of mos type semiconductor device |
| JPS5745246A (en) * | 1980-08-30 | 1982-03-15 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054739A (en) * | 1994-12-16 | 2000-04-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having channel refractive index in first and second directions |
| US6242292B1 (en) * | 1994-12-16 | 2001-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Method of producing a semiconductor device with overlapped scanned linear lasers |
| US6274885B1 (en) | 1994-12-16 | 2001-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device with TFTs of different refractive index |
| US5817548A (en) * | 1995-11-10 | 1998-10-06 | Sony Corporation | Method for fabricating thin film transistor device |
| US5943593A (en) * | 1995-11-10 | 1999-08-24 | Sony Corporation | Method for fabricating thin film transistor device |
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