KR100489586B1 - Method of forming junction part of semiconductor device - Google Patents
Method of forming junction part of semiconductor device Download PDFInfo
- Publication number
- KR100489586B1 KR100489586B1 KR1019970079303A KR19970079303A KR100489586B1 KR 100489586 B1 KR100489586 B1 KR 100489586B1 KR 1019970079303 A KR1019970079303 A KR 1019970079303A KR 19970079303 A KR19970079303 A KR 19970079303A KR 100489586 B1 KR100489586 B1 KR 100489586B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- semiconductor substrate
- junction
- oxygen ions
- ions
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 36
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 22
- 239000001301 oxygen Substances 0.000 claims abstract description 22
- -1 oxygen ions Chemical class 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 24
- 230000007547 defect Effects 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000035515 penetration Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010884 ion-beam technique Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 소자의 접합부 형성 방법에 관한 것으로, 특히 산소 이온 및 P+ 이온의 이중 이온 주입공정을 실시하여 별도의 산화 공정 없이 고집적 반도체 소자의 얕은 접합부를 형성하는 방법에 관한 것임.The present invention relates to a method of forming a junction of a semiconductor device, and more particularly to a method of forming a shallow junction of a highly integrated semiconductor device without a separate oxidation process by performing a double ion implantation process of oxygen ions and P + ions.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
반도체 소자가 고집적화되어 감에 따라 트랜지스터 영역이 작아지게 되고 따라서 보다 얕은 접합부가 요구되고 있으나 공정 상 얕은 접합부를 형성하는데 한계가 있음.As semiconductor devices become more integrated, transistor regions become smaller and therefore shallower junctions are required, but there is a limit to forming shallow junctions in the process.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
산소 이온 및 P+ 이온의 이중 이온 주입공정을 실시하여 별도의 산화 공정 없이 고집적 반도체 소자의 얕은 접합부를 형성함.A double ion implantation process of oxygen ions and P + ions is performed to form shallow junctions of highly integrated semiconductor devices without a separate oxidation process.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 접합부 형성 공정.Bonding part formation process of a semiconductor element.
Description
본 발명은 반도체 소자의 접합부(junction) 형성 방법에 관한 것으로, 특히 산소(O2) 이온 및 P+ 이온의 이중 이온 주입공정(Double Ion Implanting)을 실시하여 별도의 산화 공정(oxidation) 없이 고집적 반도체 소자의 얕은 접합부(shallow junction)를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a junction of a semiconductor device. In particular, a highly integrated semiconductor without a separate oxidation process is performed by performing double ion implantation of oxygen (O 2 ) ions and P + ions. A method of forming a shallow junction of a device.
반도체 소자의 제조 공정 중 모스 트랜지스터(MOS transistor)를 형성시키기 위한 소오스(source) 전극 및 드레인(drain) 전극 형성 공정은 가장 기본적이면서 반도체 소자의 전기적 특성을 결정짓는 중요한 기술이다. 그런데 반도체 소자가 초고집적화 됨에 따라 선폭(line width)이 0.1 ㎛ 이하인 게이트(gate)가 형성되면서 소오스 전극 및 드레인 전극의 얕은 접합은 필수 불가결한 요소가 되어 왔다.A source electrode and a drain electrode forming process for forming a MOS transistor among semiconductor device manufacturing processes are the most basic and important techniques for determining electrical characteristics of semiconductor devices. However, as semiconductor devices are highly integrated, a gate having a line width of 0.1 μm or less is formed, and a shallow junction between the source electrode and the drain electrode has become an indispensable element.
종래의 기술에 있어서 P+ 타입의 얕은 접합을 형성시키기 위한 방법으로는 11B+ 이온을 소오스로 주입하되 오토믹 매스 유니트(Atomic Mass Unit)가 큰 49BF+ 2를 사용하였다. 최근에는 더욱 더 얕은 접합이 요구됨에 따라 이온 빔(ion beam)을 이용하여 이온 주입 공정을 진행한다. 먼저 반도체 기판 상에 산화막을 형성하고 마스크 패턴을 이용하여 반도체 기판의 선택된 영역에 이온 주입 공정을 실시하되, 반도체 기판의 법선 성분으로부터 7°이하의 기울기를 갖는 이온 주입 각도를 유지하여 이온 빔 이온 주입 공정을 실시한다. 이 때 이온 빔의 에너지를 점점 줄여 보다 낮은 접합이 형성되도록 하고 있으나, 에너지를 줄이는데 있어 한계점에 도달하였다. 또한 반도체 소자를 형성하기 위한 여러 가지 열 공정에 의하여 접밥부 영역이 스트레스(stress)를 받게되어 손상(damage)을 입게 되는 등의 문제점이 발생하고 있다.In the related art, as a method for forming a shallow junction of P + type, 49BF + 2 having 11 A + + implanted into a source but having a large atomic mass unit was used. Recently, as a shallower junction is required, an ion implantation process is performed using an ion beam. First, an oxide film is formed on a semiconductor substrate and an ion implantation process is performed on a selected region of the semiconductor substrate using a mask pattern, while maintaining an ion implantation angle having a slope of 7 ° or less from a normal component of the semiconductor substrate to implant an ion beam ion. Carry out the process. At this time, the energy of the ion beam is gradually reduced to form a lower junction, but the limit point is reached in reducing the energy. In addition, a problem arises such that the area of the folded portion is subjected to stress due to various thermal processes for forming a semiconductor device, resulting in damage.
본 발명은 위와 같은 문제점 없이 특성이 우수한 반도체 소자의 얕은 접합부를 형성하는데 그 목적이 있다.An object of the present invention is to form a shallow junction of a semiconductor device having excellent characteristics without the above problems.
상술한 목적을 달성하기 위한 반도체 소자의 접합부 형성 방법은, 반도체 기판 상부에 게이트 전극 및 게이트 절연막을 형성한 후, 상기 반도체 기판의 선택된 영역이 노출되도록 감광막 패턴을 형성하는 단계와, 상기 노출된 반도체 기판에 산소 이온 주입 공정을 실시하되, 주입되는 산소 이온이 반도체 기판의 표면을 비정질화 시키고 격자 결함을 발생시켜 침투되도록 하는 단계와, 상기 산소 이온이 침투된 반도체 기판에 불순물 이온 주입 공정을 실시하여 접합부를 형성하되, 상기 주입된 산소 이온이 불순물 이온의 깊은 침투를 억제하여 얕은 접합이 형성되도록 하는 단계와, 이 후 반도체 소자를 제조하기 위한 열처리 공정에서 상기 산소 이온과 반도체 기판의 실리콘 성분이 자연스럽게 반응하여 산화막이 형성되도록 하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a junction portion of a semiconductor device may include forming a photoresist pattern on a semiconductor substrate to expose a selected region of the semiconductor substrate, and then forming a photoresist pattern on the semiconductor substrate; Performing an oxygen ion implantation process on the substrate, the implanted oxygen ions amorphize the surface of the semiconductor substrate and cause a lattice defect to penetrate, and impurity ion implantation process to the oxygen substrate penetrated Forming a junction, wherein the implanted oxygen ions inhibit deep penetration of impurity ions so that a shallow junction is formed, and then the oxygen ions and the silicon component of the semiconductor substrate are naturally formed in a heat treatment process for manufacturing a semiconductor device. Reacting to form an oxide film Characterized in that eojineun.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 접합부 형성 방법을 설명하기 위해 도시한 단면도이다.1 (a) to 1 (d) are cross-sectional views illustrating a method of forming a junction of a semiconductor device according to the present invention.
도 1(a)는 반도체 기판(11) 상에 게이트 전극(12) 및 게이트 절연막(13)을 형성하고, 감광막 패턴(14)을 이용하여 반도체 기판(11) 상부의 소오스 전극 및 드레인 전극이 형성될 영역만을 노출 시킨 단면도이다.FIG. 1A illustrates a
이 후 공정으로 도 1(b)에 도시된 것과 같이, 감광막 패턴(14)을 마스크로 하여 반도체 기판의 노출된 영역에 이온 주입 공정을 실시한다. 먼저 산소 이온을 불순물 이온으로 주입하는데, 주입된 산소 이온은 반도체 기판(11) 표면을 비정질화 시키고 격자 결함을 발생시킨다. 또한 일부의 산소 이온은 이러한 반도체 기판(11)의 격자 결함 사이로 침투하게 된다.Subsequently, as shown in FIG. 1B, an ion implantation process is performed on the exposed region of the semiconductor substrate using the
도 1(c)는 산소 이온이 주입된 접합부(15) 영역에 P+ 타입의 접합부를 형성하기 위해 B+ 소오스 이온을 주입하여 P+ 접합부(16)를 형성한 단면도이다. P+ 접합부(16)의 소오스 이온으로는 49BF+ 2를 사용한다. 이 때 이전 공정에서 주입된 산소 이온으로 인하여, 이온 주입 공정시 흔히 발생할 수 있는 채널링(channeling) 현상이 발생하지 않는 장점이 있다. 또한 반도체 기판(11)의 표면을 개질하며 침투된 산소 이온이 B+ 이온의 깊은 침투를 억제하여, 상대적으로 낮은 접합부(16)가 형성된다.Figure 1 (c) is by implanting B + ions for forming the source and P + type region of the junction in the oxygen ion is the joined
도 1(d)는 감광막 패턴(14)을 제거한 후, 반도체 소자를 형성하기 위한 이 후 열처리 공정에서 주입된 산소 이온과 반도체 기판(11)의 실리콘 성분이 자연스럽게 반응하여 산화막(SiO2 ; 17)을 형성한 단면도이다. 그러므로 별도의 산화막 형성을 위한 열 공정 없이 산화막(17)이 형성되어, 미세한 얕은 접합부의 열 손상을 방지할 수 있게 된다.FIG. 1D illustrates that after the
상술한 바와 같이 본 발명에 의하면, 이중 이온 주입 공정을 통하여 접합부의 깊이를 제어할 수 있고, 산화막을 형성하기 위한 별도의 산화 공정이 없이 산화막을 형성시킴으로 접합부의 열적인 보호는 물론 공정의 단순화와 고집적 반도체 소자의 제조 공정 기술이 확보되는 탁월한 효과가 있다.As described above, according to the present invention, the depth of the junction portion can be controlled through the dual ion implantation process, and the oxide layer is formed without a separate oxidation process for forming the oxide layer, thereby thermally protecting the junction portion as well as simplifying the process. There is an excellent effect that the manufacturing process technology of the highly integrated semiconductor device is secured.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 접합부 형성 방법을 설명하기 위해 도시한 단면도.1 (a) to 1 (d) are cross-sectional views illustrating a method of forming a junction of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 게이트 전극11
13 : 게이트 절연막 14 : 감광막13 gate
15 : 산소 이온이 주입된 접합부 영역 16 : P+ 접합부15: junction region implanted with oxygen ions 16: P + junction
17 : 산화막17: oxide film
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970079303A KR100489586B1 (en) | 1997-12-30 | 1997-12-30 | Method of forming junction part of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970079303A KR100489586B1 (en) | 1997-12-30 | 1997-12-30 | Method of forming junction part of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990059106A KR19990059106A (en) | 1999-07-26 |
| KR100489586B1 true KR100489586B1 (en) | 2005-09-06 |
Family
ID=37304456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970079303A KR100489586B1 (en) | 1997-12-30 | 1997-12-30 | Method of forming junction part of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100489586B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100310174B1 (en) * | 1999-12-31 | 2001-09-28 | 황인길 | Implant damage recovery method by remain oxide |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5583263A (en) * | 1978-12-19 | 1980-06-23 | Fujitsu Ltd | Mos semiconductor device |
| JPS61263274A (en) * | 1985-05-17 | 1986-11-21 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS63144575A (en) * | 1986-12-09 | 1988-06-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0794721A (en) * | 1993-09-24 | 1995-04-07 | Nippon Steel Corp | Semiconductor device and manufacture thereof |
-
1997
- 1997-12-30 KR KR1019970079303A patent/KR100489586B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5583263A (en) * | 1978-12-19 | 1980-06-23 | Fujitsu Ltd | Mos semiconductor device |
| JPS61263274A (en) * | 1985-05-17 | 1986-11-21 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS63144575A (en) * | 1986-12-09 | 1988-06-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0794721A (en) * | 1993-09-24 | 1995-04-07 | Nippon Steel Corp | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990059106A (en) | 1999-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR19990030992A (en) | Semiconductor device with double spacer and method of manufacturing same | |
| JPH05218075A (en) | Process for manufacture of semiconductor metal-oxide semiconductor device | |
| JPS6214459A (en) | Manufacture of semiconductor device | |
| US6800528B2 (en) | Method of fabricating LDMOS semiconductor devices | |
| KR100489586B1 (en) | Method of forming junction part of semiconductor device | |
| US5994737A (en) | Semiconductor device with bird's beak | |
| JP2006310484A (en) | Method for manufacturing semiconductor device | |
| KR100217899B1 (en) | Method of manufacturing transistor of semiconductor device | |
| JP4180809B2 (en) | Manufacturing method of semiconductor device | |
| KR101025917B1 (en) | MOS transistor and method for manufacturing the same | |
| KR100456579B1 (en) | Mask Read-Only Memory(ROM) Devices And Method Of Fabricating The Same | |
| KR100406589B1 (en) | Manufacturing method of semiconductor device | |
| KR100370154B1 (en) | Method for manufacturing of semiconductor device | |
| KR100260366B1 (en) | Method for fabricating semiconductor device | |
| KR100520216B1 (en) | Semiconductor device manufacturing method | |
| JPH06244415A (en) | Semiconductor device and manufacture thereof | |
| JPH10261795A (en) | Insulating gate-type field-effect transistor and its manufacture | |
| KR100321753B1 (en) | Method for fabricating metal oxide semiconductor transistor | |
| KR101051801B1 (en) | Transistor of semiconductor device and manufacturing method thereof | |
| KR0171734B1 (en) | Mos transistor of semiconductor device | |
| KR0140703B1 (en) | A method manufacture of polysilicon soure/drain | |
| KR20000004535A (en) | Method for forming isolating insulator of semiconductor devices | |
| JPH10163490A (en) | Manufacture of transistor | |
| KR19980046004A (en) | Semiconductor device and manufacturing method thereof | |
| JPH0214788B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| AMND | Amendment | ||
| E601 | Decision to refuse application | ||
| J201 | Request for trial against refusal decision | ||
| AMND | Amendment | ||
| B701 | Decision to grant | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110429 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |