KR100329748B1 - Mosfet having ldd structure for preventing drain junction leakage - Google Patents
Mosfet having ldd structure for preventing drain junction leakage Download PDFInfo
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- KR100329748B1 KR100329748B1 KR1019950012760A KR19950012760A KR100329748B1 KR 100329748 B1 KR100329748 B1 KR 100329748B1 KR 1019950012760 A KR1019950012760 A KR 1019950012760A KR 19950012760 A KR19950012760 A KR 19950012760A KR 100329748 B1 KR100329748 B1 KR 100329748B1
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- South Korea
- Prior art keywords
- mosfet
- region
- junction leakage
- ldd structure
- drain
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- 125000006850 spacer group Chemical group 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 9
- 230000000452 restraining effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 제조 공정중 모스펫(MOSFET) 구조에 관한 것으로, 특히 드레인 접합 누설 방지를 위한 LDD(lightly dopped drain) 구조의 모스펫에 관한 것이다.The present invention relates to a MOSFET structure during a semiconductor manufacturing process, and more particularly to a MOSFET having a lightly dopped drain (LDD) structure for preventing drain junction leakage.
제 1 도는 종래의 LDD 구조를 갖는 모스펫 주요부분 평면도로서, 도면에서11은 게이트, 12는 게이트 측벽의 산화막 스페이서, 13은 필드영역, 14는 액티브영역, 15는 소스드레인 형성을 위한 불순물 이온주입 영역을 각각 나타낸다.1 is a plan view of a MOSFET having a conventional LDD structure, in which FIG. 11 is a gate, 12 is an oxide spacer of a gate sidewall, 13 is a field region, 14 is an active region, and 15 is an impurity ion implantation region for source drain formation. Respectively.
잘 알려진 바와 같이 통상적인 LDD 구조 모스펫 제조 방법은, 반도체기판에 소자분리막을 형성하여 필드영역과 액티브영역을 정의하고, 게이트전극 형성 후, 저농도 불순물 이온주입과 게이트 측벽 스페이서 형성, 및 고농도 불순물 이온주입을 차례로 형성하여 모스펫을 제조하고 있다.As is well known, the conventional LDD structure MOSFET manufacturing method forms a device isolation film on a semiconductor substrate to define a field region and an active region, and after the gate electrode is formed, low concentration impurity ion implantation and gate sidewall spacer formation, and high concentration impurity ion implantation To form a MOSFET in order to manufacture.
게이트 측벽 산화막 스페이서는 게이트가 형성된 기판 상에 산화막을 증착한 다음 이 산화막을 다시 전면 비등방성 식각하는 방법을 사용하는 바, 이때의 비등방성 식각으로 인해 스페이서 가장자리를 따라 액티브 영역은 식각 손상을 받게된다. 특히 필드 영역(13)과 액티브 영역(14)의 경계부위(도면의 a)에서 심하게 손상을 받는다. 한편, 소스/드레인 형성을 위한 고농도 불순물 이온주입시 이온주입되는 액티브영역은 비정질화되고 이후 열처리 공정에 의해 재결정화된다.The gate sidewall oxide spacer is a method of depositing an oxide layer on a substrate on which a gate is formed, and then anisotropically etching the oxide layer again. The anisotropic etching causes the active region to be etched along the spacer edge. . In particular, it is severely damaged at the boundary between the field region 13 and the active region 14 (a in the drawing). On the other hand, during the implantation of high concentration impurity ions for source / drain formation, the active region implanted with ions is amorphous and then recrystallized by a heat treatment process.
따라서, 재결정화 되어가는 도중에 결정방향의 미스매치에 의해 디스로케이션 루프가 측벽 스페이서 가장자리를 따라 발생하여 드레인 접합 누설을 증가시킨다. 특히 게이트 측벽 산화막 스페이서 형성시 필드영역과 액티브영역이 교차하는 부위에서 식각 손상이 가장 심하게 발생하는 바, 이곳에서 드레인 접합 누설이 크게 발생된다.Thus, during recrystallization, dislocation loops occur along the sidewall spacer edges due to mismatches in the crystallization direction to increase drain junction leakage. In particular, when the gate sidewall oxide layer spacer is formed, etching damage is most severely generated at the intersection of the field region and the active region, and a drain junction leakage is greatly generated.
본 발명은 상기 종래기술의 문제점을 해결하기 위하여 안출된 것으로, 게이트 측벽 스페이서 형성시 식각 손상이 가장 심한 필드영역과 액티브영역의 경계부위에서 소스/드레인 형성을 위한 고농도 불순물 이온주입이 실시되지 않도록 하여드레인 접합 누설을 억제하는데 적합한 LDD 구조의 모스펫을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and it is possible to prevent high concentration impurity ion implantation for source / drain formation at the boundary between field and active regions where etching damage is most severe when forming gate sidewall spacers. It is an object of the present invention to provide a MOSFET having an LDD structure suitable for suppressing junction leakage.
상기 목적을 달성하기 위하여 본 발명은 LDD 구조의 모스펫에 있어서, LDD 구조의 모스펫에 있어서, 소자의 필드영역과 액티브영역의 경계 부위 중에서 게이트 측벽에 형성되는 절연막 스페이서와 교차하는 부위가 소스/드레인 형성을 위한 고농도 이온주입 영역의 외곽에 형성된 것을 특징으로 한다.In order to achieve the above object, the present invention provides a MOSFET having an LDD structure, in which a portion of an LDD structure has a source / drain formation where an area intersecting with an insulating film spacer formed on a gate sidewall is formed between a boundary between a field region and an active region of the device. It is characterized in that formed on the outer periphery of the high concentration ion implantation region.
이하, 첨부된 도면 제 2 도 및 제 3 도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 2 and 3.
제 2 도는 본 발명에 따른 LDD 구조를 갖는 모스펫 주요부분 평면도이고, 제 3 도는 제 2 도의 사시도로서, 도면에서 21은 게이트, 22는 게이트 측벽의 산화막 스페이서, 23은 필드영역, 24는 액티브영역, 25는 소스/드레인 형성을 위한 고농도 불순물 이온주입 영역을 각각 나타낸다.2 is a plan view of a MOSFET having an LDD structure according to the present invention, and FIG. 3 is a perspective view of FIG. 2, in which 21 is a gate, 22 is an oxide spacer of a gate sidewall, 23 is a field region, 24 is an active region, 25 denotes high concentration impurity ion implantation regions for source / drain formation, respectively.
제 2 도 및 제 3 도에 도시된 바와 같이, 본 발명은 게이트 측벽 스페이서(22) 형성시 식각 손상이 가장 심한 필드영역(23)과 액티브 영역(24)의 경계부위(도면의 b)가 고농도 이온주입 영역에서 벗어나도록 하기 위하여, 아이솔레이션 패턴 중의 레이아웃을 변경하는 것이다.As shown in FIG. 2 and FIG. 3, the present invention has a high concentration at the boundary between the field region 23 and the active region 24 (b) in which the etching damage is most severe when the gate sidewall spacers 22 are formed. In order to be out of the ion implantation region, the layout in the isolation pattern is changed.
즉, 본 발명의 LDD 구조의 모스펫은 소자의 필드영역(23)과 액티브영역(24)의 경계 부위중 게이트 측벽에 형성되는 절연막 스페이서(22)와 교차하는 부위(도면의 b)가 소스/드레인 형성을 위한 고농도 불순물 이온주입 영역(25) 밖으로 형성되어 있다.That is, in the MOSFET of the LDD structure of the present invention, a portion (b in the figure) intersecting with the insulating film spacer 22 formed on the gate sidewall among the boundary portions of the field region 23 and the active region 24 of the device is the source / drain. It is formed outside the high concentration impurity ion implantation region 25 for formation.
따라서, 스페이서(22) 형성시 손상이 심해지는 필드영역(23)과 액티브영역(24)의 경계 지역에는 이온 주입이 없어 비정질화 및 재결정화에 따른 디스로케이션 루프의 발생이 억제된다. 결국 필드영역(23)과 액티브영역(24) 및 스페이서(22)가 교차하는 부위(도면의 b)에서 드레인 접합 누설이 억제된다.Therefore, there is no ion implantation in the boundary region between the field region 23 and the active region 24, which is severely damaged when the spacer 22 is formed, so that the occurrence of the dislocation loop due to amorphous and recrystallization is suppressed. As a result, drain junction leakage is suppressed at the site where the field region 23, the active region 24, and the spacer 22 cross (b in the figure).
본 발명은 게이트 측벽 스페이서를 따라 발생하는 디스로케이션 루프 발생을 방지하여 드레인 접합 누설을 방지하므로써 소자의 전류 특성 및 전압 특성을 개선할 수 있다.The present invention can improve the current characteristics and the voltage characteristics of the device by preventing the drain junction leakage by preventing the occurrence of the dislocation loop along the gate sidewall spacer.
제 1 도는 종래의 LDD 구조를 갖는 모스펫 주요부분 평면도,1 is a plan view of a main portion of a MOSFET having a conventional LDD structure,
제 2 도 및 제 3 도는 본 발명에 따른 LDD 구조를 갖는 모스펫 주요부분의 평면도 및 사시도.2 and 3 are a plan view and a perspective view of the main portion of the MOSFET having the LDD structure according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 게이트21: gate
22 : 게이트 측벽의 산화막 스페이서22: oxide spacer on the sidewall of the gate
23 : 필드영역23: field area
24 : 액티브영역24: active area
25 : 소스/드레인 불순물 이온주입 영역25: source / drain impurity ion implantation region
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012760A KR100329748B1 (en) | 1995-05-22 | 1995-05-22 | Mosfet having ldd structure for preventing drain junction leakage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012760A KR100329748B1 (en) | 1995-05-22 | 1995-05-22 | Mosfet having ldd structure for preventing drain junction leakage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960043272A KR960043272A (en) | 1996-12-23 |
| KR100329748B1 true KR100329748B1 (en) | 2002-08-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950012760A KR100329748B1 (en) | 1995-05-22 | 1995-05-22 | Mosfet having ldd structure for preventing drain junction leakage |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0284737A (en) * | 1988-09-21 | 1990-03-26 | Nec Corp | Manufacture of semiconductor device |
| JPH03184346A (en) * | 1989-12-13 | 1991-08-12 | Olympus Optical Co Ltd | Semiconductor device and manufacture thereof |
| JPH03188637A (en) * | 1989-12-18 | 1991-08-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR920003519A (en) * | 1990-07-13 | 1992-02-29 | 문정환 | Stacked Cell Manufacturing Method and Structure |
| US5141884A (en) * | 1990-08-18 | 1992-08-25 | Samsung Electronics Co., Ltd. | Isolation method of semiconductor device |
| KR930011288A (en) * | 1991-11-14 | 1993-06-24 | 문정환 | Manufacturing Method of LDD Transistor |
-
1995
- 1995-05-22 KR KR1019950012760A patent/KR100329748B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0284737A (en) * | 1988-09-21 | 1990-03-26 | Nec Corp | Manufacture of semiconductor device |
| JPH03184346A (en) * | 1989-12-13 | 1991-08-12 | Olympus Optical Co Ltd | Semiconductor device and manufacture thereof |
| JPH03188637A (en) * | 1989-12-18 | 1991-08-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR920003519A (en) * | 1990-07-13 | 1992-02-29 | 문정환 | Stacked Cell Manufacturing Method and Structure |
| US5141884A (en) * | 1990-08-18 | 1992-08-25 | Samsung Electronics Co., Ltd. | Isolation method of semiconductor device |
| KR930011288A (en) * | 1991-11-14 | 1993-06-24 | 문정환 | Manufacturing Method of LDD Transistor |
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| Publication number | Publication date |
|---|---|
| KR960043272A (en) | 1996-12-23 |
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