JPS59200418A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59200418A JPS59200418A JP7382083A JP7382083A JPS59200418A JP S59200418 A JPS59200418 A JP S59200418A JP 7382083 A JP7382083 A JP 7382083A JP 7382083 A JP7382083 A JP 7382083A JP S59200418 A JPS59200418 A JP S59200418A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor substrate
- metal film
- ions
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 238000000206 photolithography Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 230000009257 reactivity Effects 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
この発明は、半導体装置の製造方法に係り、特に半導体
基板上に、ＣＶＤ法により一金属膜を形成する工程を含
む半導体装置の製造方法に関する。[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a step of forming a metal film on a semiconductor substrate by a CVD method. .
近年、半導体集積回路の高集積化上ともに、高速化に対
する要求が増々強くなってきている。そのためにゲート
、あるいは配線材料に多結晶シリコンの代わりに、抵抗
の低い高融点金属を用いた半導体素子が開発され始めて
おり、この金属膜を半導体１番と形成するのに、スパッ
ター法、ＣＶＤ法等、多くの方法が行なわれている。In recent years, as semiconductor integrated circuits have become more highly integrated, the demand for higher speeds has become stronger and stronger. For this reason, semiconductor devices are being developed that use low-resistance, high-melting-point metals instead of polycrystalline silicon for gates or wiring materials, and sputtering, CVD, and other methods are used to form this metal film as the semiconductor. Many methods are being used.
従来、ＣＶＤ法により金属膜を基板上に形成する場合、
基板と導入気体との間の反応を利用して、金属膜を蒸着
するため、金属膜がある厚さまで形成されると、基板と
気体間の反応が阻止され、ある厚さ以上の金属膜の形成
が困難になり、できても非常に時間がかかる場合がある
。このような場合正こは、ある抵抗値以下の抵抗値を持
つ金属膜を得ることができず、希望している低抵抗の高
速素子ができない。Conventionally, when forming a metal film on a substrate using the CVD method,
The metal film is deposited using the reaction between the substrate and the introduced gas, so when the metal film is formed to a certain thickness, the reaction between the substrate and the gas is blocked, and the metal film over a certain thickness is They can be difficult to form and, if possible, can be very time consuming. In such a case, it is impossible to obtain a metal film having a resistance value below a certain resistance value, and the desired low-resistance, high-speed device cannot be obtained.
本発明は、上述した問題点を改善したもので、金属膜形
成前に、半導体基板にイオンを注入し、基板表面の結晶
構造を乱して、アモルファス状にして、基板と導入気体
との反応性を高めて、表面の結晶構造が回復し始める温
度以下の温度において、ＣＶＤ法により、より速く、厚
い金属膜を基板上に形成することを目的とする。The present invention improves the above-mentioned problems by implanting ions into a semiconductor substrate before forming a metal film, disrupting the crystal structure of the substrate surface, making it amorphous, and causing a reaction between the substrate and the introduced gas. The purpose of this invention is to form a thick metal film on a substrate more quickly by CVD at a temperature below the temperature at which the surface crystal structure begins to recover.
本発明は、半導体基板上に絶縁保護膜を形成し。 The present invention forms an insulating protective film on a semiconductor substrate.
該絶縁膜を写真蝕刻法によりパターニングして半導体基
板の一部を露呈させた構造に対して、基板上に金属膜を
ＣＶＤ法により形成する方法を提供するものである。The present invention provides a method for forming a metal film on a substrate by CVD for a structure in which a part of the semiconductor substrate is exposed by patterning the insulating film by photolithography.
具体的には、上記の構造に対して、基板の一部あるいは
全面にイオンを注入して、表面の結晶構造を乱して、反
応活性なアモルファス状にする。Specifically, with respect to the above structure, ions are implanted into a part or the entire surface of the substrate to disturb the crystal structure on the surface and make it reactively amorphous.
この後、熱処理工程を入れず、基板表面をアモルファス
状態のまま、６００℃以下の温度において、ＣＶＤ法を
用いて、露呈している半導体基板上に金属膜を速く、厚
く形成する。Thereafter, a metal film is rapidly and thickly formed on the exposed semiconductor substrate using the CVD method at a temperature of 600° C. or less without performing a heat treatment step and leaving the substrate surface in an amorphous state.
すなわち、イオン注入により、基板表面をアモルファス
にして、ＣＶＤ法で金属膜を形成する際、表面と導入ガ
スとの反応を促進させることを特徴とする。That is, the substrate surface is made amorphous by ion implantation, and when a metal film is formed by the CVD method, the reaction between the surface and the introduced gas is promoted.
本発明によれば、半導体基板−Ｅに、迅速に金属膜を厚
く形成することができ、低抵抗のゲート、配線を用いた
高速度素子を作ることができる。According to the present invention, a thick metal film can be quickly formed on the semiconductor substrate -E, and a high-speed element using low-resistance gates and wiring can be manufactured.
以下、本発明を適用した実施例につき、図面を用いなが
ら、詳細に説明する。Embodiments to which the present invention is applied will be described in detail below with reference to the drawings.
第り図に、シリコン基板上にＷをＣＶＤ法により形成し
た場合の蒸着時間と蒸着したＷのシート抵抗の関係を示
す。（ａ）図はイオン注入の無かった場合、（ｂ）図は
イオン注入した場であり、蒸着条件は、反応ガスとして
、’ ＷＦ６を用い、温度４５０℃。FIG. 2 shows the relationship between the deposition time and the sheet resistance of the deposited W when W is formed on a silicon substrate by the CVD method. The figure (a) shows the case without ion implantation, and the figure (b) shows the case where ions were implanted.The vapor deposition conditions were: WF6 was used as the reaction gas, and the temperature was 450°C.
ＷＦ、流量５ｃｃ １キヤリアガスとしてＡｔ を１Ｏ
ｃｃ流した。この図からも明らかなように、蒸着したＷ
のシート抵抗は、蒸着時間とともに減少するが、ある程
度時間がたつと、反応が飽和して、抵抗値も下がらなく
なる。しかし、Ａｓ イオンを４０ｋｅＶで３ＸｌＯ
”ｆｆ１−打ち込んだ後にＷを蒸着すると、飽和する抵
抗値もより小さくなることがわかる。すなわち、蒸着し
たＷ層が、より厚くなっている。WF, flow rate 5cc, At 1O as 1 carrier gas
I streamed cc. As is clear from this figure, the evaporated W
The sheet resistance decreases with deposition time, but after a certain amount of time, the reaction becomes saturated and the resistance value no longer decreases. However, As ion is 3XlO at 40keV
It can be seen that when W is deposited after ff1-implantation, the saturated resistance value also becomes smaller. That is, the deposited W layer becomes thicker.
第２図は、本発明の一実施例として、ＭＯ８）ランジス
タの製造方法を示す工程断面図である。FIG. 2 is a process sectional view showing a method of manufacturing a MO8) transistor as an embodiment of the present invention.
すなわち、６〜８ΩのＰ屋シリコン基板ｌにＬＯＣＯ８
工程にしたがって熱酸化により、フィールド酸化膜２を
形成し、写真蝕刻法により、素子領域をつくる。再び、
１０００℃、０．中で熱酸化して、厚さ４００Ａのゲー
ト酸化膜３を形成し、その上にさらにＬＰＣＶＤ法によ
り３０００Ａの多結晶シリコン膜４を形成したのち、写
真蝕刻法によって、多結晶シリコンゲート電極、および
ゲート酸化膜を素子領域に形成する（１ｇ２図（ａ））
。この構造のままＡｓ＋を加速型ＢＥ ４０ｋｅＶ テ
、５ Ｘ １０”ｅ−”注入したノチ、１ｏｏｏ”ｃで
３０分熱処理を行ない、 Ａｓを活性化させて、ｎ一層
を形成する。さらＪ（５ｉｏｔｙｉｘｔ ｃ Ｖ Ｄ
法ｉｃ ヨ１，１ 形成した後、反応性イオンエツチン
グによりゲート側壁に８１０１膜を残す（第２図（ｂ）
）。この構造のまま、再びＡｓ を、今度は４０ｋｅ
Ｖ テ３．５ＸＩＯ”ｆｆｉ″注入し１そのままｔ弗化
タングステンガスによるＣＶＤ法により、ソース・ドレ
イン上、およびゲート上にＷ膜７を選択的に形成する（
第２図（Ｃ））。この上に、プラズマＣＶＤにより８ｉ
０．膜８をかぶせて、６００℃で熱処理した後、コンタ
クトホールをあけて、アルミ配線９をする（第２図（ｄ
））。以上でＭＯＳＦＥＴが完成するが、このトランジ
スタは、ゲート電極、およびソース・ドレイン領域上に
ｗ膜７を形成しているため、低抵抗の高速の動作性を有
する。In other words, LOCO8 is applied to Pya silicon substrate l of 6 to 8Ω.
According to the process, a field oxide film 2 is formed by thermal oxidation, and an element region is formed by photolithography. again,
1000℃, 0. A gate oxide film 3 with a thickness of 400 A is formed by thermal oxidation in the inside, and a polycrystalline silicon film 4 with a thickness of 3000 A is further formed thereon by LPCVD, and then a polycrystalline silicon gate electrode and a Forming a gate oxide film in the element area (Figure 1g2 (a))
. With this structure, heat treatment is performed for 30 minutes at 100"C with accelerated BE of 40keV Te, 5 x 10"e-" implanted, to activate As and form a single layer of n. c V D
After forming the 8101 film on the gate sidewalls by reactive ion etching (Figure 2(b))
). Keeping this structure, As again, this time 40ke
After implanting VTE3.5
Figure 2 (C)). On top of this, 8i
0. After covering with a film 8 and heat-treating at 600°C, a contact hole is made and an aluminum wiring 9 is placed (see Fig. 2 (d).
)). The MOSFET is thus completed, and since the W film 7 is formed on the gate electrode and source/drain regions, this transistor has low resistance and high speed operation.
以上、本発明の一実施例として、ＭＯＳＦＥＴへの応用
を示したが、金属膜をＣＶＤ法によって、基板上に形成
する工程を含む半導体装置であれば、広範囲に本発明を
適用することができる。また、上記例では、高融点金属
のＷを形成したが、これは、ＭＯでもＡ／でも金属膜を
ＣＶＤ法にＩり形成するのであれば差しつかえなく適用
できる。Although the application of the present invention to a MOSFET has been described above as an example, the present invention can be widely applied to any semiconductor device that includes a step of forming a metal film on a substrate by CVD. . Further, in the above example, W, which is a high-melting point metal, is formed, but this can be applied without any problem if a metal film is formed using the CVD method, whether MO or A/.
第１図は、本発明による製造方法により形成したｗｇの
シート抵抗値と蒸着時間との関係を、従来方法の場合と
比較して示す特性図、第２図は、本発明の一実施例とし
てＭＯＳＦＥＴの製造工程を示す工程断面図である。
ｌ・・・Ｐ型シリコン基板 ２・・・フィールド酸化膜
３・・・ゲート酸化膜
４・・・多結晶シリコンゲート電極
５・・・側壁ｓｉｏ、 ６・・・ｎ″″拡散層
７・・・タングステン層 ８・・・酸化膜９・・・ＡＩ
！配線 １ｏ・・・ｎ拡散層（７３１７） 弁
理士 則 近 憲 佑 （はが１名）第 １ 図
第２図
ｆＤ ムFIG. 1 is a characteristic diagram showing the relationship between the sheet resistance value and deposition time of WG formed by the manufacturing method of the present invention in comparison with that of the conventional method. FIG. It is a process cross-sectional view showing the manufacturing process of MOSFET. l...P-type silicon substrate 2...field oxide film 3...gate oxide film 4...polycrystalline silicon gate electrode 5...side wall sio, 6...n'''' diffusion layer 7...・Tungsten layer 8...Oxide film 9...AI
! Wiring 1o...n diffusion layer (7317) Patent attorney Noriyuki Chika (1 person) Fig. 1 Fig. 2 fD Mu
Claims (1)
刻法によりパターニングして半導体基板の一部を露呈さ
せた構造に対して、基板の一部あるいは全面にイオンを
注入し、６００℃を越えた温度下の熱工程を経ることな
しに、６００℃以下の温度において化学気相成長法によ
り、半導体基板上の一部あるいは全面に金属膜を形成す
ることを特徴とする半導体装置の製造方法。For a structure in which an insulating protective film is formed on a semiconductor substrate and the insulating film is patterned by photolithography to expose a part of the semiconductor substrate, ions are implanted into a part or the entire surface of the substrate and heated at 600°C. Manufacturing of a semiconductor device characterized in that a metal film is formed on a part or the entire surface of a semiconductor substrate by chemical vapor deposition at a temperature of 600°C or less without undergoing a thermal process at a temperature exceeding 600°C. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7382083A JPS59200418A (en) | 1983-04-28 | 1983-04-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7382083A JPS59200418A (en) | 1983-04-28 | 1983-04-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59200418A true JPS59200418A (en) | 1984-11-13 |
Family
ID=13529168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7382083A Pending JPS59200418A (en) | 1983-04-28 | 1983-04-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59200418A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482620A (en) * | 1987-09-25 | 1989-03-28 | Toshiba Corp | Manufacture of semiconductor device |
| US4855247A (en) * | 1988-01-19 | 1989-08-08 | Standard Microsystems Corporation | Process for fabricating self-aligned silicide lightly doped drain MOS devices |
| US5028554A (en) * | 1986-07-03 | 1991-07-02 | Oki Electric Industry Co., Ltd. | Process of fabricating an MIS FET |
| US5059555A (en) * | 1990-08-20 | 1991-10-22 | National Semiconductor Corporation | Method to fabricate vertical fuse devices and Schottky diodes using thin sacrificial layer |
| US5215936A (en) * | 1986-10-09 | 1993-06-01 | Kabushiki Kaisha Toshiba | Method of fabricating a semiconductor device having a lightly-doped drain structure |
| US5429958A (en) * | 1986-01-15 | 1995-07-04 | Harris Corporation | Process for forming twin well CMOS integrated circuits |
| JP2012089807A (en) * | 2010-10-22 | 2012-05-10 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
-
1983
- 1983-04-28 JP JP7382083A patent/JPS59200418A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5429958A (en) * | 1986-01-15 | 1995-07-04 | Harris Corporation | Process for forming twin well CMOS integrated circuits |
| US5028554A (en) * | 1986-07-03 | 1991-07-02 | Oki Electric Industry Co., Ltd. | Process of fabricating an MIS FET |
| US5215936A (en) * | 1986-10-09 | 1993-06-01 | Kabushiki Kaisha Toshiba | Method of fabricating a semiconductor device having a lightly-doped drain structure |
| JPS6482620A (en) * | 1987-09-25 | 1989-03-28 | Toshiba Corp | Manufacture of semiconductor device |
| US4855247A (en) * | 1988-01-19 | 1989-08-08 | Standard Microsystems Corporation | Process for fabricating self-aligned silicide lightly doped drain MOS devices |
| US5059555A (en) * | 1990-08-20 | 1991-10-22 | National Semiconductor Corporation | Method to fabricate vertical fuse devices and Schottky diodes using thin sacrificial layer |
| JP2012089807A (en) * | 2010-10-22 | 2012-05-10 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
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