JPH04266031A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04266031A JPH04266031A JP2629891A JP2629891A JPH04266031A JP H04266031 A JPH04266031 A JP H04266031A JP 2629891 A JP2629891 A JP 2629891A JP 2629891 A JP2629891 A JP 2629891A JP H04266031 A JPH04266031 A JP H04266031A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal silicide
- oxide film
- oxidation
- electrode wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 29
- 230000003647 oxidation Effects 0.000 claims abstract description 28
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 79
- 238000000034 method Methods 0.000 description 13
- 239000012535 impurity Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 5
- 229910008814 WSi2 Inorganic materials 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、金属シリサイドを用い
た電極配線を持つ半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having electrode wiring using metal silicide.
【０００２】0002
【従来の技術】従来より、集積回路等の各種半導体装置
の電極配線として多結晶シリコンが広く用いられている
。しかし、多結晶シリコンは不純物をドープしても、金
属配線に比べて抵抗が高い。したがって集積回路の高集
積化，高速化が進むにしたがって、電極配線での信号遅
延が問題になっている。特にＭＯＳ型集積回路では、通
常ＭＯＳトランジスタのゲート電極がそのまま第１層配
線として用いられるので、ここでの抵抗は素子の高速動
作の障害となる。多結晶シリコンに代る耐熱性の低抵抗
電極配線材料として、高融点金属のシリサイドが注目さ
れている。図３および図４は、ゲート電極配線にタング
ステン・シリサイド（ＷＳｉｘ ）膜を用いた従来のＬ
ＤＤ構造ＭＯＳ型半導体装置の製造工程を示している。2. Description of the Related Art Conventionally, polycrystalline silicon has been widely used as electrode wiring for various semiconductor devices such as integrated circuits. However, even when doped with impurities, polycrystalline silicon has higher resistance than metal wiring. Therefore, as integrated circuits become more highly integrated and faster, signal delays in electrode wiring become a problem. Particularly in MOS type integrated circuits, the gate electrode of the MOS transistor is usually used as the first layer wiring, so the resistance here becomes an obstacle to high-speed operation of the device. Refractory metal silicide is attracting attention as a heat-resistant, low-resistance electrode wiring material that can replace polycrystalline silicon. Figures 3 and 4 show a conventional L
The manufacturing process of a DD structure MOS type semiconductor device is shown.
【０００３】図３（ａ） に示すように、シリコン基板
１１に素子分離酸化膜１２を形成した後、熱酸化によっ
て５〜２０ｎｍ程度の薄いゲート酸化膜１３を形成する
。次に図３（ｂ） に示すように、ＣＶＤ法によって１
００ｎｍ程度の多結晶シリコン膜１４を堆積し、続いて
スパッタリングによって３００ｎｍ程度のＷＳｉｘ 膜
１５を形成する。
そして通常のフォトリソグラフィによってこれらのＷＳ
ｉｘ 膜１５と多結晶シリコン膜１４をパターニングし
て、図３（ｃ） に示すようにゲート電極配線１６を形
成する。As shown in FIG. 3A, after forming an element isolation oxide film 12 on a silicon substrate 11, a thin gate oxide film 13 of about 5 to 20 nm is formed by thermal oxidation. Next, as shown in Figure 3(b), 1
A polycrystalline silicon film 14 of about 300 nm thick is deposited, and then a WSix film 15 of about 300 nm thick is formed by sputtering. Then, these WS are formed by normal photolithography.
The ix film 15 and the polycrystalline silicon film 14 are patterned to form a gate electrode wiring 16 as shown in FIG. 3(c).
【０００４】その後、ゲート電極をマスクとして不純物
のイオン注入を行って、図３（ｄ） に示すように低濃
度の浅いソース，ドレイン拡散層１８，１９を形成する
。このとき、不純物活性化のためのイオン注入後の酸化
性雰囲気での熱処理によって、ゲート電極配線１６の表
面には２０〜３０ｎｍの後酸化膜１７が形成される。ま
たこの熱処理工程で、当初アモルファス状態であったＷ
Ｓｉｘ 膜１５は結晶化され、ＷＳｉ２ なる成分が多
くなる。[0004] Thereafter, impurity ions are implanted using the gate electrode as a mask to form low concentration shallow source and drain diffusion layers 18 and 19 as shown in FIG. 3(d). At this time, a post-oxide film 17 with a thickness of 20 to 30 nm is formed on the surface of the gate electrode wiring 16 by heat treatment in an oxidizing atmosphere after ion implantation for impurity activation. In addition, during this heat treatment process, W, which was initially in an amorphous state,
The Six film 15 is crystallized and the WSi2 component increases.
【０００５】その後、ＬＤＤ構造を形成するために、Ｃ
ＶＤ法によってシリコン酸化膜２０を堆積しこれをエッ
チングして、図４（ａ） に示すようにゲート電極側壁
に酸化膜２０を残す。このとき、ＷＳｉｘ 膜１５の上
面は露出する。その後、ゲート電極１６と酸化膜２０を
マスクとして不純物のイオン注入を行って、高濃度のソ
ース，ドレイン拡散層を形成する。[0005] Then, in order to form an LDD structure, C
A silicon oxide film 20 is deposited by the VD method and etched to leave the oxide film 20 on the side walls of the gate electrode as shown in FIG. 4(a). At this time, the upper surface of the WSix film 15 is exposed. Thereafter, impurity ions are implanted using the gate electrode 16 and the oxide film 20 as masks to form highly concentrated source and drain diffusion layers.
【０００６】この様な一連の工程に於いて、２回目の不
純物イオン注入工程に先立って、基板表面に薄く熱酸化
膜を形成する工程が入る。これは、ＣＭＯＳ構造の場合
には、ｐチャネル領域とｎチャネル領域のイオン注入の
打ち分けを行うが、その際、マスクとして用いるフォト
レジストが基板に直接接触するのを防止する必要がある
こと、また後の不純物活性化の際の不純物の外方拡散を
防止する必要があること、等の理由による。ところが、
この不純物イオン注入工程に先立つ酸化熱処理工程で、
ＷＳｉｘ 膜１５が深く酸化され、図４（ｂ） に示す
ように異常酸化膜３０が形成される。この異常酸化膜３
０は、ＳｉＯ２ とＷＯ３ からなるもので、体積膨脹
は約２．７倍に達する。この異常酸化膜３０によってゲ
ート電極配線の抵抗は大幅に増大し、またしばしば膜が
剥がれる、といった問題が生じる。In this series of steps, a step of forming a thin thermal oxide film on the substrate surface is performed prior to the second impurity ion implantation step. This is because in the case of a CMOS structure, ion implantation is performed separately for the p-channel region and the n-channel region, but at that time, it is necessary to prevent the photoresist used as a mask from coming into direct contact with the substrate. Another reason is that it is necessary to prevent outward diffusion of impurities during subsequent impurity activation. However,
In the oxidation heat treatment process that precedes this impurity ion implantation process,
The WSix film 15 is deeply oxidized, and an abnormal oxide film 30 is formed as shown in FIG. 4(b). This abnormal oxide film 3
0 is made of SiO2 and WO3, and the volume expansion reaches approximately 2.7 times. This abnormal oxide film 30 significantly increases the resistance of the gate electrode wiring, and often causes problems such as peeling of the film.
【０００７】このＷＳｉｘ 膜の異常酸化は、図３（ｄ
） に示す酸化膜１７の形成工程では生じない。したが
ってこの異常酸化は、ＷＳｉｘ が結晶化されているこ
とが前提となっている。本発明者等の検討によれば、こ
の現象は次のように理解される。ＷＳｉｘ 膜がアモル
ファス状態では、酸化性雰囲気に晒したときに、ＷＳｉ
ｘ 中のＳｉが主として酸化されて良質の酸化膜（Ｓｉ
Ｏ２）が形成され、これが表面を覆ってその後の酸化が
抑えられる。これに対して、ＷＳｉｘ 膜が結晶化され
てＷＳｉ２ 結晶粒が表面を覆っていると、酸化性雰囲
気に晒したとき酸化によるＳｉの消費に対してＳｉの供
給が不十分となり、Ｗが直接酸化される事態になるもの
と思われる。This abnormal oxidation of the WSix film is shown in FIG.
) does not occur in the process of forming the oxide film 17 shown in FIG. Therefore, this abnormal oxidation is based on the premise that WSix is crystallized. According to the studies of the present inventors, this phenomenon can be understood as follows. When the WSix film is in an amorphous state, when exposed to an oxidizing atmosphere, the WSi
The Si in x is mainly oxidized to form a high quality oxide film (Si
O2) is formed, which covers the surface and suppresses subsequent oxidation. On the other hand, if the WSix film is crystallized and the surface is covered with WSi2 crystal grains, when exposed to an oxidizing atmosphere, the supply of Si will be insufficient for the consumption of Si by oxidation, and W will be directly oxidized. It seems likely that this will happen.
【０００８】[0008]
【発明が解決しようとする課題】以上のように、従来の
金属シリサイド膜電極配線を用いた半導体装置の製造方
法では、シリサイド膜が複数回の酸化熱処理工程の後に
異常酸化膜が形成され、電極配線の信頼性が確保できな
いという問題があった。本発明は、この様な点に鑑みな
されたもので、信頼性の高い金属シリサイド電極配線を
持つ半導体装置の製造方法を提供することを目的とする
。[Problems to be Solved by the Invention] As described above, in the conventional manufacturing method of semiconductor devices using metal silicide film electrode wiring, an abnormal oxide film is formed on the silicide film after multiple oxidation heat treatment steps, and the electrode There was a problem in that the reliability of the wiring could not be ensured. The present invention has been made in view of these points, and an object of the present invention is to provide a method for manufacturing a semiconductor device having highly reliable metal silicide electrode wiring.
【０００９】[0009]
【課題を解決するための手段】本発明は、半導体基板上
に金属シリサイド膜からなる電極配線を形成し、第１の
酸化熱処理により金属シリサイド膜表面に酸化膜を形成
した後、金属シリサイド膜表面の酸化膜を一旦除去し、
第２の酸化熱処理を行う場合に、第２の熱酸化処理に先
立って露出している金属シリサイド膜表面をシリコン膜
で覆い、第２の酸化熱処理ではこのシリコン膜を酸化膜
に変換するようにしたことを特徴としている。[Means for Solving the Problems] The present invention involves forming an electrode wiring made of a metal silicide film on a semiconductor substrate, forming an oxide film on the surface of the metal silicide film by a first oxidation heat treatment, and then forming an oxide film on the surface of the metal silicide film. Once the oxide film of
When performing the second oxidation heat treatment, the exposed surface of the metal silicide film is covered with a silicon film prior to the second thermal oxidation treatment, and this silicon film is converted into an oxide film in the second oxidation heat treatment. It is characterized by what it did.
【００１０】0010
【作用】本発明によれば、結晶化した金属シリサイド膜
表面がシリコン膜で覆われた状態で酸化熱処理が行われ
、良質のシリコン酸化膜が形成されて金属シリサイド膜
が保護される。すなわち金属シリサイド膜自身の酸化は
防止され、従来のような異常酸化による電極配線の抵抗
増大や剥がれが生じることはなくなる。とくにシリコン
膜としてアモルファス・シリコン膜を用いると、膜堆積
時に結晶粒界が形成されることがなく、酸化開始温度が
低くまた酸化速度も大きいことから、安定でバリア性の
高い酸化膜が形成されて金属シリサイド膜自身の異常酸
化が確実に防止される。According to the present invention, oxidation heat treatment is performed with the surface of the crystallized metal silicide film covered with a silicon film, and a high quality silicon oxide film is formed to protect the metal silicide film. That is, the metal silicide film itself is prevented from being oxidized, and the increase in resistance and peeling of the electrode wiring due to abnormal oxidation, which occurs in the prior art, is no longer caused. In particular, when an amorphous silicon film is used as the silicon film, grain boundaries are not formed during film deposition, the oxidation initiation temperature is low, and the oxidation rate is high, so a stable oxide film with high barrier properties can be formed. Thus, abnormal oxidation of the metal silicide film itself is reliably prevented.
【００１１】[0011]
【実施例】以下、図面を参照しながら実施例を説明する
。図１（ａ） 〜（ｄ） および図２（ａ） 〜（ｃ）
は、本発明の一実施例に係るＭＯＳ型半導体装置の製
造工程を示す断面図である。Embodiments Hereinafter, embodiments will be described with reference to the drawings. Figures 1(a) to (d) and Figures 2(a) to (c)
1A and 1B are cross-sectional views showing a manufacturing process of a MOS type semiconductor device according to an embodiment of the present invention.
【００１２】図１（ａ） に示すように、例えば比抵抗
６Ω・ｃｍのｐ型シリコン基板１１に、通常の工程にし
たがって素子分離酸化膜１２を形成した後、熱酸化によ
って５〜２０ｎｍの薄いゲート酸化膜１３を形成する。
次に図１（ｂ） に示すように、ＬＰＣＶＤ法によって
１００ｎｍ程度の多結晶シリコン膜１４を堆積する。堆
積した多結晶シリコン膜１４には、Ａｓ等の不純物を例
えば、ドーズ量１〜５×１０１５／ｃｍ２で注入する。
続いて、スパッタリングによって３００ｎｍ程度のＷＳ
ｉｘ膜１５を形成する。このスパッタリングはたとえば
、ＷＳｉ２．７ の合金ターゲットを用いた、Ａｒガス
中でのＤＣマグネトロンスパッタによる。堆積後の膜は
Ｘ線回折によると非晶質であることが確認された。As shown in FIG. 1(a), an element isolation oxide film 12 is formed on a p-type silicon substrate 11 having a resistivity of 6 Ω·cm, for example, according to a normal process, and then a thin film of 5 to 20 nm is formed by thermal oxidation. A gate oxide film 13 is formed. Next, as shown in FIG. 1(b), a polycrystalline silicon film 14 of about 100 nm is deposited by the LPCVD method. An impurity such as As is implanted into the deposited polycrystalline silicon film 14 at a dose of, for example, 1 to 5×10 15 /cm 2 . Next, WS of about 300 nm was formed by sputtering.
ix film 15 is formed. This sputtering is, for example, by DC magnetron sputtering in Ar gas using a WSi2.7 alloy target. The deposited film was confirmed to be amorphous by X-ray diffraction.
【００１３】そして通常のフォトリソグラフィと反応性
イオンエッチングによって、ＷＳｉｘ 膜１５と多結晶
シリコン１４の積層膜をパターニングして、図１（ｃ）
に示すようにゲート電極配線１６を形成する。Then, the laminated film of the WSix film 15 and the polycrystalline silicon 14 is patterned by ordinary photolithography and reactive ion etching to form the structure shown in FIG. 1(c).
A gate electrode wiring 16 is formed as shown in FIG.
【００１４】その後、例えばリンを加速電圧４０ｋｅＶ
，ドーズ量５×１０１３／ｃｍ２ の条件でイオン注入
し、酸化熱処理によって、図１（ｄ） に示すように低
濃度の浅いソース，ドレイン拡散層１８，１９を形成す
る。この酸化熱処理は例えば、９００℃の乾燥酸素中で
行う。これにより、ゲート電極配線１６の表面には１０
〜３０ｎｍの後酸化膜１７が形成される。またこの熱処
理工程で、ＷＳｉｘ 膜１５は正方晶の結晶（ＷＳｉ２
）として結晶化される。After that, for example, phosphorus is accelerated at a voltage of 40 keV.
, and a dose of 5.times.10.sup.13/cm.sup.2, followed by oxidation heat treatment to form shallow, low concentration source and drain diffusion layers 18 and 19, as shown in FIG. 1(d). This oxidation heat treatment is performed, for example, in dry oxygen at 900°C. As a result, the surface of the gate electrode wiring 16 has 10
A post-oxide film 17 of ~30 nm is formed. In addition, in this heat treatment process, the WSix film 15 is formed into a tetragonal crystal (WSi2
) is crystallized as
【００１５】その後、ＬＤＤ構造を形成するために、Ｃ
ＶＤ法によってシリコン酸化膜２０を１５０ｎｍ程度堆
積し、これを反応性イオンエッチングによってエッチン
グして、図２（ａ） に示すようにゲート電極側壁に酸
化膜２０を残す。このとき、ＷＳｉｘ 膜１５の上面は
露出する。[0015] After that, in order to form an LDD structure, C
A silicon oxide film 20 is deposited to a thickness of about 150 nm using the VD method, and this is etched using reactive ion etching to leave the oxide film 20 on the side walls of the gate electrode as shown in FIG. 2(a). At this time, the upper surface of the WSix film 15 is exposed.
【００１６】次いで、図２（ｂ） に示すように、ＬＰ
ＣＶＤ法によって約５ｎｍのアモルファス・シリコン膜
２１を堆積する。堆積条件は例えば、基板温度を５５０
℃に保ち、ＳｉＨ４ ガスを１００ＳＣＣＭ導入し、０
．５Ｔｏｒｒ〜１Ｔｏｒｒの真空度で行なう。このとき
堆積速度は、約４ｎｍ／ｍｉｎ である。Next, as shown in FIG. 2(b), the LP
An amorphous silicon film 21 of about 5 nm is deposited by CVD. For example, the deposition conditions include a substrate temperature of 550°C.
℃, introduced 100 SCCM of SiH4 gas, and
．． The vacuum level is 5 Torr to 1 Torr. At this time, the deposition rate is about 4 nm/min.
【００１７】その後、酸化熱処理によって、シリコン膜
２１をすべて酸化して、図２（ｃ） に示すようにＷＳ
ｉｘ 膜表面には約１５ｎｍの後酸化膜２４を形成する
。酸化膜２０の側壁残しの工程でソース，ドレイン領域
の基板表面が露出している場合も、ここがシリコン膜２
１で覆われ、これが酸化膜に変換される。この酸化熱処
理の条件は例えば、乾燥酸素中で９００℃，１５分であ
る。そして最後にＡｓ等をイオン注入し活性化熱処理を
行なって、高濃度のソース，ドレイン拡散層２２，２３
を形成する。Ａｓのイオン注入条件は例えば、加速電圧
４０ｋｅＶ，ドーズ量５×１０１５／ｃｍ２ とする。
この実施例によれば、ＷＳｉｘ 膜の異常酸化が生じる
ことはなく、信頼性の高い電極配線が得られる。Thereafter, the silicon film 21 is completely oxidized by oxidation heat treatment to form a WS as shown in FIG. 2(c).
A post-oxidation film 24 of about 15 nm is formed on the surface of the ix film. Even if the substrate surface of the source and drain regions is exposed in the process of leaving the sidewalls of the oxide film 20, this is the silicon film 2.
1, which is converted into an oxide film. The conditions for this oxidation heat treatment are, for example, 900° C. for 15 minutes in dry oxygen. Finally, As or the like is ion-implanted and an activation heat treatment is performed to form highly concentrated source and drain diffusion layers 22, 23.
form. The As ion implantation conditions are, for example, an acceleration voltage of 40 keV and a dose of 5×10 15 /cm 2 . According to this example, abnormal oxidation of the WSix film does not occur, and highly reliable electrode wiring can be obtained.
【００１８】本発明は上記実施例に限られるものではな
い。実施例では、ＬＤＤ構造のＭＯＳ型半導体装置を製
造する場合を説明したが、金属シリサイド膜形成工程と
、それが結晶化された後に酸化処理工程が入る他のあら
ゆる半導体装置の製造に適用して同様の効果が得られる
。また実施例では、Ｗのシリサイドを用いたが、その他
、Ｔｉ ，Ｚｒ ，Ｈｆ ，Ｖ，Ｎｂ ，Ｔａ ，Ｃｒ
，Ｍｏ ，Ｃｏ ，Ｎｉ ，Ｒｈ ，Ｐｄ，Ｉｒ ，
Ｐｔ 等のシリサイドを用いて電極配線を形成する場合
も同様に本発明を適用することができる。The present invention is not limited to the above embodiments. In the embodiment, a case was explained in which a MOS type semiconductor device with an LDD structure was manufactured. However, the present invention can also be applied to the manufacturing of any other semiconductor device in which a metal silicide film formation process and an oxidation treatment process are performed after the metal silicide film is crystallized. A similar effect can be obtained. Further, in the example, W silicide was used, but other materials include Ti, Zr, Hf, V, Nb, Ta, Cr.
, Mo, Co, Ni, Rh, Pd, Ir,
The present invention can be similarly applied to the case where electrode wiring is formed using silicide such as Pt.
【００１９】[0019]
【発明の効果】以上説明したように本発明によれば、金
属シリサイドを電極配線に用いる場合に、結晶化した後
に露出した金属シリサイド膜表面をシリコン膜で覆って
酸化熱処理を行なうことによって、金属シリサイドの異
常酸化を防止して、信頼性の高い電極配線を持つ半導体
装置を製造することができる。As explained above, according to the present invention, when metal silicide is used for electrode wiring, the surface of the metal silicide film exposed after crystallization is covered with a silicon film and subjected to oxidation heat treatment, thereby making it possible to Abnormal oxidation of silicide can be prevented, and a semiconductor device with highly reliable electrode wiring can be manufactured.
【図１】本発明の一実施例に係るＭＯＳ型半導体装置の
製造工程前半を示す断面図。FIG. 1 is a cross-sectional view showing the first half of the manufacturing process of a MOS type semiconductor device according to an embodiment of the present invention.
【図２】同実施例の製造工程後半を示す断面図。FIG. 2 is a sectional view showing the latter half of the manufacturing process of the same embodiment.
【図３】従来例のＭＯＳ型半導体装置の製造工程前半を
示す断面図。FIG. 3 is a cross-sectional view showing the first half of the manufacturing process of a conventional MOS type semiconductor device.
【図４】同従来例の製造工程後半を示す断面図。FIG. 4 is a sectional view showing the latter half of the manufacturing process of the conventional example.
１１…シリコン基板、１２…素子分離酸化膜、１３…ゲ
ート酸化膜、１４…多結晶シリコン膜、１５…ＷＳｉｘ
膜、１６…ゲート電極配線、１７…熱酸化膜、１８，
２２…ソース拡散層、１９，２３…ドレイン拡散層、２
０…ＣＶＤ酸化膜、２１…アモルファス・シリコン膜、
２４…熱酸化膜。11... Silicon substrate, 12... Element isolation oxide film, 13... Gate oxide film, 14... Polycrystalline silicon film, 15... WSix
Film, 16... Gate electrode wiring, 17... Thermal oxide film, 18,
22... Source diffusion layer, 19, 23... Drain diffusion layer, 2
0...CVD oxide film, 21...amorphous silicon film,
24...Thermal oxide film.
Claims (1)
電極配線を形成する工程と、第１の酸化熱処理により前
記金属シリサイド膜表面に酸化膜を形成する工程と、前
記金属シリサイド膜表面の酸化膜を除去する工程と、露
出した前記金属シリサイド膜表面にシリコン膜を堆積す
る工程と、第２の酸化熱処理により前記シリコン膜を酸
化膜に変換する工程と、を備えたことを特徴とする半導
体装置の製造方法。1. A step of forming an electrode wiring made of a metal silicide film on a semiconductor substrate, a step of forming an oxide film on the surface of the metal silicide film by a first oxidation heat treatment, and a step of forming an oxide film on the surface of the metal silicide film. a step of depositing a silicon film on the exposed surface of the metal silicide film; and a step of converting the silicon film into an oxide film by a second oxidation heat treatment. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2629891A JP2997554B2 (en) | 1991-02-20 | 1991-02-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2629891A JP2997554B2 (en) | 1991-02-20 | 1991-02-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04266031A true JPH04266031A (en) | 1992-09-22 |
| JP2997554B2 JP2997554B2 (en) | 2000-01-11 |
Family
ID=12189432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2629891A Expired - Fee Related JP2997554B2 (en) | 1991-02-20 | 1991-02-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2997554B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07283214A (en) * | 1994-04-04 | 1995-10-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US6017809A (en) * | 1996-12-11 | 2000-01-25 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| WO2000057463A1 (en) * | 1999-03-24 | 2000-09-28 | Tokyo Electron Limited | Heat treating method for thin film and forming method for thin film |
| JP2017022377A (en) * | 2015-07-14 | 2017-01-26 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
1991
- 1991-02-20 JP JP2629891A patent/JP2997554B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07283214A (en) * | 1994-04-04 | 1995-10-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US6017809A (en) * | 1996-12-11 | 2000-01-25 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| WO2000057463A1 (en) * | 1999-03-24 | 2000-09-28 | Tokyo Electron Limited | Heat treating method for thin film and forming method for thin film |
| US6448178B1 (en) | 1999-03-24 | 2002-09-10 | Tokyo Electron Limited | Heat treating method for thin film and forming method for thin film |
| JP2017022377A (en) * | 2015-07-14 | 2017-01-26 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US10763373B2 (en) | 2015-07-14 | 2020-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US11393930B2 (en) | 2015-07-14 | 2022-07-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2997554B2 (en) | 2000-01-11 |
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