JPS59121834A - Manufacture of electrode wiring - Google Patents
Manufacture of electrode wiringInfo
- Publication number
- JPS59121834A JPS59121834A JP22729482A JP22729482A JPS59121834A JP S59121834 A JPS59121834 A JP S59121834A JP 22729482 A JP22729482 A JP 22729482A JP 22729482 A JP22729482 A JP 22729482A JP S59121834 A JPS59121834 A JP S59121834A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- point metal
- electrode wiring
- high melting
- aperture part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000002844 melting Methods 0.000 claims abstract description 17
- 230000008018 melting Effects 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 238000007740 vapor deposition Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000011261 inert gas Substances 0.000 abstract description 2
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000007796 conventional method Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この究明は、十纏体装置における電極部［株］の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) This investigation relates to a method for manufacturing an electrode section in a ten-piece device.
（従来技術）
従来の半導体装置の電極配線製造方法について第１図を
参照して説明する。第１図（ａ）において、１はシリコ
ン基板、２はその表面にＣＶＤＫよって形成されたＰＳ
Ｇなどの絶縁被膜である。まず、この絶縁被膜２上に第
１図（ｂ）に示すようにレジスト３を（布し、このレジ
スト３には公知のホ） ＩＪソ技術によって窓４を形成
する。次に、懇４を有する前記レジスト３をマスクとし
てフッ酸系のエツチング液あるいはイオンエツチング技
術によって′７ｅ縁被族２をエツチングする。これによ
り、第１図（ｃ）に示すように、絶縁被膜２に前記レジ
スト３の窓４に対応して開口部５を形成する。しかる後
、第１図（ｄ）に示すようにレジスト３を除去する。(Prior Art) A conventional method for manufacturing electrode wiring for a semiconductor device will be described with reference to FIG. In FIG. 1(a), 1 is a silicon substrate, 2 is a PS formed on its surface by CVDK.
It is an insulating coating such as G. First, as shown in FIG. 1(b), a resist 3 is coated on the insulating film 2, and a window 4 is formed on this resist 3 by a known IJ technique. Next, the '7e edge group 2 is etched using a hydrofluoric acid etching solution or ion etching technique using the resist 3 having the oxide layer 4 as a mask. Thereby, as shown in FIG. 1(c), openings 5 are formed in the insulating film 2 in correspondence with the windows 4 of the resist 3. Thereafter, the resist 3 is removed as shown in FIG. 1(d).
その後、開口部５および絶線被膜２上に第１図（ｅ）に
示すように電極配線用金属６を蒸着あるいはスパッタリ
ングによって付着する。Thereafter, as shown in FIG. 1(e), an electrode wiring metal 6 is deposited on the opening 5 and the insulation film 2 by vapor deposition or sputtering.
しかるに、このような従来の方法では、開口部５の上端
で電極配線用金属６の仮積性が悪くなシ、対応する部分
７で電極配線用金属６が薄くなる。However, in such a conventional method, the metal for electrode wiring 6 does not have a poor temporary stacking property at the upper end of the opening 5, and the metal for electrode wiring 6 becomes thin at the corresponding portion 7.
さらに甚だしい場合は、この部分７で１！極配線用金属
６が断線に至るもので、また前述のように薄くなった場
合も後の半導体装置の通電試験で断線に至ることがある
。In even more severe cases, this part 7 is 1! The electrode wiring metal 6 may lead to wire breakage, and even if it becomes thin as described above, it may lead to wire breakage during a later conduction test of the semiconductor device.
この絶縁被膜の開口部での電極配線用金属の被覆性を改
善するために第２図に示すようガ製造方法を用いるのが
一般的である。この製造方法において、第２図（ａ）な
いしくｄ）に示す工程は、先の製造方法の第１図（ａ）
ないしくｄ）に示す工程と同一である。In order to improve the coverage of the electrode wiring metal at the opening of the insulating film, it is common to use a method of manufacturing the metal as shown in FIG. In this manufacturing method, the steps shown in FIGS. 2(a) to d) are similar to those shown in FIG. 1(a) of the previous manufacturing method.
This step is the same as step d).
この同一工程によシ開ロ部５を得てレノスト３を除去し
た後、この第２図に示す方法では、１０００℃前後の温
度およびＮ２などの不活性がス雰囲、気中で２０〜３０
分処理する。これにより、第２図（ｅ）に示すように、
開口部５の上端部は緩やかな形状になる。したがって、
次に第２図（ｆ）に示すように′醒億配線用金属６を形
成するが、第１図（ｅ）のような被覆性が悪い状態はな
く、被覆性は改善される。After obtaining the open bottom part 5 by this same process and removing the renost 3, in the method shown in FIG. 30
Process in minutes. As a result, as shown in FIG. 2(e),
The upper end of the opening 5 has a gentle shape. therefore,
Next, as shown in FIG. 2(f), the metal 6 for the interconnection is formed, but the coverage is improved, without the poor coverage as shown in FIG. 1(e).
しかるに、この方法では、１０００℃前後の高温で熱処
理して開口部５を緩やかな形状にするもの −であるか
ら、その時、絶縁被膜２であるＰＳＧよシＰ（燐）が析
出し、開口部５のシリコン基板ＩＫ拡散する。一般にＮ
チャネル型ＭＯ８ならば、ソース・ドレインの拡散層が
Ｎ型であるから、Ｐ（燐）が拡散しても問題はないが、
Ｐチャネル型ＭＯＳの場合は、ソース・ドレインの拡散
層がＰ型であるため、析出したＰ（燐）がこのＰ型の拡
散層に拡散すると抵抗を犬さくしたり、あるいはＰ型拡
散層を反転してＮ型化してしまい、トランジスタ特性を
損ねてしまう。However, in this method, the opening 5 is made into a gentle shape by heat treatment at a high temperature of around 1000°C. 5. Diffuse the silicon substrate IK. Generally N
If it is a channel type MO8, the source/drain diffusion layers are N type, so there is no problem even if P (phosphorus) is diffused.
In the case of a P-channel type MOS, the source/drain diffusion layer is P-type, so if precipitated P (phosphorus) diffuses into this P-type diffusion layer, it will increase the resistance or reverse the P-type diffusion layer. This causes the transistor to become N-type, impairing the transistor characteristics.
（発明の目的）
この発明は上記の点に鑑みなされたもので、素子の特性
を撰なうことなく電極配線の被覆性を改善することがで
きる電極配線の製造方法を提供することを目的とする。(Objective of the Invention) The present invention was made in view of the above points, and an object of the present invention is to provide a method for manufacturing an electrode wiring that can improve the coverage of the electrode wiring without changing the characteristics of the element. do.
（実施例） 以下この発明の一実施例を第３図を診照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
この発明の一実施例では、開口部５をエツチングによシ
形成するまで第１図の従来の方法と同一工程をとる。こ
の同一工程を第３図（ａ）ないしくｃ） Ｋ示してお勺
、図中第１図（ａ）ないしくＣ）と同一符号は第１図と
同一部分を示す。In one embodiment of the present invention, the steps are the same as the conventional method of FIG. 1 until the opening 5 is formed by etching. This same process is shown in FIGS. 3(a) to 3(c). In the drawings, the same reference numerals as in FIGS. 1(a) to 1(c) indicate the same parts as in FIG. 1.
従来と同一工程により開口部５を形成したならば、次に
、レノスト３を残したまま、Ｐｔ 、 Ｔａ 。Once the opening 5 is formed using the same process as the conventional method, Pt and Ta are then formed while leaving the renost 3 intact.
Ｔｉ 、 Ｗ 、 Ｍｏなどの高融点金属８を蒸着ある
いはスパッタリングによって付着させる。この高融点金
属８は、第３図（ｄ）に示すようにレノスト３上および
開口部５により露出したシリコン基板（半導体基板ｌ）
の底面に付着する。A high melting point metal 8 such as Ti, W, Mo, etc. is deposited by vapor deposition or sputtering. As shown in FIG. 3(d), this high melting point metal 8 is applied to the silicon substrate (semiconductor substrate l) exposed on the renost 3 and through the opening 5.
It sticks to the bottom of the.
次に、第３図（ｅ）に示すように、レノスト３およびそ
の上の高融点金属８を除去する。これにより、高融点金
属８は、開口部５のシリコン基板１表面にのみ残る。Next, as shown in FIG. 3(e), the renost 3 and the high melting point metal 8 thereon are removed. As a result, the high melting point metal 8 remains only on the surface of the silicon substrate 1 in the opening 5.
しかる後、１０００℃前後の温度でＮ２などの不活性ガ
ス雰囲気中で熱処置を行う。これによシ、開口部５は、
第３図（ｆ）に示すように端部が緩やかな−形状となる
。また、高融点金属８はシリ丈イド化し、シリコン基板
１とのオーミック性がよくなる。Thereafter, heat treatment is performed at a temperature of around 1000° C. in an inert gas atmosphere such as N2. In addition to this, the opening 5 is
As shown in FIG. 3(f), the end portion has a gentle negative shape. Furthermore, the high melting point metal 8 becomes silicid, and the ohmic properties with the silicon substrate 1 are improved.
しかし、この熱処理時に、開口部５のシリコン基板１に
、絶縁被膜（ＰＳＧ膜）２がらＰ（燐）が拡散すること
は、前記高融点金属８の存在により防止される。However, during this heat treatment, the presence of the high melting point metal 8 prevents P (phosphorus) from diffusing through the insulating film (PSG film) 2 into the silicon substrate 1 in the opening 5 .
その後、開口部５および絶縁被膜２上に第３図（ｇ）に
示すように電極配線用金Ｊｆ４６を蒸着あるいはスパッ
タリングによって付着する。ここで、電極配線用金属６
は、開口部５で高融点金属８と接触し、さらにこの高融
点金属８を介してシリコン基板ｌ忙接続する。−また、
開口部５における高融点金属８の被覆性は、開口部５の
端部が緩やがな形状どなっているから良好である。Thereafter, gold Jf 46 for electrode wiring is deposited on the opening 5 and the insulating film 2 by vapor deposition or sputtering, as shown in FIG. 3(g). Here, metal 6 for electrode wiring
contacts the high melting point metal 8 at the opening 5, and is further connected to the silicon substrate via the high melting point metal 8. -Also,
The coverage of the refractory metal 8 in the opening 5 is good because the end of the opening 5 has a gentle shape.
（発明の効果）
以上の実Ｍ？Ｊがら明らがなようにこの発明の製造方法
では、開口部の半得体基板表面に高融点金属を付着させ
た状態で、開口部の端部を緩やかに・するための高温熱
処理を行う。したがって、この熱処理時に、開口部の半
導体基板に、絶縁被膜（ＰＳＧ族）からＰ （燐）が拡
散することは前記高融点金属によって防止される。よっ
て、前記熱処理が、Ｐチャネル型ＭＯＳのソース・ドレ
イン層の抵抗あるいはＭＯ８特性に悪影普を与えること
はなくなる。(Effect of the invention) The above actual M? As is clear from J, in the manufacturing method of the present invention, high-temperature heat treatment is performed to soften the edges of the opening while a refractory metal is attached to the surface of the semiconductor substrate in the opening. Therefore, during this heat treatment, the high melting point metal prevents P (phosphorus) from diffusing from the insulating film (PSG group) into the semiconductor substrate in the opening. Therefore, the heat treatment will not adversely affect the resistance of the source/drain layer of the P-channel MOS or the MO8 characteristics.
また、開口部の高融点金属は、前記高温熱処理によシ半
導体基板（シリコン基板）と反応してシリサイドを形成
して良好なオーミック性を示す。Furthermore, the high-melting point metal in the opening reacts with the semiconductor substrate (silicon substrate) through the high-temperature heat treatment to form silicide, thereby exhibiting good ohmic properties.
したがって、半導体基板と高融点金属、さらに半導体基
板と金属配線とのコンタクト抵抗は非常に低い値となる
。Therefore, the contact resistance between the semiconductor substrate and the high melting point metal, as well as between the semiconductor substrate and the metal wiring, has a very low value.
以上のようにこの発明の方法は、素子の特性を損なわな
いばかりか、素子の特性を向上させて電惚配服の扱横性
を改善することができる。この発明の方法は、Ｐチャネ
ル型ＭＯ８の製造および、Ｐチャネル型ＭＯ８を有する
Ｃ）ＶＩＯ８の製造に利用することができる。As described above, the method of the present invention not only does not impair the characteristics of the element, but also improves the characteristics of the element and improves the handling properties of the electric clothing. The method of the present invention can be used to manufacture P-channel type MO8 and C)VIO8 having P-channel type MO8.
第１図および第２図は従来の電極配線の製造方法を説明
するだめの断面図、第３図はこの発明の電極配線の製造
方法の一笑施例を説明するだめの断面図である。
ｌ・・・シリコン基板、２・・・絶縁被膜、３・・・レ
ジスト、４・・・窓、５・・・開口部、６・・・電極配
線用金属、７・・・高融点金属。
特許出願人 沖電気工業株式会社
第１図
第２図
第３
８ ５
８1 and 2 are cross-sectional views for explaining a conventional method for manufacturing electrode wiring, and FIG. 3 is a cross-sectional view for explaining an embodiment of the method for manufacturing electrode wiring according to the present invention. 1... Silicon substrate, 2... Insulating film, 3... Resist, 4... Window, 5... Opening, 6... Metal for electrode wiring, 7... High melting point metal. Patent applicant: Oki Electric Industry Co., Ltd. Figure 1 Figure 2 Figure 3 8 5 8
Claims (1)
と、このレジストに窓を形成する工程と、この窓が形成
されたレジストをマスクとして前記絶縁被膜をエツチン
グすることにより、この絶縁被膜に開口部を形成する工
程と、前記レジストを残した状態で、前記開口部によシ
露出した半導体基板の表面に高１点金属を付層させる工
程と、その後前記レソス）４−除去した上で熱処理する
ことにより、前記−口筒５の端部を緩やかにすると同時
に前記局融点金属をシリサイド化する工程と、しかる後
前記開口部を含む絶縁板膜上に電極配線を形成する工程
とを具備してなる電極配線の製造方法。Openings are formed in the insulating film by forming a resist on the insulating film on the surface of the semiconductor substrate, forming a window in this resist, and etching the insulating film using the resist with the window formed as a mask. a step of forming a high point metal on the surface of the semiconductor substrate exposed through the opening with the resist remaining; and then heat treatment after removing the resist. Accordingly, the method includes a step of softening the end of the opening tube 5 and at the same time siliciding the local melting point metal, and then forming an electrode wiring on the insulating plate film including the opening. A method for manufacturing electrode wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22729482A JPS59121834A (en) | 1982-12-28 | 1982-12-28 | Manufacture of electrode wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22729482A JPS59121834A (en) | 1982-12-28 | 1982-12-28 | Manufacture of electrode wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59121834A true JPS59121834A (en) | 1984-07-14 |
Family
ID=16858554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22729482A Pending JPS59121834A (en) | 1982-12-28 | 1982-12-28 | Manufacture of electrode wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121834A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62500343A (en) * | 1984-10-05 | 1987-02-05 | アナログ デバイセス インコ−ポレ−テツド | Low leakage junction field effect transistor |
| JPS62188222A (en) * | 1986-01-11 | 1987-08-17 | Sony Corp | Manufacture of semiconductor compound |
-
1982
- 1982-12-28 JP JP22729482A patent/JPS59121834A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62500343A (en) * | 1984-10-05 | 1987-02-05 | アナログ デバイセス インコ−ポレ−テツド | Low leakage junction field effect transistor |
| JPS62188222A (en) * | 1986-01-11 | 1987-08-17 | Sony Corp | Manufacture of semiconductor compound |
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