JPS59113666A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS59113666A JPS59113666A JP22341082A JP22341082A JPS59113666A JP S59113666 A JPS59113666 A JP S59113666A JP 22341082 A JP22341082 A JP 22341082A JP 22341082 A JP22341082 A JP 22341082A JP S59113666 A JPS59113666 A JP S59113666A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- layer
- etched
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000010408 film Substances 0.000 claims abstract description 66
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- 238000005530 etching Methods 0.000 abstract description 19
- 229910052681 coesite Inorganic materials 0.000 abstract description 11
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 11
- 239000000377 silicon dioxide Substances 0.000 abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 11
- 229910052682 stishovite Inorganic materials 0.000 abstract description 11
- 229910052905 tridymite Inorganic materials 0.000 abstract description 11
- 239000011521 glass Substances 0.000 abstract description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000354 decomposition reaction Methods 0.000 abstract description 3
- 239000007769 metal material Substances 0.000 abstract description 2
- 239000002904 solvent Substances 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910001120 nichrome Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、液晶セルのスイッチング等に用いる薄膜トラ
ンジスタ、特にソース・ドレイン電極としてｎ＋型アモ
ルファスシリコン／金属構造を採用することにより保護
膜、配向膜等の形成プロセスにおいて高温にさらされて
も特性変化を生しないようにした薄膜トランジスタの製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a thin film transistor used for switching liquid crystal cells, etc., and in particular, to forming a protective film, an alignment film, etc. by adopting an n+ type amorphous silicon/metal structure as source/drain electrodes. The present invention relates to a method for manufacturing a thin film transistor that does not cause characteristic changes even when exposed to high temperatures during a process.
従来技術と問題点
アモルファスシリコン（ａ−３ｔ ： Ｈ） ｔ！膜ト
ランジスタのソース・ドレイン電極としてはｎ＋ａ −
３ｉ／金属構造が優れている。即ちこの種トランジスタ
は第１図ｆａｌに示すようにガラス基板１にゲート電極
２、ゲート絶縁膜３、ａ−３ｉ層４、アルミニウムのソ
ース・ドレイン電極１０ ａ、 １０ｂからなるが、
ケート電極２でａ−３ｉ層４にチャネルを作りソース・
ドレイン電極間に電流（電子）を流してｌ・ランジスタ
動作させるにはａ−３ｉ Ｔｆｉ ４とソース・ドレイ
ン電極ｔｏａ、１０ｂとのオーミックコンタクト特に電
子に対するそれが良好でなければならない。Conventional technology and problems Amorphous silicon (a-3t: H) t! As source/drain electrodes of membrane transistors, n+a −
3i/Excellent metal structure. That is, as shown in FIG. 1, this type of transistor consists of a glass substrate 1, a gate electrode 2, a gate insulating film 3, an a-3i layer 4, and aluminum source/drain electrodes 10a and 10b.
A channel is created in the a-3i layer 4 using the gate electrode 2 and the source
In order to operate the transistor by flowing current (electrons) between the drain electrodes, the ohmic contact between the a-3i Tfi 4 and the source/drain electrodes toa and 10b must be good, especially for electrons.
現在、１ａ−３ｔと電子に対して良いオーミック電極と
して働く金属はアルミニウム（Ａｌｌ）が知られている
。ところが／ｌは３価であるため熱的な拡散等でａ−３
ｉ中にはいるとアクセプターとして働き、Ａｊ！／ａ−
３ｉコンタクトは１００〜３００°Ｃ程度の熱履歴の後
にボールに対しても良好なオーミック接触を示してしま
う。この結果ＴＰＴはボールアキュムレーションモード
でも働くようになりＯＦＦ状態のマージンがとれなくな
る。電子に対してだけ良好なオーム接触を得るにはｎ＋
ｉ層を介在させて金属ソース・トレイン電極をａ−３ｔ
チャネル層４に接触させるのがよい。Aluminum (All) is currently known as a metal that acts as a good ohmic electrode for 1a-3t and electrons. However, since /l is trivalent, it becomes a-3 due to thermal diffusion, etc.
Once inside i, it acts as an acceptor, and Aj! /a-
The 3i contact shows good ohmic contact even with the ball after a thermal history of about 100 to 300°C. As a result, the TPT also works in the ball accumulation mode, making it impossible to maintain a margin in the OFF state. To get good ohmic contact only for electrons, n+
A-3T metal source/train electrode with i layer interposed
It is preferable to contact the channel layer 4.
ｎ＋ａ −Ｓ ｉ層８ａ、８ｂを介在させるとするとか
＼る薄膜トランジスタの製造工程は第１図（ｂｌに示す
ようにガラス基板１上にゲート電極２、ゲート絶縁膜３
、ａ−３ｉ層４、ｎ＋ａ −Ｓ ｉ層８、ソース・ドレ
イン用アルミニウム膜１０をＣＶＤ、蒸着などにより順
次形成し、次いでチャネル部のＡｅ成膜０ａ及びｎ＋ａ
−３ｉｌｉ８ｃを除去することが必要である（除去しな
いとソース・ドレイン間が短絡する）。除去するには、
周知のエツチング法またはリフトオフ法が有効である。The manufacturing process of a thin film transistor in which n+a-Si layers 8a and 8b are interposed is as shown in FIG.
, a-3i layer 4, n+a-Si layer 8, and aluminum film 10 for source/drain are sequentially formed by CVD, vapor deposition, etc., and then Ae films 0a and n+a of the channel part are formed.
It is necessary to remove -3ili8c (if not removed, a short circuit will occur between the source and drain). To remove,
Well-known etching or lift-off methods are effective.
しかしエツチング法では、ソース・ドレイン電極の分離
つまりアルミニウムのエツチングは、該アルミニウム層
の下層はｎ”ａ −Ｓ ｉでＡβとはエツチング液が異
なるから簡単、容易であるが、ｎ”ａ −Ｓ ｉ層゛８
のエツチングか厄介である。即ちｎ＋ａ −Ｓ ｉ膜と
１ａ−３ｉｌＪとのエツチングレートの比は１膜２程度
と小さいため、ｎ”ａ −Ｓ ｉ層だけを選択的にエツ
チングすることが困難で、図示のようにａ−３１ｌｉＷ
４を削ってしまう（エツチング過剰）又はｎ”ａ−３ｉ
層が残留（エツチング液足）してしまう。However, in the etching method, separation of the source and drain electrodes, that is, etching of aluminum, is simple and easy because the lower layer of the aluminum layer is n"a-Si and the etching solution is different from Aβ, but n"a-S i-layer 8
The etching is troublesome. That is, since the etching rate ratio between the n+a-Si film and the 1a-3ilJ is as small as 1 film and 2, it is difficult to selectively etch only the n''a-Si layer, and as shown in the figure, the a- 31liW
4 is removed (excessive etching) or n”a-3i
A layer remains (etching liquid feet).
リフトオフ法はａ−３ｉ層４まで積んだとき、層４の上
部に厚くレジストを塗布し、パターニングしてゲート上
のレジストのみ残し、か−る状態でｎ＋ａ −Ｓ ｉ層
及びＡβ層１ｏを被着し、リフトオフして第１図（ａｌ
の状態にするが、この方式はｎ＋ａ−３ｉ膜８の成膜時
の基板温度が２５０°〜３００°程度と高いためレジス
トの耐熱性を考えると、プロセス的に採用は殆んど不可
能である。In the lift-off method, when the a-3i layer 4 is stacked, a thick resist is applied to the top of the layer 4, and patterned to leave only the resist on the gate, and in this state the n+a-Si layer and the Aβ layer 1o are covered. Arrived, lifted off and moved to Figure 1 (al.
However, in this method, the substrate temperature during the formation of the n+a-3i film 8 is as high as 250° to 300°, so it is almost impossible to adopt this method considering the heat resistance of the resist. be.
発明の目的
本発明はゲート上ｎ＋ａ −Ｓ ｉ層及びＡ４層の除去
にエツチング法を用いるが、このエツチングを容易かつ
正確に行なうことができ、またゲート層つまりチャネル
部の表面保護も同時に行なうことができる製造法を提供
しようとするものである。Purpose of the Invention The present invention uses an etching method to remove the n+a-Si layer and the A4 layer on the gate, and it is an object of the present invention to be able to perform this etching easily and accurately, and to protect the surface of the gate layer, that is, the channel portion, at the same time. The aim is to provide a manufacturing method that allows for
発明の構成
本発明でば、ゲーＩ・Ｓ ｉ Ｏ２膜、ａ−８ｉ膜とと
もに連続放映した５ｉ０２膜をチャネル部に残すことに
より外部雰囲気あるいは薄膜トランジスタ上部にさらに
形成する膜等の影響を受けない安定な特性が得られ、さ
らにこの５ｉ０２膜をｎ”ａ −３ｔ膜工ツチング時の
ストッパーとして用いることにより、ｎ＋層だけを確実
に取り去ることのできるエツチングプロセスを提供でき
ソース・トレイン電極としてｎ＋ａ−３ｉ／金属構造を
有する薄膜トランジスタの製造を容易にすることができ
る。Structure of the Invention According to the present invention, by leaving the 5i02 film, which is continuously exposed together with the GaISiO2 film and the a-8i film, in the channel region, it is possible to maintain stability without being affected by the external atmosphere or other films further formed on the top of the thin film transistor. Furthermore, by using this 5i02 film as a stopper during etching of the n"a-3t film, it is possible to provide an etching process that can reliably remove only the n+ layer. /It is possible to easily manufacture a thin film transistor having a metal structure.
即ち本発明は半導体層にアモルファスシリコン薄膜を用
いた薄膜トランジスタの製造方法において、ゲート電極
を形成した基板上にゲート絶縁膜、アモルファスシリコ
ン膜、保護用絶縁膜を逐次連続製膜した後、エツチング
してチャネル部にのみ該保護絶縁膜を残し、次いでｎ＋
型アモルファスシリコン膜及び金属膜を製膜し、該金属
膜をパターニングして金属ソース・ドレイン電極を形成
し、これをマスクにチャネル部の前記ｎ＋型アモルファ
スシリコン膜をエツチングしてｎ”ａ−３ｉ／金属構造
のソース・ドレイン電極を構成することを特徴とするが
、次に実施例を参照しながらこれを詳細に説明する。That is, the present invention is a method for manufacturing a thin film transistor using an amorphous silicon thin film as a semiconductor layer, in which a gate insulating film, an amorphous silicon film, and a protective insulating film are successively formed on a substrate on which a gate electrode is formed, and then etched. The protective insulating film is left only in the channel part, and then the n+
A type amorphous silicon film and a metal film are formed, the metal film is patterned to form a metal source/drain electrode, and using this as a mask, the n+ type amorphous silicon film in the channel portion is etched to form an n''a-3i The present invention is characterized in that the source/drain electrodes have a metal structure, which will be described in detail below with reference to Examples.
発明の実施例
第２図は本発明の実施例を示す薄膜トランジスタＴＰＴ
の製造工程図である。この工程図に従って本発明を説明
するに先ず（ａｌに示すようにガラス基板ｌにニクロム
（ＮｉＣｒ）を蒸着し、パターニングしてゲート電極２
を作る。このゲート電極２を形成したガラス基板＋１１
上に、グロー放電分解法を用いてゲート５ｉ０２膜３を
３０００人、ａ−３ｔ膜４を５０００人、保護ＳｉＯ２
膜５を３０００人、レジスト（Ａ Ｚ）との密着性をよ
くするためのａ−３ｉ層６を２００人、真空を破らず連
続で製膜する。次にレジスト（ＡＺ１３５０Ｊ）を塗布
し、パターニングして同図（ｂ）に示す所要形状のレジ
スト膜７を作る。次にレジスト膜７をマスクとしてａ−
３ｉ層６を、ＣＦａガスを用いたプラズマエツチングに
て、また５１０２層５をエツチング液Ｆ１０８を用いた
ケミカルエツチングにて取り去る。その後レジスト膜７
を溶剤アセトンにて除去し同図（Ｃ１の状態にする。Embodiment of the invention FIG. 2 shows a thin film transistor TPT showing an embodiment of the invention.
FIG. To explain the present invention according to this process diagram, first, as shown in (al), nichrome (NiCr) is vapor-deposited on a glass substrate l, and patterned to form a gate electrode 2.
make. Glass substrate +11 on which this gate electrode 2 is formed
On top, using the glow discharge decomposition method, 3000 layers of gate 5i02 film 3, 5000 layers of a-3t film 4, and protective SiO2
The film 5 was formed by 3000 people, and the a-3i layer 6 was formed by 200 people to improve adhesion to the resist (AZ), and the film was formed continuously without breaking the vacuum. Next, a resist (AZ1350J) is applied and patterned to form a resist film 7 having a desired shape as shown in FIG. Next, using the resist film 7 as a mask, a-
The 3i layer 6 is removed by plasma etching using CFa gas, and the 5102 layer 5 is removed by chemical etching using etching solution F108. After that, resist film 7
is removed using the solvent acetone to obtain the state shown in the same figure (C1).
次に同図（ｄ）に示ずようにｎ＋３ Ｓ ｉ８を４０
０人程度、グロー放電分解法にて製膜する。次に再びレ
ジスト（ＡＺ１３５０Ｊ）を塗布し、バターニングして
同図（ｅｌに示すように位置合せした所要形状のレジス
ト膜９を作り、この状態で金属本例ではアルミニウム、
ニクロム等（Ａ Ａ／ｎ ａ−３ｉ ／ ｉ ａ −Ｓ
ｉ構造でば熱履歴後ボールアキュムレーションモード
のみられることがあるため）１０を蒸着する。その後リ
フトオフを行なって金属材料１０のソース・ドレイン電
極パターンを形成し、これをマスクにｎ＋２−８ｉ（８
）の不要部をＣＦａプラズマによりエツチングする。ｎ
”ａ−３ｉｌｉ５８の下部には８１０２層５があり、こ
れはＣＦ４プラズマによるエツチングレートがａ−３ｉ
はど高くないので、ｎ＋２３ｉ層のエツチングは容易に
行なえる。こうして同図（ｆｌの求める状態を得る。Next, as shown in the same figure (d), n+3 S i8 is 40
Approximately 0 people use the glow discharge decomposition method to form the film. Next, a resist (AZ1350J) is applied again and buttered to form a resist film 9 of the desired shape aligned as shown in the same figure (el).
Nichrome etc. (AA/na-3i/ia-S
In case of i-structure, ball accumulation mode may be observed after thermal history). After that, lift-off is performed to form a source/drain electrode pattern of the metal material 10, and using this as a mask, n+2-8i (8
) is etched by CFa plasma. n
``There is an 8102 layer 5 below the a-3ili 58, which has an etching rate of CF4 plasma of a-3i.
Since the height is not high, the n+23i layer can be easily etched. In this way, the state desired by fl is obtained in the same figure.
レジストＡＺ１３５０ＪはＳｉＯ２との密着が悪く、こ
れを改善するため集積回路、製造工程などではカンブリ
ング剤を用いているが、本発明のようにａ−ｓｉｌｉｉ
ｉ６を用いると簡単につまりａ−３ｉ層４の製造工程を
もう一度行なう、保護膜５の製造工程から見れば単にガ
スを入れ換えるだけで密着製改善ができる。Resist AZ1350J has poor adhesion to SiO2, and to improve this, a combing agent is used in integrated circuits and manufacturing processes.
If i6 is used, the adhesion can be improved simply by repeating the manufacturing process of the a-3i layer 4, or by simply replacing the gas from the viewpoint of the manufacturing process of the protective film 5.
保護用ＳｉＯ２層５がないとａ−３ｉ層４のチャネル部
は露出することになる。か＼るＴＦＴは液晶ディスプレ
イなどに用い□られ、この場合配向膜が上面つまりソー
ス・トレイン電ｔｉｌｏａ、１０ｂ側に被着されるが、
この結果チャネルが雷時オンになってＴＰＴはスイッチ
ング機能を失なうなどの問題がある。保護膜５があると
きか−る問題の発生を回避できる。Without the protective SiO2 layer 5, the channel portion of the a-3i layer 4 would be exposed. Such TFTs are used in liquid crystal displays, etc., and in this case, an alignment film is deposited on the upper surface, that is, on the source train electrode 10b side.
As a result, there is a problem that the channel is turned on during lightning and the TPT loses its switching function. When the protective film 5 is provided, the above problem can be avoided.
発明の詳細
な説明したことから明らかなように本発明によれば、半
導体活性層４の上下両界面は連続成膜工程によるＳｉＯ
２膜に接しているので、界面の清浄性の欠除からくる特
性の不安定性がない。また上部の５ｉ０２膜５はエツチ
ングプロセスによりｎ”ａ−３ｉ ８／金１１１０ｔＲ
造のソース・ドレイン電極を形成する際のｎａ−３ｔエ
ツチングのストッパーとして（ｌＪ＜ため、エツチング
プロセスか確実である等の利点が得られる。この本発明
によるＴＰＴは半導体活性層の上下両界面を清浄に保ち
かつ確実なエツチングプロセスによりｎ＋２− Ｓ ｉ
／金属構造のソース・トレイン電極を構成することがで
きるので、トランジスタ作製直後はもちろん、作製後に
さらに保護膜や液晶の配向膜を形成する等の高温（〜３
００°Ｃ）プロセスを経ても特性は安定である。As is clear from the detailed description of the invention, according to the present invention, both the upper and lower interfaces of the semiconductor active layer 4 are made of SiO through a continuous film forming process.
Since it is in contact with two membranes, there is no instability in properties due to lack of cleanliness at the interface. Furthermore, the upper 5i02 film 5 is etched with n"a-3i 8/gold 1110tR by an etching process.
As a stopper for NA-3T etching when forming source/drain electrodes (LJ<), the TPT according to the present invention has advantages such as a reliable etching process. n+2-S i by keeping it clean and using a reliable etching process.
/ Since the source/train electrode can be constructed with a metal structure, it can be used not only immediately after transistor fabrication, but also after fabrication at high temperatures (up to 3
The properties remain stable even after the process (00°C).
第１図は薄膜トランジスタの説明図、第２図は本発明の
実施例を示す工程図である。
図面で１＝ガラス基板、２ ： Ｎ ｉ Ｃｒゲート電
極、３：ケート絶縁膜（ＧＤ ＳｉＯ２膜）、４二半
導体活性層（ノンドープ ａ−３ｉ：Ｈ膜）、５：チャ
ネル部保護用絶縁膜（ＧＤ ＳｉＯ２膜）、６：ＧＤ
ａ−３ｉ：Ｈ膜、７：レジスト、８：ｎ”ａ−３ｉ
：Ｈ膜、９ニレジスト、１０：金属電極。
出願人 富士通株式会社
代理人弁理士 青 柳 稔FIG. 1 is an explanatory diagram of a thin film transistor, and FIG. 2 is a process diagram showing an embodiment of the present invention. In the drawing, 1 = glass substrate, 2: NiCr gate electrode, 3: gate insulating film (GD SiO2 film), 42: semiconductor active layer (non-doped a-3i:H film), 5: channel protection insulating film ( GD SiO2 film), 6:GD
a-3i: H film, 7: resist, 8: n''a-3i
:H film, 9 resist, 10: metal electrode. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi
Claims (1)
ンジスタの製造方法において、ゲート電極を形成した基
板上にゲート絶縁膜、アモルファスシリコン膜、保護用
絶縁膜を逐次連続製膜した後、エツチングしてチャネル
部にのみ該保護絶縁膜を残し、次いでｎ＋型アモルファ
スシリコン膜及び金属膜を！！股し、該金属膜をパター
ニングして金属ソース・ドレイン電極を形成し、これを
マスクにチャネル部の前記ｎ＋型アモルファスシリコン
膜をエツチングしてｌ”ａ−３ｉ ／金属構造のソース
・ドレイン電極を構成することを特徴とする薄膜トラン
ジスタの製造方法。In a method for manufacturing a thin film transistor using an amorphous silicon thin film as a semiconductor layer, a gate insulating film, an amorphous silicon film, and a protective insulating film are sequentially formed on a substrate on which a gate electrode is formed, and then etched only in the channel region. Leave the protective insulating film behind, then apply the n+ type amorphous silicon film and metal film! ! Then, the metal film is patterned to form metal source/drain electrodes, and using this as a mask, the n+ type amorphous silicon film in the channel part is etched to form source/drain electrodes with a l''a-3i/metal structure. 1. A method of manufacturing a thin film transistor, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22341082A JPS59113666A (en) | 1982-12-20 | 1982-12-20 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22341082A JPS59113666A (en) | 1982-12-20 | 1982-12-20 | Manufacture of thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59113666A true JPS59113666A (en) | 1984-06-30 |
| JPH0556016B2 JPH0556016B2 (en) | 1993-08-18 |
Family
ID=16797703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22341082A Granted JPS59113666A (en) | 1982-12-20 | 1982-12-20 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59113666A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4778773A (en) * | 1986-06-10 | 1988-10-18 | Nec Corporation | Method of manufacturing a thin film transistor |
| JPS644071A (en) * | 1987-06-26 | 1989-01-09 | Nippon Telegraph & Telephone | Thin film transistor and manufacture thereof |
| US4958205A (en) * | 1985-03-29 | 1990-09-18 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor array and method of manufacturing the same |
| US5045487A (en) * | 1982-03-31 | 1991-09-03 | Fujitsu Limited | Process for producing a thin film field-effect transistor |
| US5166086A (en) * | 1985-03-29 | 1992-11-24 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor array and method of manufacturing same |
| US5493129A (en) * | 1988-06-29 | 1996-02-20 | Hitachi, Ltd. | Thin film transistor structure having increased on-current |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58212177A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Insulated gate type transistor and manufacture thereof |
-
1982
- 1982-12-20 JP JP22341082A patent/JPS59113666A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58212177A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Insulated gate type transistor and manufacture thereof |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5045487A (en) * | 1982-03-31 | 1991-09-03 | Fujitsu Limited | Process for producing a thin film field-effect transistor |
| US4958205A (en) * | 1985-03-29 | 1990-09-18 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor array and method of manufacturing the same |
| US5137841A (en) * | 1985-03-29 | 1992-08-11 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing a thin film transistor using positive and negative photoresists |
| US5166086A (en) * | 1985-03-29 | 1992-11-24 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor array and method of manufacturing same |
| US4778773A (en) * | 1986-06-10 | 1988-10-18 | Nec Corporation | Method of manufacturing a thin film transistor |
| JPS644071A (en) * | 1987-06-26 | 1989-01-09 | Nippon Telegraph & Telephone | Thin film transistor and manufacture thereof |
| US5493129A (en) * | 1988-06-29 | 1996-02-20 | Hitachi, Ltd. | Thin film transistor structure having increased on-current |
| US5821565A (en) * | 1988-06-29 | 1998-10-13 | Hitachi, Ltd. | Thin film transistor structure having increased on-current |
| US5981973A (en) * | 1988-06-29 | 1999-11-09 | Hitachi, Ltd. | Thin film transistor structure having increased on-current |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0556016B2 (en) | 1993-08-18 |
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