JPS61156106A - Substrate for liquid crystal display - Google Patents

Abstract

PURPOSE:To obtain a substrate for liquid crystal display which is less in leakage current and easily produced, by providing a gate electrode made of a high- melting point material, insulating film covering the gate electrode, and semicon ductor coating film formed on the insulating film and equipped with a PN junction whose channel is formed by using the gate electrode as a mask. CONSTITUTION:Since intense tensile stress is applied to a gate electrode 2 made of a high-melting point material in the course of various processes, espe cially at the time of heating treatment, etc., the gate electrode 2 is put between and supported by a base layer 3 of polystalline silicon and chemical-resisting protecting film 4 of silicon dioxide. The gate electrode 2 is covered with an insulating film 5 of silicon dioxide and (P) type polycrystalline silicon 6 and (N<+>) type polycrystalline silicon 7 respectively have PN junctions (h) and (i) at their boundary faces and constitute semiconductor coating films forming NPN transistors which are separated from each other by means of a channel (j). A protecting film and orienting film of liquid crystal can be provided further to the surface of a source drain electrode 8 and transparent electrode 9 forming a displaying picture element, if necessary.

Description

【発明の詳細な説明】 イ）産業上の利用分野 本発明は薄膜叱幼素子を一巣毎に何する液晶表示器用基
板に閃するっ 口）従来の技術 従来、液晶表示器の自索毎に上納素子を設ける事が盛ん
に研究され、一部曲品化もされているが、特に歩留り等
の関係から能！１１Ｊ木子として＃膜能納素子を利用す
る事が好まれ、特開昭５８−２１６２８５号、特開昭５
９−１９５６８０号等、枚挙に厘かない。そしてこれら
の薄膜能動索子はアモルファス型と多結晶型に大別され
るが次の様な特性がある。[Detailed Description of the Invention] A) Industrial Application Field The present invention is directed to the use of a thin film retarding element on a substrate for a liquid crystal display for each unit. Although there has been active research into installing a top-loading element in the semiconductor, and some have even been made into curved products, it has not been possible to do so due to issues such as yield. It is preferred to use a #membrane Nona element as the 11J tree, and is disclosed in Japanese Patent Application Laid-open Nos. 58-216285 and 1983.
9-195680, etc., too numerous to mention. These thin film active cords are broadly classified into amorphous type and polycrystalline type, and have the following characteristics.

アモルファス（非晶質リンリコンを用いた薄膜能＃素子
は、一般に漏れ電流が小さいが、キャリア移ＩＩＩＩＪ
度が低いため応答が遅く、チャネル寸法を小さくするこ
とで高速性を得ようとしているが限界がある。Thin film devices using amorphous (non-crystalline phosphorus) generally have low leakage current, but carrier transfer
The response is slow due to the low sensitivity, and attempts have been made to achieve high speed by reducing the channel dimensions, but there are limits.

一方多結晶ンリコンを用いるとキャリア移動度がアモル
ファス型の１〜２桁大きいためスイッチング特性は優れ
ている。しかし逆に漏れ電流が大さく、１ＩＩＩＩＩを
挟持したＭＯＳ梨にするなど特別の工夫をしているが、
位置合せ等製造が煩雑になり、歩餉低十を生じやすい。On the other hand, when polycrystalline silicon is used, the carrier mobility is one to two orders of magnitude higher than that of the amorphous type, and the switching characteristics are excellent. However, on the other hand, the leakage current is large, so special measures have been taken such as using a MOS pear with 1III sandwiched between them.
Manufacture such as alignment becomes complicated, and it is easy to cause errors.

ノリ発明が解決しようとする開祖点 本光用は上述の点を改めるために行なわれたもので、漏
れ電流が少なく製造しやすい液晶表示器用基板を提供す
るものである。This invention was made to solve the above-mentioned problems, and is to provide a substrate for a liquid crystal display that has low leakage current and is easy to manufacture.

二）問題点を解決するための手段 本発明はゲート電極に高融点材料を用い、ゲート電極を
マスクとして形成されたチャンネルとＰＮ接合とを有す
る多結晶型の半導体被膜とを具備したものである。2) Means for Solving the Problems The present invention uses a high melting point material for the gate electrode, and is equipped with a polycrystalline semiconductor film having a channel and a PN junction formed using the gate electrode as a mask. .

ホ）作　用 このような構成に工り、パターン上液も重要なチャンネ
ルは自己整合で製造しやすく、ＰＮ接合により漏れ電流
が抑えられる。E) Function: With such a structure, the channel, which is important for the liquid on the pattern, is self-aligned and easy to manufacture, and leakage current is suppressed by the PN junction.

へ）実施例 第１図は本発明の実施例の液晶表示器用基板の要部模式
図（ａ）とＡ−ＡＩ’断面図（ｂ）である。図において
（１）はガラス等の絶縁基板で、（２）は高融点材料か
らなるゲート電極である。このゲート電極（２）は諸工
程中に特に加熱処理等で大きな引張応力が加わるので多
結晶シリコンの下地層（３）と二酸化シリコンの耐薬品
用の保ｔｊＩｌ膜（４）で挟持されている。（５）はゲ
ート電ｍ　（２１を覆う二酸化シリコンの絶縁膜である
。（６）はＰ型多結晶のシリコン、（７）はｎ＋型多結
晶のシリコンでこれらは境界面にＰｎ！？Ａ合す）（ロ
）を有しチャンネル（ハ）により分離されたｎＰｎ　ト
ランジスタを形成する半導体被膜となっている。１８１
　（８）はソース・ドレイン電極、（９）は表示画素を
形成するａ用電極である。図示していないが、これらの
構成のさらに表面に、必要に応じて保護膜や液晶の配向
膜を設けてもよい。f) Embodiment FIG. 1 is a schematic diagram (a) of a main part of a substrate for a liquid crystal display according to an embodiment of the present invention, and a sectional view (b) taken along line A-AI'. In the figure, (1) is an insulating substrate made of glass or the like, and (2) is a gate electrode made of a high melting point material. Since large tensile stress is applied to this gate electrode (2) during various processes, especially during heat treatment, it is sandwiched between a polycrystalline silicon base layer (3) and a silicon dioxide chemical-resistant protective film (4). . (5) is a silicon dioxide insulating film that covers the gate electrode m (21). (6) is P-type polycrystalline silicon, (7) is n+-type polycrystalline silicon, and these have Pn!?A at the interface. It is a semiconductor film that forms an nPn transistor having two layers (b) connected to each other and separated by a channel (c). 181
(8) is a source/drain electrode, and (9) is an electrode for a forming a display pixel. Although not shown, a protective film or a liquid crystal alignment film may be further provided on the surface of these structures as necessary.

このような構造の液晶表示器用基板の製造方法について
第２図に基づいて説明する。まず第２図（−）に示すよ
うに絶縁基板（１）上にＰドープの多結晶シリコン膜Ｕ
を６００℃ＬＰ−ＣＶＤ決により約０．２μｍ、次いで
モリブデン膜（１２１を真空魚看て０゜２μｍ、さらに
５ｉ０２膜（１４１をＡＴ−ＣＶＤ＆により約０．１μ
ｍ棟層し、ゲート電極に対応する位置にレジスト（２）
を設ける。（レジストは以後も単に設けると表現するが
通常のフォトリングラフィにより、スピンナーによるＵ
Ｖレジスト材檗布、露光、現像のいわゆるパターニング
工程ヲさんでいる。）このレジストをもとにドライエツ
チングしてゲート電極（２）等を形成するっ レジスト■を除去した後Ｓ　ｉ０２膜Ｉ５）を０．４μ
ｍ、Ｐ−ドープの多結晶シリコン膜（１６）を６００”
ＣＬＰ−ＣＶＤ＆により０．６μｍ次いでドーパントを
ｎ梨にした多結晶シリコン膜Ｕη＋ｃ１同工程により０
．４／Ｉｍ順次堆槓し、レジメ）　ｆ２１１を設ける。A method of manufacturing a substrate for a liquid crystal display having such a structure will be explained based on FIG. 2. First, as shown in FIG. 2 (-), a P-doped polycrystalline silicon film U is placed on an insulating substrate (1).
A film of about 0.2 μm was formed by LP-CVD at 600℃, then a molybdenum film (121 was formed to a thickness of 0.2 μm using a vacuum filter), and a 5i02 film (141 was formed to about 0.1 μm by AT-CVD).
m ridge layer and resist (2) at the position corresponding to the gate electrode.
will be established. (The resist will be expressed as simply being provided from now on, but by normal photolithography, the resist will be
It handles the so-called patterning process of V-resist material, exposure, and development. ) Based on this resist, dry etching is performed to form the gate electrode (2) etc. After removing the resist (2), the Si02 film I5) is deposited with a thickness of 0.4 μm.
m, P-doped polycrystalline silicon film (16) with a thickness of 600"
A polycrystalline silicon film Uη+c1 with a dopant of 0.6 μm was formed by CLP-CVD & the same process
．． 4/Im sequentially piled, regimen) f211 is provided.

ここで重要なことは、レジストシυのパターニングにあ
たって露光を絶縁基板（１）側から行うことで、これに
よりゲート電極（２）がマスクとなり、セルフアライメ
ント（自己整合）パターニングが行えることである。（
第２図（ｂ）参照〕このレジス）　ＣＩ！］ｌをもとに
上側の多結晶シリコン膜０ηのみをドライエッチレチャ
ネル（ハ）を形成する。次いでレジス１１２υを１余去
し、第２図（Ｃ）に示すように新たなレジスト囚を形成
して、上下層の多結晶シリコン模り□□□（１７）を除
去し、レジストリも除去する。そして熱拡敢、光アニー
ル等（例えば１０５０℃２時間）ＫよりＰｎ接合を形成
するが、この時ｔｃ血に０．　＋μｍ程度の酸化シリコ
ン薄膜α９も形成され、これによりｎＰｎ　トランジス
タは極めて安定なものとなる。What is important here is that when patterning the resist film υ, exposure is performed from the insulating substrate (1) side, so that the gate electrode (2) serves as a mask and self-alignment patterning can be performed. (
Refer to Figure 2 (b)] CI! ] A dry etch channel (c) is formed only in the upper polycrystalline silicon film 0η based on the polycrystalline silicon film 0η. Next, one part of the resist 112υ is removed, a new resist is formed as shown in FIG. 2(C), and the upper and lower layers of the polycrystalline silicon pattern □□□ (17) are removed, and the resist is also removed. . Then, a Pn junction is formed using K by thermal expansion, photo-annealing, etc. (for example, 1050°C for 2 hours), but at this time, the tc blood has 0. A silicon oxide thin film α9 of about +μm is also formed, which makes the nPn transistor extremely stable.

次いで￥Ｊ２図（ｄ）に示すように給電路を形成するた
めに酸化シリコン＃暎（１５１Ｋ　窓ｔつけるためのレ
ジストノを設はドライエンチし、レジスト（支）除去後
にアルミニクムを主材とした例えばＡｔ−５ｉ（２％）
層側を蒸着又はスパッタにより設ける。そして同図（ｅ
）の如く再びレジスト（至）によねパターニングし、窒
素雰囲気中でアニールする。Next, as shown in Figure 2 (d), a silicon oxide resist (151K) was dry-etched to form a power supply path, and after the resist was removed, a resist made of aluminum, such as aluminum, was used as the main material. -5i (2%)
The layer side is provided by vapor deposition or sputtering. And the same figure (e
), the resist is again patterned and annealed in a nitrogen atmosphere.

Ｍｋ後に適用電極（ＩＴＯ）膜四を蒸看又４スパッタで
約０．１μｍ塗布し、第２図（ｆ）の如くレジストｔａ
でパターニングして第１図（ｂ）のような基板を得る。After Mk, apply an applied electrode (ITO) film 4 by steam or sputtering to a thickness of about 0.1 μm, and form a resist ta as shown in FIG. 2(f).
A substrate as shown in FIG. 1(b) is obtained by patterning.

ト）発り、１４の効果 以上の如くにより、高温処理が重なるけれどもゲート電
極は高融点材料（上述のモリブデンの他、タンタル、タ
ングステンでも町）であるからパターンくずれや揮発は
なく、かつその影Ｖこよる自己整合によりチャネルが形
成出来るから最も重要な位は合せが周単に行える。さら
に能動索子としてはｎ＋Ｐｎ＋（上述の例の連でｆｎＰ
＋でもよい）の構成を何しているので麹れ電流が少なく
でさる。g) As described above, although the high-temperature treatment is repeated, since the gate electrode is made of a high-melting point material (in addition to the above-mentioned molybdenum, tantalum and tungsten are also used), there will be no pattern distortion or volatilization, and the effect of Since a channel can be formed by self-alignment using V, the most important point can be easily aligned. Furthermore, as an active chord, n+Pn+ (fnP in the above example series)
Because of the structure of the (+ is acceptable), the malting current is small.

向上Ｕ＋Ｖをｎ−１（又はｐ＋　　）にするのは：Ａ’
−ミック接ＩＩＩｊ＆をとりやすくする上でも効果が大
きい。To make the improvement U+V n-1 (or p+): A'
- It is also very effective in making it easier to take the Mick contact IIIj&.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明実施例の液晶表示器用基板の要部模式図
（ａ）とそのＡ−Ａ’断面図（ｂ）、第２図（ａ）乃至
（ｆ）はその製造工程を説明する工程図である。 （１）・・・絶縁基板、（２）・・・ゲート電極、（５
）・・・絶縁膜、（６）・・・（Ｐ型多結晶の）シリコ
ン、（７）・・・（ｎ”１Ｍ多結晶の）シリコン、１８
）１８）・・・ソース・ドレン電極、１９）・・・透明
電極。Fig. 1 is a schematic diagram (a) of a main part of a substrate for a liquid crystal display according to an embodiment of the present invention, and its AA' cross-sectional view (b), and Fig. 2 (a) to (f) explain the manufacturing process thereof. It is a process diagram. (1)...Insulating substrate, (2)...Gate electrode, (5
)...Insulating film, (6)...(P-type polycrystalline) silicon, (7)...(n''1M polycrystalline) silicon, 18
)18)...Source/drain electrode, 19)...Transparent electrode.

Claims (1)

【特許請求の範囲】[Claims] １）絶縁基板と、絶縁基盤上に設けられた高融点材料か
らなるゲート電極と、そのゲート電極を覆う絶縁膜と、
絶縁膜上に形成され、ゲート電極をマスクとしてチヤネ
ルが形成されたＰＮ接合を有する半導体被膜とを具備し
た事を特徴とする液晶表示器用基板。1) an insulating substrate, a gate electrode made of a high melting point material provided on the insulating substrate, and an insulating film covering the gate electrode;
1. A substrate for a liquid crystal display, comprising a semiconductor film formed on an insulating film and having a PN junction in which a channel is formed using a gate electrode as a mask.