JPH0546106B2 - - Google Patents
Info
- Publication number
- JPH0546106B2 JPH0546106B2 JP57072428A JP7242882A JPH0546106B2 JP H0546106 B2 JPH0546106 B2 JP H0546106B2 JP 57072428 A JP57072428 A JP 57072428A JP 7242882 A JP7242882 A JP 7242882A JP H0546106 B2 JPH0546106 B2 JP H0546106B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- tft
- amorphous silicon
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 58
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- -1 -Si-Cu Chemical class 0.000 description 1
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、アモルフアスシリコンを用いた半導
体装置とその製造方法に係り、特にオーミツク電
極部の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device using amorphous silicon and a method for manufacturing the same, and particularly relates to an improvement in an ohmic electrode portion.
近年、アモルフアスシリコン（ａ−Si）により
形成された薄膜電界効果トランジスタ（TFT）
が注目されている。特に、上記半導体薄膜が低温
で形成できるため、薄膜半導体装置を構成するた
めの基板が特に限定されず、又、従来の露光技
術、エツチング技術等のパターン形成法もそのま
ま使用でき大面積基板への集積化も可能であるな
どの利点を有するため、目的に応じて、多種多様
の構造の半導体装置が実現できる。これらの半導
体薄膜を用いた半導体装置の機能を十分に発揮す
るために、同一基板内にスイツチング素子や能動
回路素子として、上記半導体薄膜により形成され
たTFTを設けることが多い。これにより、半導
体薄膜を用いた半導体装置の機能的な集積化も可
能となり、その応用は極めて広くなる。
In recent years, thin film field effect transistors (TFTs) made of amorphous silicon (a-Si) have been developed.
is attracting attention. In particular, since the semiconductor thin film described above can be formed at low temperatures, the substrate for constructing the thin film semiconductor device is not particularly limited, and conventional pattern forming methods such as exposure technology and etching technology can be used as is, making it possible to form large-area substrates. Since it has advantages such as being able to be integrated, semiconductor devices with a wide variety of structures can be realized depending on the purpose. In order to fully exhibit the functions of semiconductor devices using these semiconductor thin films, TFTs formed from the above semiconductor thin films are often provided as switching elements or active circuit elements within the same substrate. This makes it possible to functionally integrate semiconductor devices using semiconductor thin films, and its applications become extremely wide-ranging.
第１図および第２図は従来のTFTの２つの基
本構造を概略的に示す図である。これらの図にお
いて、１は基板、２はａ−Si膜、３はゲート絶縁
膜、４はゲート電極、５，６はそれぞれソース、
ドレイン電極である。第１図のものはａ−Si膜２
の同じ面側にゲート電極とソース電極５およびド
レイン電極６が設けられ、第２図のものはａ−Si
膜２の下面側にゲート電極４、上面側にソース電
極５およびドレイン電極６が設けられている。こ
れらのTFTは結晶シリコンを用いたいわゆる
MOSFETと類似の電気的特性を示すが、
MOSFETとの動作原理の根本的な違いは、トラ
ンジスタのチヤンネルのしや断条件が、
MOSFETではPN接合の逆方向特性を利用する
のに対し、TFTではａ−Si膜２の高抵抗を利用
する点である。 FIGS. 1 and 2 are diagrams schematically showing two basic structures of conventional TFTs. In these figures, 1 is a substrate, 2 is an a-Si film, 3 is a gate insulating film, 4 is a gate electrode, 5 and 6 are sources, respectively.
This is the drain electrode. The one in Figure 1 is a-Si film 2.
A gate electrode, a source electrode 5, and a drain electrode 6 are provided on the same side of the
A gate electrode 4 is provided on the lower surface of the film 2, and a source electrode 5 and a drain electrode 6 are provided on the upper surface. These TFTs are made of crystalline silicon.
Shows similar electrical characteristics to MOSFETs, but
The fundamental difference in operating principle from MOSFET is that the transistor channel conditions are
The MOSFET uses the reverse direction characteristic of the PN junction, whereas the TFT uses the high resistance of the a-Si film 2.
チヤンネルの導通状態は共に、電界効果による
半導体表面の反転あるいはキヤリア蓄積を利用す
る。従つて、これらのTFTを構成するためには、
ａ−Si膜２の非導通状態での抵抗がチヤンネル形
成時の抵抗に比べ十分高いことが必要である。 Both channel conduction states utilize inversion or carrier accumulation on the semiconductor surface due to field effects. Therefore, to configure these TFTs,
It is necessary that the resistance of the a-Si film 2 in a non-conducting state is sufficiently higher than the resistance during channel formation.
なお、第１図、第２図のTFTにおいて、ソー
ス電極５、ドレイン電極６とａ−Si膜２のコンタ
クト部に不純物ドープにより抵抗を下げたａ−Si
膜を設けて、良好なオーミツクコンタクトをとり
TFT特性を向上させる場合もある。又、基板１
が導電性材料であるときは、その表面に絶縁層を
設けて絶縁性基板として用いる。 In addition, in the TFTs shown in FIGS. 1 and 2, the contact portions between the source electrode 5, the drain electrode 6, and the a-Si film 2 are doped with impurities to lower the resistance.
A film is provided to ensure good ohmic contact.
It may also improve TFT characteristics. Also, substrate 1
When is a conductive material, an insulating layer is provided on its surface and used as an insulating substrate.
ところで、ａ−Siを用いたTFTでは、Ｐチヤ
ンネル及びＮチヤンネルのTFT動作が可能であ
るが、電界効果移動度がＮチヤンネルの方が１〜
２桁大きいことから、通常Ｎチヤンネル動作とし
て利用されることが多い。この場合、ソース、ド
レイン電極の材料としてはAlを用いる場合が多
い。しかしながら、Alを電極材料とする場合、
第３図に示すような非オーミツク特性を示し、と
きには破線のようにヒステリシス特性を示すこと
がある。このような非オーミツク特性は、Ｐをド
ープしたn+型ａ−Si膜を電極下地として形成する
ことによりかなり改善されるが、それでも非オー
ミツク特性となる場合がある。このような特性
は、主にａ−Si TFTを製造する過程での熱処
理、汚染等が原因と考えられる。良好な特性のａ
−Si TFTを得るためには、従つて十分に管理さ
れた製造工程が必要であるが、同一条件と思われ
る製造工程管理の下でも、TFTが良好な特性を
示すとは限らないことが実験的に明らかになつて
いる。 By the way, in TFT using a-Si, P channel and N channel TFT operation is possible, but the field effect mobility of N channel is 1~1.
Since it is two orders of magnitude larger, it is usually used for N-channel operation. In this case, Al is often used as the material for the source and drain electrodes. However, when using Al as the electrode material,
It exhibits non-ohmic characteristics as shown in FIG. 3, and sometimes exhibits hysteresis characteristics as shown by the broken line. Although such non-ohmic characteristics can be considerably improved by forming a P-doped n + -type a-Si film as the electrode base, non-ohmic characteristics may still occur. Such characteristics are thought to be mainly caused by heat treatment, contamination, etc. during the process of manufacturing the a-Si TFT. good characteristics a
-In order to obtain Si TFTs, a well-controlled manufacturing process is required, but experiments have shown that even under the same manufacturing process control conditions, TFTs do not necessarily exhibit good characteristics. It is becoming clear that
本発明の目的は、ａ−Si膜を用いた素子のオー
ミツク電極部の特性改善を図つた半導体装置を提
供することにある。
An object of the present invention is to provide a semiconductor device in which the characteristics of an ohmic electrode portion of an element using an a-Si film are improved.
本発明は、ａ−Si膜を用いたTFTのソース、
ドレインのオーミツク電極の下地層として、不純
物ドープのn+型ａ−Si膜とMo膜の積層膜を介在
させることを特徴とする。
The present invention provides a TFT source using an a-Si film,
A feature is that a laminated film of an impurity-doped n + type a-Si film and a Mo film is interposed as the underlying layer of the drain ohmic electrode.
本発明によれば、n+型ａ−Si膜とMo膜からな
る下地層を設けることにより、ａ−Si膜に対する
オーミツク電極の特性は優れたものとなり、
TFT等の素子に適用して安定した素子特性が得
られる。
According to the present invention, by providing a base layer consisting of an n + type a-Si film and a Mo film, the properties of the ohmic electrode with respect to the a-Si film are excellent.
Stable device characteristics can be obtained when applied to devices such as TFT.
第４図は本発明の一実施例のTFTを示す断面
図である。１１はガラス基板等の絶縁性基板であ
り、この上にゲート電極１２を形成した後、全面
にゲート絶縁膜となるSiO2膜１３を設け、この
上にアンドープａ−Si膜１４を堆積し、Al膜に
よるソース電極１７1およびドレイン電極１７2を
形成している。ソース電極１７1およびドレイン
電極１７2の下地層として、これらとａ−Si膜１
４との間にＰドープのn+型ａ−Si膜１５とMo膜
１６の積層膜を介在させている。Mo膜１６は、
余り厚くすると応力によるはがれが生ずるため、
例えばａ−Si膜１４と１５の合計厚みに対して1/
２以下の厚みにすることが好ましい。
FIG. 4 is a sectional view showing a TFT according to an embodiment of the present invention. 11 is an insulating substrate such as a glass substrate, and after forming a gate electrode 12 on this, a SiO 2 film 13 serving as a gate insulating film is provided on the entire surface, and an undoped a-Si film 14 is deposited on this. A source electrode 17 1 and a drain electrode 17 2 are formed of an Al film. These and the a-Si film 1 are used as a base layer for the source electrode 17 1 and the drain electrode 17 2 .
A laminated film of a P-doped n + type a-Si film 15 and a Mo film 16 is interposed between the film and the film 4 . The Mo film 16 is
If it is too thick, it will peel off due to stress, so
For example, the total thickness of a-Si films 14 and 15 is 1/
The thickness is preferably 2 or less.
次にこのTFTの具体的な製造工程を第５図ａ
〜ｄを参照して説明する。絶縁性基板１１に750
Åのゲート電極１２を所定パターンで形成した
後、全面を2500ÅのSiO2膜１３でおおい、この
上にプラズマ分解法でアンドープａ−Si膜１４を
4000Å堆積し、続いて500ÅのＰドープn+型ａ−
Si膜１５を堆積し、更にスパツタ法により500Å
のMo膜１６を蒸着するａ。次にPEP工程によ
り、Mo膜１６、ａ−Si膜１５および１４の３層
積層膜を素子領域にのみ残してパターニングする
ｂ。次に全面に1μｍのAl膜１７を蒸着するｃ。
そしてPEP工程によりこのAl膜１７およびMo膜
１６をエツチングしてソース電極１７1およびド
レイン電極１７2を形成し、最後にこれらソース
電極１７1およびドレイン電極１７2をマスクとし
てチヤンネル領域上に残つているn+型ａ−Si膜１
５をエツチング除去して完成するｄ。 Next, the specific manufacturing process of this TFT is shown in Figure 5a.
This will be explained with reference to d. 750 on insulating substrate 11
After forming a gate electrode 12 with a thickness of 2500 Å in a predetermined pattern, the entire surface is covered with a SiO 2 film 13 with a thickness of 2500 Å, and an undoped a-Si film 14 is formed on this using a plasma decomposition method.
4000 Å deposited followed by 500 Å P-doped n + type a-
A Si film 15 is deposited, and then 500Å is deposited by sputtering method.
Depositing a Mo film 16 of a. Next, the three-layer laminated film of the Mo film 16, the a-Si films 15 and 14 is patterned by a PEP process, leaving it only in the element region b. Next, a 1 μm thick Al film 17 is deposited on the entire surface c.
Then, the Al film 17 and the Mo film 16 are etched by a PEP process to form a source electrode 17 1 and a drain electrode 17 2 .Finally, the source electrode 17 1 and the drain electrode 17 2 are used as masks to remain on the channel region. n + type a-Si film 1
5 is completed by etching away d.
こうして得られたTFTの特性評価を行つた結
果、優れた特性を示すことが確認された。第６図
はその電圧−電流特性であり、電流の立上り部分
で良好なオーミツク特性を示している。またヒス
テリシスは現われず、相互コンダクタンスgmも
従来のTFTに比べて１桁程度大きいものとなつ
ている。 As a result of evaluating the characteristics of the TFT thus obtained, it was confirmed that it exhibited excellent characteristics. FIG. 6 shows its voltage-current characteristics, showing good ohmic characteristics at the rising edge of the current. Further, hysteresis does not appear, and the mutual conductance gm is about one order of magnitude larger than that of conventional TFTs.
第７図は本発明の手法を抵抗素子に応用した参
考例である。その製造工程を説明すると次のとお
りである。絶縁性基板２１上にSiH4のグロー放
電分解法により、不純物をドープしないａ−Si膜
２２を3000Å、続いてＰドープn+型ａ−Si膜２３
を500Å堆積させる。しかる後、Siエツチングに
より所望の抵抗素子パターンを形成し、厚さ1000
ÅのMo膜２４、続いて厚さ5000ÅのAl膜２５を
真空蒸着法にて堆積する。そして、パターニング
法により、AlとMoをリン酸系のエツチング液に
より同時にエツチングし、端子電極２５1，２５2
を形成してこの電極パターンをマスクとして、Ｐ
ドープａ−Si膜２３をCDE法にてエツチングし
て抵抗素子を完成させる。 FIG. 7 is a reference example in which the method of the present invention is applied to a resistance element. The manufacturing process will be explained as follows. An a-Si film 22 not doped with impurities is formed on an insulating substrate 21 to a thickness of 3000 Å using a SiH 4 glow discharge decomposition method, and then a P-doped n + type a-Si film 23 is formed on the insulating substrate 21.
Deposit 500Å. After that, the desired resistance element pattern is formed by Si etching, and the thickness is 1000mm.
A Mo film 24 with a thickness of 5000 Å and subsequently an Al film 25 with a thickness of 5000 Å are deposited by vacuum evaporation. Then, using a patterning method, Al and Mo are simultaneously etched using a phosphoric acid-based etching solution, and the terminal electrodes 25 1 , 25 2 are etched at the same time.
and using this electrode pattern as a mask, P
The doped a-Si film 23 is etched using the CDE method to complete the resistor element.
このようにして試作された抵抗素子の電流電圧
特性を測定した結果、直線性に優れたものである
ことが明らかになつた。 As a result of measuring the current-voltage characteristics of the resistance element prototyped in this way, it was revealed that it had excellent linearity.
本発明は上記各実施例に限定されるものではな
い。例えば電極材料はAlに限らず、Al−Si、Al
−Si−Cu等の化合物でもよく、又、Al以外の
Au、Ni等一般的な金属でよい。ただし、Moと
同一工程でエツチングが行なえる材料が望まし
い。又、TFTの場合、第１図に示すような構造
のものであつてもよい。この場合にも、ソース、
ドレイン電極の下地層として上記実施例と同様に
n+型ａ−Si膜とMo膜の積層膜を用いることで、
上記実施例と同様の効果が得られる。 The present invention is not limited to the above embodiments. For example, the electrode material is not limited to Al, but also Al-Si, Al
It may be a compound such as -Si-Cu, or it may be a compound other than Al.
Common metals such as Au and Ni may be used. However, it is desirable to use a material that can be etched in the same process as Mo. Further, in the case of TFT, it may have a structure as shown in FIG. In this case too, the source,
As the base layer of the drain electrode, as in the above example.
By using a laminated film of n + type a-Si film and Mo film,
The same effects as in the above embodiment can be obtained.
第１図および第２図は従来のTFTの代表的構
造を示す図、第３図は従来のTFTの電圧−電流
特性例を示す図、第４図は本発明の一実施例の
TFTの構造を示す図、第５図ａ〜ｄはその製造
工程を示す図、第６図は得られたTFTの電圧−
電流特性を示す図、第７図は参考例の抵抗素子の
構造を示す図である。
１１……絶縁性基板、１２……ゲート電極、１
３……SiO2膜、１４……アンドープａ−Si膜、
１５……Ｐドープn+型ａ−Si膜、１６……Mo
膜、１７……Al膜、１７1……ソース電極、１７2
……ドレイン電極。
1 and 2 are diagrams showing a typical structure of a conventional TFT, FIG. 3 is a diagram showing an example of voltage-current characteristics of a conventional TFT, and FIG. 4 is a diagram showing an example of the voltage-current characteristics of a conventional TFT.
Figures showing the structure of the TFT, Figures 5a to 5d are diagrams showing the manufacturing process, and Figure 6 shows the voltage of the obtained TFT.
A diagram showing the current characteristics, and FIG. 7 is a diagram showing the structure of a resistive element as a reference example. 11... Insulating substrate, 12... Gate electrode, 1
3...SiO 2 film, 14... Undoped a-Si film,
15...P-doped n + type a-Si film, 16...Mo
Film, 17... Al film, 17 1 ... Source electrode, 17 2
...Drain electrode.
Claims (1)
コン膜の下面側または上面側にゲート電極が形成
され、前記アモルフアスシリコン膜の表面に選択
的にコンタクトするソース、ドレインのオーミツ
ク電極が形成された薄膜電界効果トランジスタを
備えた半導体装置において、前記オーミツク電極
の下地層として、不純物をドープしたn+型アモ
ルフアスシリコン膜とMo膜の積層膜を有するこ
とを特徴とするアモルフアスシリコン半導体装
置。1 A thin film in which a gate electrode is formed on the lower surface side or upper surface side of an amorphous silicon film formed on an insulating substrate, and source and drain ohmic electrodes are formed in selective contact with the surface of the amorphous silicon film. An amorphous silicon semiconductor device comprising a field effect transistor, characterized in that the ohmic electrode has a laminated film of an n + type amorphous silicon film doped with an impurity and a Mo film as a base layer of the ohmic electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7242882A JPS58190061A (en) | 1982-04-28 | 1982-04-28 | Amorphous silicon semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7242882A JPS58190061A (en) | 1982-04-28 | 1982-04-28 | Amorphous silicon semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58190061A JPS58190061A (en) | 1983-11-05 |
| JPH0546106B2 true JPH0546106B2 (en) | 1993-07-13 |
Family
ID=13489004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7242882A Granted JPS58190061A (en) | 1982-04-28 | 1982-04-28 | Amorphous silicon semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58190061A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5968975A (en) * | 1982-10-12 | 1984-04-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS59124162A (en) * | 1982-12-29 | 1984-07-18 | Sharp Corp | Thin film transistor |
| JPS6014473A (en) * | 1983-07-05 | 1985-01-25 | Asahi Glass Co Ltd | Electrode structure for thin film transistor |
| JPH0682839B2 (en) * | 1984-08-21 | 1994-10-19 | セイコー電子工業株式会社 | Manufacturing method of display panel |
| JPS61193485A (en) * | 1985-02-22 | 1986-08-27 | Matsushita Electric Ind Co Ltd | Manufacture of thin film transistor array |
| US4855806A (en) * | 1985-08-02 | 1989-08-08 | General Electric Company | Thin film transistor with aluminum contacts and nonaluminum metallization |
| US4933296A (en) * | 1985-08-02 | 1990-06-12 | General Electric Company | N+ amorphous silicon thin film transistors for matrix addressed liquid crystal displays |
| JPS6292371A (en) * | 1985-10-18 | 1987-04-27 | Hitachi Ltd | Thin-film transistor and manufacture thereof |
| JPS6490560A (en) * | 1987-10-01 | 1989-04-07 | Casio Computer Co Ltd | Thin-film transistor |
| US5188974A (en) * | 1987-10-31 | 1993-02-23 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4868171A (en) * | 1971-12-20 | 1973-09-17 | ||
| JPS50125683A (en) * | 1974-03-20 | 1975-10-02 | ||
| JPS51147290A (en) * | 1975-06-13 | 1976-12-17 | Nec Corp | Semiconductor device |
| JPS5687364A (en) * | 1979-12-18 | 1981-07-15 | Nec Corp | Semiconductor device |
| JPS56135938A (en) * | 1980-03-28 | 1981-10-23 | Yoshie Hasegawa | Fixed probe board |
-
1982
- 1982-04-28 JP JP7242882A patent/JPS58190061A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4868171A (en) * | 1971-12-20 | 1973-09-17 | ||
| JPS50125683A (en) * | 1974-03-20 | 1975-10-02 | ||
| JPS51147290A (en) * | 1975-06-13 | 1976-12-17 | Nec Corp | Semiconductor device |
| JPS5687364A (en) * | 1979-12-18 | 1981-07-15 | Nec Corp | Semiconductor device |
| JPS56135938A (en) * | 1980-03-28 | 1981-10-23 | Yoshie Hasegawa | Fixed probe board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58190061A (en) | 1983-11-05 |
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