JPS5950564A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS5950564A JPS5950564A JP16171682A JP16171682A JPS5950564A JP S5950564 A JPS5950564 A JP S5950564A JP 16171682 A JP16171682 A JP 16171682A JP 16171682 A JP16171682 A JP 16171682A JP S5950564 A JPS5950564 A JP S5950564A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulator layer
- insulator
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000010409 thin film Substances 0.000 title claims abstract description 6
- 239000012212 insulator Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 claims abstract description 5
- 238000000206 photolithography Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、プラズマ化学気相成長法により作製した非晶
質シリコン膜を半導体層として用いる薄膜トランジスタ
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a thin film transistor using an amorphous silicon film produced by plasma chemical vapor deposition as a semiconductor layer.
従来例の構成とその問題点
従来、薄膜トランジスタ（以下ＴＰＴと云う）は、非晶
質シリコン膜（以下ａ−８ｉ膜と云う）を半導体層とし
て用いる場合、第１図に示す如く絶縁基板１上に、ゲー
ト電極２．絶縁体層３．ａ−８ｉ半導体層４をこの順序
に形成し、最後にソース。Conventional structure and its problems Conventionally, when a thin film transistor (hereinafter referred to as TPT) uses an amorphous silicon film (hereinafter referred to as A-8I film) as a semiconductor layer, it is formed on an insulating substrate 1 as shown in FIG. , gate electrode 2. Insulator layer 3. The a-8i semiconductor layer 4 is formed in this order, and finally the source.
ドレイン電極５を設けた構成を有している。ａ−８ｉ層
４としては、ソース、ドレイン電極５とオーミックコン
タクトを取るために、不純物をａ−Ｓｉ層層中中拡散す
る場合もある。It has a structure in which a drain electrode 5 is provided. For the a-8i layer 4, impurities may be diffused into the a-Si layer in order to establish ohmic contact with the source and drain electrodes 5.
上記構成の大きｌ欠点は、ａ−３ｉ層４の表面が、ＴＰ
Ｔを形成する間外気にさらさｆるという点である。一般
に、プラズマ化学気相成長法（以下プラズマＣｖＤ法と
云う）で製膜さ扛たａ−８ｉ層は、単結晶Ｓｉに比較し
て多孔性であるため表面積が大きくなり、雰囲気の影響
を受けやすい。したがって、電極とのコンタクトのオー
ミック性、またａ−３ｉそのものの物性の経時変化等に
より、ＴＰＴ素子への悪影響がみらｎる。このため、写
囲気の影響を出来る限り小さくしたＴＰＴ特性を得るに
は、なんらかの形でＴＦＴ形成中、ａ−３ｉ表面を保護
する必要がある。The major drawback of the above structure is that the surface of the a-3i layer 4 is
The point is that it is exposed to outside air while forming the T. In general, the A-8I layer formed by plasma chemical vapor deposition (hereinafter referred to as plasma CVD) is more porous than single-crystal Si, so its surface area is larger and it is less affected by the atmosphere. Cheap. Therefore, the TPT element is adversely affected by the ohmic nature of the contact with the electrode and by changes in the physical properties of a-3i itself over time. Therefore, in order to obtain TPT characteristics in which the influence of photoreflection is minimized, it is necessary to protect the a-3i surface in some way during TFT formation.
発明の目的
本発明はこのような点に鑑みて成さ几たもので、ａ−３
ｉ層表面への悪影響を除去したＴＰＴの製造方法を提供
するものである。Purpose of the Invention The present invention has been made in view of the above points, and a-3
The present invention provides a method for manufacturing TPT that eliminates adverse effects on the surface of the i-layer.
発明の構成
不発明のＴＦＴの製造方法は、少なくともゲート電極が
形成さｎたガラス絶縁基板上に、プラズマＣＶＤ法で第
１の絶縁体層、ａ−８ｉ層、第２の絶縁体層を連続して
形成する第１の工程と、第２の絶縁体層をフォトリソグ
ラフィにより所望の形状にバターニングする第２の工程
と、バターニングした第２の絶縁体層をマスクにしてａ
−８ｉ層をそｎと同一形状にエツチングする第３の工程
と、第２の絶縁体層に２個の開孔部を設け、この開孔部
を介してａ−３ｉ層にソース、ドレイン電極を形成する
第４の工程の各工程を含むものである。Structure of the Invention The method for manufacturing a TFT according to the invention includes sequentially forming a first insulating layer, an a-8i layer, and a second insulating layer by a plasma CVD method on a glass insulating substrate on which at least a gate electrode is formed. a second step of patterning the second insulator layer into a desired shape by photolithography; and a second step of patterning the second insulator layer into a desired shape by photolithography.
A third step of etching the -8i layer into the same shape as that of the second insulator layer, and forming two openings in the second insulating layer and connecting the source and drain electrodes to the a-3i layer through these openings. This includes each step of the fourth step of forming.
徴は、少なくともゲート電極２を設けたガラス基板１上
に、プラズマＣＶＤ法により絶縁体層３、ａ−３ｉ層４
、さらに絶縁体層６を真空を破らず連続して形成するこ
とにある。さらに、本発明の第２の特徴は、ＴＦＴを形
成する上で、ａ−３ｉ層４を所定の形状にバターニング
する際、ａ−３ｉ層４上の絶縁体層６をあらかじめバタ
ーニングし、そ′ｉ′Ｌをマスクにして、ａ−８ｉ層４
を絶縁体層６と同一形状にエツチングすることにある。The characteristic is that an insulator layer 3 and an a-3i layer 4 are formed by plasma CVD on a glass substrate 1 provided with at least a gate electrode 2.
Furthermore, the purpose is to form the insulating layer 6 continuously without breaking the vacuum. Furthermore, the second feature of the present invention is that when patterning the a-3i layer 4 into a predetermined shape in forming a TFT, the insulating layer 6 on the a-3i layer 4 is buttered in advance, Using that'i'L as a mask, a-8i layer 4
The purpose is to etch it into the same shape as the insulating layer 6.
実施例の説明
以下、本発明の実施例について図面を参照して詳細に説
明する。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第３図（Ａ）に示す如く少くともゲート電極２を設けた
ガラス基板１上に、絶縁体層３．ａ−３ｉ層４゜絶縁体
層６の３層を真空を破らず連続してプラズマＣＶＤ法で
製膜し、第３図（Ｂ）に示す如く最終製膜した絶縁体層
６を通常のフォ） ｌ）ソグラフィを用いてバターニン
グする。絶縁体層３，６としては、二酸化シリコンある
いはチン化シリコンを用いる。ａ−３ｉ層４上の絶縁体
層６のフォトリソグラフィにおいて、絶縁体層６が二酸
化シリコンの場合は、フォトレジストでマスクし、フッ
酸とフン化アンモニウムの混液（以下ＢＨＦと略丁）で
エツチングすることか可能である。寸だ、絶縁体層６と
してチン化シリコンを使用する場合、ＣＶＤ法で形成し
たチン化シリコンは、ＢＨＦでエツチング出来ないが、
プラズマＣＶＤで形成したチン化シリコンは、ＢＨＦに
よってエツチング可能であるため、通常のフォトリング
ラフィを使用できる。次に、絶縁体６上のレジスト７を
除去した後、この絶縁体層６をマスクにしてａ−８ｉ層
４をエツチングする。エツチング液としては、ＫｏＨあ
るいはＮａＯＨの水溶液、またはＡ Ｐ Ｗ （Ａｗｉ
ｎｅＰｙｒｏｃａｔｅｃｈｏｌ Ｗａｔｅｒ ） ｆ
用いる。ＮａＯＨ２０ダに対しＨ２Ｏ１００ｃｃのＮａ
ＯＨ水溶液を使用する場合、水溶液が６５℃〜７５℃で
ａ−３ｉ層のエツチングレートは５０〜１０Ｑ八／ｓｅ
ｃテあった。ａ−８ｉ層のエツチングの際、マスクとし
て用いる絶縁体層は、上述のエツチング液に侵さｎ：Ｚ
いため、ａ−８ｉ層だけの選択エツチングが可能である
。第３図（Ｃ）に絶縁体層６をマスクにして、エツチン
グしたａ−８ｉ層４の断面図を示す。さらに、第３図（
Ｄ）に示す如くソース、ドレイン電極を形成するため、
ａ−３ｉ層４上の絶縁体層６の一部と、ゲート電極引き
出しのために絶縁体層３の一部をフォトリングラフィで
取り除く。このとき、はじめてＴＦＴに関与する部分の
ａ−３ｉ層４の表面８が露出する。As shown in FIG. 3(A), an insulating layer 3. Three layers of the a-3i layer 4° insulator layer 6 are successively formed by plasma CVD without breaking the vacuum, and the final formed insulator layer 6 is deposited using a normal photoform as shown in FIG. 3(B). ) l) Buttering using lithography. As the insulator layers 3 and 6, silicon dioxide or silicon chloride is used. In the photolithography of the insulator layer 6 on the a-3i layer 4, if the insulator layer 6 is made of silicon dioxide, it is masked with a photoresist and etched with a mixed solution of hydrofluoric acid and ammonium fluoride (hereinafter abbreviated as BHF). It is possible to do so. When using silicon nitride as the insulator layer 6, silicon nitride formed by CVD cannot be etched with BHF.
Since silicon nitride formed by plasma CVD can be etched with BHF, ordinary photolithography can be used. Next, after removing the resist 7 on the insulator 6, the a-8i layer 4 is etched using the insulator layer 6 as a mask. As an etching solution, an aqueous solution of KoH or NaOH, or an aqueous solution of A P W (Awi
nePyrocatechol Water) f
use 100cc of H2O for 20 da of NaOH
When using an OH aqueous solution, the etching rate of the a-3i layer is 50 to 10Q8/se when the aqueous solution is 65°C to 75°C.
There was cte. During etching of the a-8i layer, the insulator layer used as a mask is eroded by the above-mentioned etching solution, and the n:Z
Therefore, selective etching of only the a-8i layer is possible. FIG. 3C shows a cross-sectional view of the a-8i layer 4 etched using the insulator layer 6 as a mask. Furthermore, Figure 3 (
To form source and drain electrodes as shown in D),
A part of the insulator layer 6 on the a-3i layer 4 and a part of the insulator layer 3 for drawing out the gate electrode are removed by photolithography. At this time, the surface 8 of the a-3i layer 4 that is involved in the TFT is exposed for the first time.
葦だａ−８ｉ層４上の絶縁体層６を、ＢＨＦでエツチン
グしているため、ａ−８ｉ層４上に出来た酸化物もこの
エツチング液で同時に除去できるという効果をもつ。ソ
ース、ドレイン電極を設ける前にａ−８ｉのエツチング
液で、ａ−８ｉ層４の表面８に出来た酸化物を取り除く
ためのエツチングを行い、ａ−８ｉ層４の清浄な面を露
出させ、この上にＡβ膜を蒸着あるいはスパッターで設
け、所定の形状にエツチングして、第２図の工うなａ−
３ｉ層を半導体層として用いたＴＦＴｉ形成する。Since the insulator layer 6 on the A-8i layer 4 is etched with BHF, the oxide formed on the A-8i layer 4 can also be removed at the same time with this etching solution. Before providing the source and drain electrodes, etching is performed using an A-8I etching solution to remove the oxide formed on the surface 8 of the A-8I layer 4, exposing the clean surface of the A-8I layer 4. An Aβ film is deposited on top of this by vapor deposition or sputtering, and etched into a predetermined shape.
A TFTi using the 3i layer as a semiconductor layer is formed.
以上のように、本発明の方法によると、ＴＰＴの形成中
にａ−３ｉ層の表面が露出さｎることがないため、フォ
トリングラフィでパターニングする際に薬品に対して保
護さ几、雰囲気に対して安定したＴＦＴを形成すること
が可能である。さらに、ａ−３ｉ層４上の絶縁体層６を
マスクにして、ａ−８ｉ層４をパターニング出来、フｉ
トレジストを使用する場合に比較し、密着したマスクに
なり過多のエツチングのないパターニングが可能である
。そして、第２図に示すようにＡｄのソース、ドレイン
電極５の形成を、ａ−８ｉ層４の表面が全く露出しない
、ｒ、うにパターニングすると、最終のａ−３ｉ層の保
護膜ｆ：も兼用することが可能となる。丑だ、ソース、
ドレイン電極のエツチングの際に発生する発生期の水素
によるａ−８ｉ層４への影響も、絶縁体層６で保護さて
しているため問題とならない。As described above, according to the method of the present invention, the surface of the a-3i layer is not exposed during the formation of TPT, so it is protected from chemicals during patterning by photolithography. It is possible to form a TFT that is stable against. Furthermore, using the insulator layer 6 on the a-3i layer 4 as a mask, the a-8i layer 4 can be patterned, and the film can be patterned.
Compared to the case where a resist is used, the mask is in close contact and patterning without excessive etching is possible. Then, as shown in FIG. 2, when the Ad source and drain electrodes 5 are patterned in such a way that the surface of the a-8i layer 4 is not exposed at all, the final protective film f of the a-3i layer is also formed. It becomes possible to use it for both purposes. It's ox, sauce.
The influence of nascent hydrogen generated during etching of the drain electrode on the a-8i layer 4 does not pose a problem since it is protected by the insulator layer 6.
この工すにして形成したＴＰＴの特性と、ａ−８ｉ層４
の表面を露出して形成したＴＰＴの特性の一例を、第４
図（Ａ）と第４図（Ｂ）に示す。チャンネル長２０ μ
ｍ 、 ｆ ヤ７ネル幅１５０ μｍ 、 ａ−８ｉ層
４゜上部絶縁体層６と下部絶縁体層３の膜厚がそｎぞ
４ｎ３ｏｏＯ〜４０００人、３０００〜４０００人。The characteristics of TPT formed using this process and the a-8i layer 4
An example of the characteristics of TPT formed by exposing the surface of
This is shown in Figure (A) and Figure 4 (B). Channel length 20μ
m, f layer 7 channel width 150 μm, a-8i layer 4°, film thickness of upper insulator layer 6 and lower insulator layer 3 are similar.
4n3ooO~4000 people, 3000~4000 people.
７ｏ○０〜８０００人の場合の特性である。図はソース
、ドレイン間の電圧ＶＳＩ）を一定にして、ゲート電圧
Ｖｇ を−１０Ｖ〜４０Ｖ捷で変化させた時のソース、
ドレイン間を流ｎる電流１ｓｎ ｋ測定したものである
が、不発明の方法によって形成したＴＰＴの特性は、従
来のＴＰＴの特性に較べて、ＶＳＤが従来の３０Ｖに対
して１Ｑ■であるにもがかわらず、ＩＳＤのゲート電圧
ｖｇに対する変化は太すク、特性の向上がみらｎる。This is the characteristic for the case of 7o○0 to 8000 people. The figure shows the source when the voltage (VSI) between the source and drain is kept constant and the gate voltage Vg is varied from -10V to 40V.
The current flowing between the drains was measured at 1snk, and the characteristics of the TPT formed by the uninvented method were as follows: compared to the characteristics of the conventional TPT, the VSD was 1Q■ compared to the conventional 30V. However, the change in the ISD gate voltage vg becomes thicker and the characteristics are improved.
発明の詳細
な説明したように、不発明の製造方法にょｎば、ＴＰＴ
素子の形成中、ａ−３ｉ層の表面が絶縁体層で保護さｎ
ているため取り扱いが容易であり、しかも従来のＴＰＴ
の形成中にａ−８ｉ層の表面が露出するものに較べ、よ
り向上した特性が得らｎる。また雰囲気に対しても、絶
縁体層によって保護さ几ているため、安定した特性のＴ
ＦＴを製造することが可能となる。As described in detail of the invention, the inventive method of manufacturing TPT
During device formation, the surface of the a-3i layer is protected by an insulating layer.
It is easy to handle because it is
Compared to the case in which the surface of the a-8i layer is exposed during the formation of the layer, more improved characteristics can be obtained. Also, since it is protected from the atmosphere by an insulating layer, it has stable characteristics.
It becomes possible to manufacture FT.
第１図は従来の方法により製作したＴＰＴの断面図、第
２図は本発明の方法によって製作したＴＰＴの一例を示
す断面図、第３図（Ａ）〜第３図（Ｄ）は不発明の各製
造工程を説明するだめの断面図、第４図（Ａ）、 （Ｂ
）はそｎぞｎ本発明の方法と従来の方法によって製作し
たＴＰＴのゲート電圧とソース。
ドレイン電流との関係を示す特性図である。
１・・・・・・ガラス絶縁基板、２・・・・・・ゲート
電極、３・・・・・・絶縁体層、４・・・・・・ａ−８
ｉ層、５・・・・・・ソース・ドレイン電極、６・・・
・・・絶縁体層、７・・・・・・レジスト。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
、：５．５
？
第２図
第３図
第３図
（Ｃλ
と
（ｐ〕Fig. 1 is a sectional view of a TPT manufactured by a conventional method, Fig. 2 is a sectional view showing an example of a TPT manufactured by the method of the present invention, and Figs. 3(A) to 3(D) are a non-inventive one. 4 (A), (B
) are the gate voltage and source of TPTs manufactured by the method of the present invention and the conventional method. FIG. 3 is a characteristic diagram showing the relationship with drain current. DESCRIPTION OF SYMBOLS 1...Glass insulating substrate, 2...Gate electrode, 3...Insulator layer, 4...A-8
i layer, 5...source/drain electrode, 6...
...Insulator layer, 7...Resist. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure: 5.5? Figure 2 Figure 3 Figure 3 (Cλ and (p)
Claims (1)
、プラズマ化学気相成長法で第１の絶縁体層、非晶質シ
リコン層、第２の絶縁体層を連続して形成する第１の工
程と、前記第２の絶縁体層をフォトリングラフィにより
所望の形状にパターニングする第２の工程と、パターニ
ングした前記第２の絶縁体層をマスクにして前記非晶質
シリコン層をそｎと同一形状にエツチングする第３の工
程と、前記第２の絶縁体層に２個の開孔部を設け、この
開孔部を介して前記非晶質シリコン層上にソース、ドレ
イン電極を形成する第４の工程の各工程を含む薄膜トラ
ンジスタの製造方法。A first step of successively forming a first insulator layer, an amorphous silicon layer, and a second insulator layer by plasma chemical vapor deposition on a glass insulating substrate on which at least a gate electrode is formed. and a second step of patterning the second insulator layer into a desired shape by photolithography, and patterning the amorphous silicon layer in the same manner as the patterned second insulator layer. a third step of etching into a shape; and a third step of forming two openings in the second insulating layer and forming source and drain electrodes on the amorphous silicon layer through the openings. A method for manufacturing a thin film transistor including each step of step 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16171682A JPS5950564A (en) | 1982-09-16 | 1982-09-16 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16171682A JPS5950564A (en) | 1982-09-16 | 1982-09-16 | Manufacture of thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5950564A true JPS5950564A (en) | 1984-03-23 |
| JPH0351095B2 JPH0351095B2 (en) | 1991-08-05 |
Family
ID=15740516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16171682A Granted JPS5950564A (en) | 1982-09-16 | 1982-09-16 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950564A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183687A (en) * | 1985-02-08 | 1986-08-16 | 松下電器産業株式会社 | Manufacture of thin film transistor array |
| JPS61183972A (en) * | 1985-02-08 | 1986-08-16 | Matsushita Electric Ind Co Ltd | Manufacture of thin film semiconductor device |
| JPS61187272A (en) * | 1985-02-14 | 1986-08-20 | Matsushita Electric Ind Co Ltd | Thin-film field-effect transistor and manufacture thereof |
| US5173753A (en) * | 1989-08-10 | 1992-12-22 | Industrial Technology Research Institute | Inverted coplanar amorphous silicon thin film transistor which provides small contact capacitance and resistance |
| US5493129A (en) * | 1988-06-29 | 1996-02-20 | Hitachi, Ltd. | Thin film transistor structure having increased on-current |
| US5627088A (en) * | 1986-01-24 | 1997-05-06 | Canon Kabushiki Kaisha | Method of making a device having a TFT and a capacitor |
| JP2006100760A (en) * | 2004-09-02 | 2006-04-13 | Casio Comput Co Ltd | Thin-film transistor and its manufacturing method |
-
1982
- 1982-09-16 JP JP16171682A patent/JPS5950564A/en active Granted
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183687A (en) * | 1985-02-08 | 1986-08-16 | 松下電器産業株式会社 | Manufacture of thin film transistor array |
| JPS61183972A (en) * | 1985-02-08 | 1986-08-16 | Matsushita Electric Ind Co Ltd | Manufacture of thin film semiconductor device |
| JPS61187272A (en) * | 1985-02-14 | 1986-08-20 | Matsushita Electric Ind Co Ltd | Thin-film field-effect transistor and manufacture thereof |
| US5627088A (en) * | 1986-01-24 | 1997-05-06 | Canon Kabushiki Kaisha | Method of making a device having a TFT and a capacitor |
| US5493129A (en) * | 1988-06-29 | 1996-02-20 | Hitachi, Ltd. | Thin film transistor structure having increased on-current |
| US5821565A (en) * | 1988-06-29 | 1998-10-13 | Hitachi, Ltd. | Thin film transistor structure having increased on-current |
| US5173753A (en) * | 1989-08-10 | 1992-12-22 | Industrial Technology Research Institute | Inverted coplanar amorphous silicon thin film transistor which provides small contact capacitance and resistance |
| JP2006100760A (en) * | 2004-09-02 | 2006-04-13 | Casio Comput Co Ltd | Thin-film transistor and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0351095B2 (en) | 1991-08-05 |
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