JPS588230U - pulse delay circuit - Google Patents

pulse delay circuit

Info

Publication number
JPS588230U
JPS588230U JP1981102475U JP10247581U JPS588230U JP S588230 U JPS588230 U JP S588230U JP 1981102475 U JP1981102475 U JP 1981102475U JP 10247581 U JP10247581 U JP 10247581U JP S588230 U JPS588230 U JP S588230U
Authority
JP
Japan
Prior art keywords
pulse
delay
delay circuit
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1981102475U
Other languages
Japanese (ja)
Other versions
JPH0119471Y2 (en
Inventor
徳山　義夫
Original Assignee
日本ビクター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本ビクター株式会社 filed Critical 日本ビクター株式会社
Priority to JP1981102475U priority Critical patent/JPS588230U/en
Priority to US06/395,219 priority patent/US4490755A/en
Priority to DE3225584A priority patent/DE3225584C2/en
Priority to GB08219928A priority patent/GB2104703B/en
Priority to FR8212117A priority patent/FR2509507B1/en
Priority to KR828203068A priority patent/KR880002211B1/en
Publication of JPS588230U publication Critical patent/JPS588230U/en
Application granted granted Critical
Publication of JPH0119471Y2 publication Critical patent/JPH0119471Y2/ja
Granted legal-status Critical Current

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  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案回路の一実施例を示す回路図、第２図Ａ
−Ｅ及び第３図Ａ−Ｄは夫々第１図の動作説明用信号波
形図である。 １・・・入力端子、′２・・・単安定マルチバイブレー
タ（モノマルチ）、３・・・遅延回路、６・・・コンパ
レータ、８・・・フリップフロップ、９・・・出力端子
、Ｔｒ・・・スイッチングトランジスタ、ｖＲ・・・可
変抵抗器、Ｃ１・・・充放電用コンデンサ。Figure 1 is a circuit diagram showing an embodiment of the circuit of the present invention, Figure 2A
-E and FIGS. 3A to 3D are signal waveform diagrams for explaining the operation of FIG. 1, respectively. 1... Input terminal, '2... Monostable multivibrator (mono multi), 3... Delay circuit, 6... Comparator, 8... Flip-flop, 9... Output terminal, Tr. ...Switching transistor, vR...Variable resistor, C1...Charging/discharging capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力パルスの周期に略等しい遅延量可変範囲を有し該入
力パルスと同一の繰り返し周波数で所望の遅延量が付与
されたパルスを出力するパルス遅延回路において、上記
入力パルスを極めて短時間遅延する第１の遅延回路と、
該第１の遅延回路の出力遅延パルスが供給され該遅延パ
ルスにより充放電制御されるコンデンサの端子電圧を基
準電圧とレベル比較し、このレベル比較出力と該入力パ
ルス又はこれに位相同期したパルスとの論理和出力によ
り第１の安定状態ときれ、かつ、該遅延パルスにより第
２の安定状態とされるフリップフロップの出力端子より
遅延パルスを出力する第２の遅延回路とよりなり、該第
２の遅延回路内のコンデンサの時定数を可変制御するこ
とにより所望の遅延量が付与されたパルスを出力すると
共に最大遅延量を上記人力パルスの周期に略等しい値に
制限するよう構成したパルス遅延回路。In a pulse delay circuit that has a variable delay amount range that is approximately equal to the period of an input pulse and outputs a pulse with a desired amount of delay at the same repetition frequency as the input pulse, a pulse delay circuit that delays the input pulse for an extremely short time. 1 delay circuit;
The output delay pulse of the first delay circuit is supplied, and the terminal voltage of the capacitor whose charge and discharge are controlled by the delay pulse is compared in level with a reference voltage, and this level comparison output is compared with the input pulse or a pulse whose phase is synchronized therewith. a second delay circuit that outputs a delayed pulse from an output terminal of a flip-flop which is brought into a first stable state by the OR output of and which is brought into a second stable state by the delayed pulse; A pulse delay circuit configured to variably control the time constant of a capacitor in the delay circuit to output a pulse with a desired amount of delay and to limit the maximum amount of delay to a value approximately equal to the period of the human pulse. .
JP1981102475U 1981-07-09 1981-07-10 pulse delay circuit Granted JPS588230U (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP1981102475U JPS588230U (en) 1981-07-10 1981-07-10 pulse delay circuit
US06/395,219 US4490755A (en) 1981-07-09 1982-07-06 Recording and reproducing video signals at selectable different tape traveling speeds from plural video head pairs
DE3225584A DE3225584C2 (en) 1981-07-09 1982-07-08 Video signal recording and reproducing apparatus
GB08219928A GB2104703B (en) 1981-07-09 1982-07-09 Video recording and reproducing apparatus
FR8212117A FR2509507B1 (en) 1981-07-09 1982-07-09 RECORDING AND REPRODUCING APPARATUS FOR RECORDING AND REPRODUCING VIDEO SIGNALS AT DIFFERENT SPEEDS OF MOVING A BAND FROM SEVERAL PAIRS OF VIDEO HEADS
KR828203068A KR880002211B1 (en) 1981-07-09 1982-07-09 Tracking free-set correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981102475U JPS588230U (en) 1981-07-10 1981-07-10 pulse delay circuit

Publications (2)

Publication Number Publication Date
JPS588230U true JPS588230U (en) 1983-01-19
JPH0119471Y2 JPH0119471Y2 (en) 1989-06-06

Family

ID=29897118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981102475U Granted JPS588230U (en) 1981-07-09 1981-07-10 pulse delay circuit

Country Status (1)

Country Link
JP (1) JPS588230U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008017447A (en) * 2006-06-30 2008-01-24 O2 Micro Inc Variable frequency multi-phase oscillator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028966A (en) * 1973-07-13 1975-03-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028966A (en) * 1973-07-13 1975-03-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008017447A (en) * 2006-06-30 2008-01-24 O2 Micro Inc Variable frequency multi-phase oscillator

Also Published As

Publication number Publication date
JPH0119471Y2 (en) 1989-06-06

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