JPS6372936U - - Google Patents
Info
- Publication number
- JPS6372936U JPS6372936U JP16671786U JP16671786U JPS6372936U JP S6372936 U JPS6372936 U JP S6372936U JP 16671786 U JP16671786 U JP 16671786U JP 16671786 U JP16671786 U JP 16671786U JP S6372936 U JPS6372936 U JP S6372936U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- reference voltage
- turned
- voltage point
- delayed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000003111 delayed effect Effects 0.000 claims 12
- 238000010586 diagram Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は、この考案の位相比較器の第一実施例
を示す回路図、第２図は、この考案の位相比較器
と共に用いて好適なタイミング抽出回路を示す図
、第３図Ａ〜Ｋは、この考案の第一実施例の位相
比較器の動作説明に供するタイミングチヤート、
第４図は、この考案の位相比較器の第二実施例を
示す回路図、第５図は、この考案の位相比較器の
第三実施例を示す回路図である。
１１，１３…位相比較器の入力端子、２０…パ
ルス発生回路、２１，２３…論理積回路、２５…
インバータ、３０…遅延回路、３１…第一遅延素
子、３３…第二遅延素子、４０…制御信号発生回
路、４１…第一スイツチ素子、４３…第二スイツ
チ素子、４５…第三スイツチ素子、４７…第四ス
イツチ素子、５１…第一コンデンサ、５３…第二
コンデンサ、５５…第三コンデンサ、６１…出力
端子、１０１…コンデンサ、１０３…演算増幅器
。
FIG. 1 is a circuit diagram showing a first embodiment of the phase comparator of this invention, FIG. 2 is a diagram showing a timing extraction circuit suitable for use with the phase comparator of this invention, and FIGS. 3 A to K is a timing chart for explaining the operation of the phase comparator of the first embodiment of this invention,
FIG. 4 is a circuit diagram showing a second embodiment of the phase comparator of this invention, and FIG. 5 is a circuit diagram showing a third embodiment of the phase comparator of this invention. 11, 13... Input terminal of phase comparator, 20... Pulse generation circuit, 21, 23... AND circuit, 25...
Inverter, 30... Delay circuit, 31... First delay element, 33... Second delay element, 40... Control signal generation circuit, 41... First switch element, 43... Second switch element, 45... Third switch element, 47 ... Fourth switch element, 51... First capacitor, 53... Second capacitor, 55... Third capacitor, 61... Output terminal, 101... Capacitor, 103... Operational amplifier.
Claims (1)
はバースト状のデイジタル信号とから制御信号を
出力するための位相比較器において、 デイジタル信号に対する出力信号の位相の進み
及び遅れを表わす進みパルス及び遅れパルスを発
生するパルス発生回路と、 前記進みパルス及び遅れパルスの遅延パルスを
出力する遅延回路と、 第一及び第二基準電圧点間に設けられ前記進み
パルス及び遅延進みパルスのタイミング差と前記
遅れパルス及び遅延遅れパルスのタイミング差と
に対応して電圧レベルが変動される制御信号を出
力する制御信号出力回路と を具えたことを特徴とする位相比較器。 (2) 前記制御信号出力回路を、前記第一基準電
圧点に一方の端子が接続され前記進みパルスによ
つてオン・オフされる第一スイツチ素子、前記遅
延進みパルスによつてオン・オフされる第二スイ
ツチ素子、前記遅延遅れパルスによつてオン・オ
フされる第三スイツチ素子及び一方の端子が前記
第二基準電圧点に接続され前記遅れパルスによつ
てオン・オフされる第四スイツチ素子の直列回路
と、 前記第一及び第二スイツチ素子の接続点と前記
第二基準電圧点との間に接続された第一コンデン
サと、 前記第三及び第四スイツチ素子の接続点と前記
第二基準電圧点との間に接続された第二コンデン
サと、 前記第二及び第三スイツチ素子の接続点と前記
第二基準電圧点との間に接続された第三コンデン
サとを以つて構成したことを特徴とする実用新案
登録請求の範囲第１項記載の位相比較器。 (3) 前記第二基準電圧点をアースとしたことを
特徴とする実用新案登録請求の範囲第１項又は第
２項に記載の位相比較器。 (4) 前記第一基準電圧点を正の電圧点とし、前
記第二基準電圧点を該第一電圧点と同電圧で極性
が異なる負の電圧点とし、 前記制御信号出力回路を、前記正の電圧点に一
方の端子が接続され前記進みパルスによつてオン
・オフされる第一スイツチ素子、前記遅延進みパ
ルスによつてオン・オフされる第二スイツチ素子
、前記遅延遅れパルスによつてオン・オフされる
第三スイツチ素子及び前記負の電圧点に一方の端
子が接続され前記遅れパルスによつてオン・オフ
される第四スイツチ素子の直列回路と、 前記第一及び第二スイツチ素子の接続点と第三
基準電圧点との間に接続された第一コンデンサと
、 前記第三及び第四スイツチ素子の接続点と第三
基準電圧点との間に接続された第二コンデンサと
、 前記第二及び第三スイツチ素子の接続点に接続
された積分器と を以つて構成したことを特徴とする実用新案登録
請求の範囲第１項記載の位相比較器。 (5) 前記遅延回路を、前記進みパルスの遅延パ
ルスを出力する第一遅延素子と、前記遅れパルス
の遅延パルスを出力する第二遅延素子とを以つて
構成したことを特徴とする実用新案登録請求の範
囲第１〜第４項のいずれか１項に記載の位相比較
器。[Claims for Utility Model Registration] (1) In a phase comparator for outputting a control signal from an output signal from a voltage controlled oscillator and a continuous or burst digital signal, the phase lead of the output signal with respect to the digital signal. and a pulse generation circuit that generates lead pulses and lagging pulses representing lag; a delay circuit that outputs delayed pulses of the lead pulse and the lag pulse; and a pulse generating circuit that outputs the lead pulse and the delay pulse that are provided between the first and second reference voltage points, and the lead pulse and the delay pulse. A phase comparator comprising: a control signal output circuit that outputs a control signal whose voltage level is varied in response to a timing difference between an advanced pulse and a timing difference between the delayed pulse and the delayed delayed pulse. (2) The control signal output circuit includes a first switch element whose one terminal is connected to the first reference voltage point and is turned on and off by the lead pulse, and a first switch element which is turned on and off by the delayed lead pulse. a second switch element that is turned on and off by the delayed pulse, a third switch element that is turned on and off by the delayed pulse, and a fourth switch whose one terminal is connected to the second reference voltage point and which is turned on and off by the delayed pulse. a series circuit of elements; a first capacitor connected between a connection point between the first and second switch elements and the second reference voltage point; a connection point between the third and fourth switch elements and the second reference voltage point; a second capacitor connected between two reference voltage points; and a third capacitor connected between the connection point of the second and third switch elements and the second reference voltage point. A phase comparator according to claim 1, characterized in that: (3) The phase comparator according to claim 1 or 2 of the utility model registration claim, characterized in that the second reference voltage point is grounded. (4) The first reference voltage point is a positive voltage point, the second reference voltage point is a negative voltage point that is the same voltage as the first voltage point but has a different polarity, and the control signal output circuit is connected to the positive voltage point. a first switch element whose one terminal is connected to a voltage point of and is turned on and off by the lead pulse; a second switch element which is turned on and off by the delay lead pulse; and a second switch element which is turned on and off by the delay lead pulse; a series circuit of a third switch element that is turned on and off; and a fourth switch element that has one terminal connected to the negative voltage point and is turned on and off by the delayed pulse; and the first and second switch elements. a first capacitor connected between the connection point of the third and fourth switch elements and a third reference voltage point; a second capacitor connected between the connection point of the third and fourth switch elements and the third reference voltage point; 2. The phase comparator according to claim 1, further comprising an integrator connected to a connection point between said second and third switch elements. (5) Registration of a utility model characterized in that the delay circuit is configured with a first delay element that outputs a delayed pulse of the advanced pulse and a second delay element that outputs a delayed pulse of the delayed pulse. A phase comparator according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16671786U JPH0641392Y2 (en) | 1986-10-31 | 1986-10-31 | Phase comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16671786U JPH0641392Y2 (en) | 1986-10-31 | 1986-10-31 | Phase comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6372936U true JPS6372936U (en) | 1988-05-16 |
| JPH0641392Y2 JPH0641392Y2 (en) | 1994-10-26 |
Family
ID=31097962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16671786U Expired - Lifetime JPH0641392Y2 (en) | 1986-10-31 | 1986-10-31 | Phase comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0641392Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007088595A1 (en) * | 2006-01-31 | 2007-08-09 | Fujitsu Limited | Pll circuit and semiconductor integrated device |
-
1986
- 1986-10-31 JP JP16671786U patent/JPH0641392Y2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007088595A1 (en) * | 2006-01-31 | 2007-08-09 | Fujitsu Limited | Pll circuit and semiconductor integrated device |
| US7659760B2 (en) | 2006-01-31 | 2010-02-09 | Fujitsu Limited | PLL circuit and semiconductor integrated device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0641392Y2 (en) | 1994-10-26 |
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