JPS58135135U - Programmable delay signal generation circuit - Google Patents
Programmable delay signal generation circuitInfo
- Publication number
- JPS58135135U JPS58135135U JP3055882U JP3055882U JPS58135135U JP S58135135 U JPS58135135 U JP S58135135U JP 3055882 U JP3055882 U JP 3055882U JP 3055882 U JP3055882 U JP 3055882U JP S58135135 U JPS58135135 U JP S58135135U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- programmable delay
- signal
- output signal
- signal generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案によるプログラマブル信号遅延発生回
路の一実施例を示すブロック図である。
なお、図において、ＰＤＣはプログラマブルディレー回
路、ＡＤＣはＡ／Ｄコンバータ回路、Ｃ１Ｔはカウンタ
回路、ＮＧはＮＡＮＤゲート、Ｃ１Ｃは前記ＡＩＤコン
バータ回路、カウンタ回路、及びＮＡＮＤゲートを制御
する制御回路。
第２図は、本考案におけるプログラマブル信号遅延発生
の一例を説明するための波形図である。
ｉａはスタート信号、Ｏａ １．０ａ２ｙ Ｏａ３は遅
延時間Ｔｄ０．Ｔ、２．Ｔｄ３と遅延して出力される信
号例を示している。FIG. 1 is a block diagram showing an embodiment of a programmable signal delay generation circuit according to the present invention. In the figure, PDC is a programmable delay circuit, ADC is an A/D converter circuit, C1T is a counter circuit, NG is a NAND gate, and C1C is a control circuit that controls the AID converter circuit, the counter circuit, and the NAND gate. FIG. 2 is a waveform diagram for explaining an example of programmable signal delay generation in the present invention. ia is the start signal, Oa 1.0a2y Oa3 is the delay time Td0. T, 2. An example of a signal that is output with a delay of Td3 is shown.
Claims (1)
時間経過後出力信号が出力される回路において、電圧値
により信号の伝搬時間が制御されるプログラマブルディ
レー回路と、前記プログラマブルディレー回路の電圧値
を可変するＡ／Ｄコンバータ回路と、前記プログラマブ
ルディレー回路の出力信号の極性を反転しプログラマブ
ルディレー回路の入力端へ帰還し発振せしめるとともに
、帰還の０Ｎ１０ＦＦを制御するゲートと、前記プログ
ラマブルディレー回路と前記ゲートにて発振する出力信
号をカウントするカウンタ回路と、前記Ａ／Ｄコンバー
タ回路及びカウンタ回路の制御を行なう制御回路とで構
成し、信号伝搬遅延時間に対応するＡ／Ｄコンバータ回
路へのデータの設定と、カウンタ回路に対してカウント
パルス数を決定するデータの設定とにより所望の信号の
発生遅延時間を制御することを特徴とするプログラマブ
ル遅延信号発生回路。At least a programmable delay circuit in which the signal propagation time is controlled by a voltage value in a circuit that outputs an output signal after a preset time has elapsed from the application of the activation signal, and a voltage value of the programmable delay circuit is variable. an A/D converter circuit that inverts the polarity of the output signal of the programmable delay circuit and returns it to the input terminal of the programmable delay circuit to cause oscillation, and a gate that controls the feedback 0N10FF; a counter circuit that counts the output signal oscillated by the signal, and a control circuit that controls the A/D converter circuit and the counter circuit, and sets data to the A/D converter circuit corresponding to the signal propagation delay time. A programmable delay signal generation circuit, characterized in that the generation delay time of a desired signal is controlled by setting data for determining the number of count pulses in a counter circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3055882U JPS58135135U (en) | 1982-03-04 | 1982-03-04 | Programmable delay signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3055882U JPS58135135U (en) | 1982-03-04 | 1982-03-04 | Programmable delay signal generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58135135U true JPS58135135U (en) | 1983-09-10 |
Family
ID=30042267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3055882U Pending JPS58135135U (en) | 1982-03-04 | 1982-03-04 | Programmable delay signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58135135U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS498963A (en) * | 1972-05-25 | 1974-01-26 |
-
1982
- 1982-03-04 JP JP3055882U patent/JPS58135135U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS498963A (en) * | 1972-05-25 | 1974-01-26 |
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