JPS5888411U - AC signal generator - Google Patents
AC signal generatorInfo
- Publication number
- JPS5888411U JPS5888411U JP18419781U JP18419781U JPS5888411U JP S5888411 U JPS5888411 U JP S5888411U JP 18419781 U JP18419781 U JP 18419781U JP 18419781 U JP18419781 U JP 18419781U JP S5888411 U JPS5888411 U JP S5888411U
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- address signal
- counter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 14
- 239000000284 extract Substances 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Recording Measured Values (AREA)
- Circuit For Audible Band Transducer (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案信号発生器の一実施例のブロック系統図
、第2図は正弦波信号とデータとの関係を示す図、第3
図は第1図中メモリの具体的ブロック系統図である。
1・・・クロック信号発生器、2〜4・・・カウンタ、
5・・・リード・オンリ・メモリ、7・・・メモリ、8
・・・D/A変換器、9・・・中央処理制御装置、10
・・・DC成分除去回路、11・・・出力端子。Fig. 1 is a block system diagram of one embodiment of the signal generator of the present invention, Fig. 2 is a diagram showing the relationship between a sine wave signal and data, and Fig. 3 is a diagram showing the relationship between a sine wave signal and data.
The figure is a concrete block system diagram of the memory in FIG. 1. 1... Clock signal generator, 2-4... Counter,
5...Read-only memory, 7...Memory, 8
...D/A converter, 9...Central processing control unit, 10
...DC component removal circuit, 11...output terminal.
Claims (2)
ルスを供給され、外部からの制御信号にて分周比を可変
されて該制御信号に応じた分周比にて該クロックパルス
を分周する第1のカウンタと、該第1のカウンタの出力
を供給され該分、同化に応じた速度でアドレス信号を出
力する第2のカウンタと、求める交流信号の時間軸方向
に対する各レベルに夫為応じており該交流信号の−のレ
ベルに対して2種のデータにて構成されるデータを所定
周期分該アドレス信号に対応してメモリされており、該
アドレス信号の出力速度に応じた速度で該データを1組
とされてこれを時分割的に繰返しとり出すメモリ回路と
、該メモリ回路からのデータをD/A変換して交流信号
を得る回路とよりなる交流信号発生器。(1) A circuit that generates a clock pulse, which is supplied with the clock pulse, whose frequency division ratio is varied by an external control signal, and which divides the clock pulse at a frequency division ratio that corresponds to the control signal. a first counter; a second counter that is supplied with the output of the first counter and outputs an address signal at a speed corresponding to the assimilation; and a second counter that outputs an address signal at a speed corresponding to the assimilation; Data consisting of two types of data for the negative level of the AC signal is stored in memory corresponding to the address signal for a predetermined period, and is output at a speed corresponding to the output speed of the address signal. An alternating current signal generator comprising a memory circuit that repeatedly extracts a set of data in a time-division manner, and a circuit that converts the data from the memory circuit from D/A to obtain an alternating current signal.
アドレス信号を供給されるリード・オンリ・メモリと、
該アドレス信号に同期しており時間的にずれた2つのタ
イミングで該リード・オンリ・メモリからのデータのう
ちの一方のデータ及び他方のデータを夫々メモリする第
1及び第2のメモリと、該第2のメモリが該他方のデー
タをメモリする際に該第1のメモリからの該一方のデー
タをメモリする第3のメモリとよりなり、該第2及び第
3のメモリから同時に該2種のデータを1組として読出
すように構成してなる実用新案登録請求の範囲第1項記
載の交流信号発生器。(2) the memory circuit includes a read-only memory that stores the data and is supplied with the address signal;
first and second memories respectively storing one data and the other data of the data from the read-only memory at two time-shifted timings that are synchronized with the address signal; and a third memory that stores the one data from the first memory when the second memory stores the other data, and simultaneously stores the two types of data from the second and third memories. An alternating current signal generator according to claim 1, which is configured to read data as a set.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18419781U JPS5888411U (en) | 1981-12-10 | 1981-12-10 | AC signal generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18419781U JPS5888411U (en) | 1981-12-10 | 1981-12-10 | AC signal generator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5888411U true JPS5888411U (en) | 1983-06-15 |
Family
ID=29984146
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18419781U Pending JPS5888411U (en) | 1981-12-10 | 1981-12-10 | AC signal generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5888411U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4982215A (en) * | 1972-12-11 | 1974-08-08 |
-
1981
- 1981-12-10 JP JP18419781U patent/JPS5888411U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4982215A (en) * | 1972-12-11 | 1974-08-08 |
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