JPS5875860A - Liquid-cooled semiconductor device - Google Patents
Liquid-cooled semiconductor deviceInfo
- Publication number
- JPS5875860A JPS5875860A JP56173959A JP17395981A JPS5875860A JP S5875860 A JPS5875860 A JP S5875860A JP 56173959 A JP56173959 A JP 56173959A JP 17395981 A JP17395981 A JP 17395981A JP S5875860 A JPS5875860 A JP S5875860A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- liquid
- semiconductor device
- semiconductor
- cooled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は液冷型半導体装置の冷却効率を向上すするため
の改良に関するヶ
近時計算機システムの大規模化、高速化に伴って、半導
体集積回路素子（ＩＣ）を高集積化すること、及び半導
体ＩＣを高密度に実装することが重畳な課題となってい
る０
通常の半導体ＩＣは、動作時に素子内で発生した熱の大
部分がパツケー゛ジを経て、空冷によｐ素子外に放熱さ
れる構造を有している０従りてこＯような通常素子に於
ては、該素子が高密度に実装され、これら実装素子の発
熱によりてその環境温度が大幅に上昇した際１１、素子
の冷却が充分になされず、素子温度が上昇してその機能
が損なわれるという問題がある。そしてこの問題を除去
するべぐ提供されたのが液冷臘の半導体装置である〇液
冷型半導体装置の代表的構造としては、セラ電ツク等の
配線基板上に多数の半導体ＩＣチップが集積搭載される
論理素子等に於て多く用いられる構造、成るいは金属基
板上に一個の大塵半導体チップが搭載される大電力素子
等に多く用いられる構造がある〇
篇１図は前者の論理素子等に多く用いられる構造を有す
る液冷部半導装置の断面を模式的に表わしたもので、図
に於て１はセラミック配線基板、２は接続端子、３社チ
ップ・ステージ、４は半導体（ＩＣ）チップ、５は配線
パッド、６は内部配鰺、７社；ネクタ線、８紘金属キヤ
ツプ、９は冷１２はフルオ胃カーボン（Ｉｃ＠ｆ歇）寺
化５Ｐ聞Ｖ（牛活性な冷媒、１３はパツキン、１４はか
しめ手段を示す。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements to improve the cooling efficiency of liquid-cooled semiconductor devices.Recently, with the increase in scale and speed of computer systems, semiconductor integrated circuit elements (ICs) are used. High integration and high-density packaging of semiconductor ICs have become overlapping issues. In normal semiconductor ICs, most of the heat generated within the device during operation passes through the package and is cooled by air. In normal elements such as P elements, which have a structure in which heat is dissipated to the outside of the p element, the elements are mounted in a high density, and the environmental temperature increases significantly due to the heat generated by these mounted elements. When the temperature rises to 11, there is a problem that the element is not sufficiently cooled, and the element temperature rises, impairing its function. To eliminate this problem, a liquid-cooled semiconductor device was provided.A typical structure of a liquid-cooled semiconductor device is that a large number of semiconductor IC chips are integrated on a wiring board such as a ceramic circuit board. There is a structure that is often used in mounted logic elements, etc., or a structure that is often used in high power devices, etc. in which a single large semiconductor chip is mounted on a metal substrate. Figure 1 of Part 1 shows the logic of the former. This is a schematic cross-section of a liquid-cooled semiconductor device with a structure often used in devices, etc. In the figure, 1 is a ceramic wiring board, 2 is a connection terminal, 3 chip stages, and 4 is a semiconductor device. (IC) chip, 5 is the wiring pad, 6 is the internal wiring, 7 companies; connector wire, 8 is the metal cap, 9 is the cold 12 is the fluo gastric carbon (Ic@f 歇) Temple 5P listening V (Cow active A refrigerant, 13 a packing, and 14 a caulking means.
又第２図は後者の大電力素子岬に多く用いられる構造を
有する液冷型半導体装置の断面を模式的に表わしたもの
で、図に於て１′はステム・ヘッダ（金属基板）、２は
接続端子、３はチップ・ステージ、４は半導体チップ、
５Ｆｉ配線パツド、７はコネクタ巌、８は金属中ヤップ
、９は冷媒導入管、ｌＯは放熱フィン、１１は冷却フィ
ン、１２は冷媒、１５は金シリコン等のろう材、１６は
溶接部、１７はハメチック・シール部を示している。Fig. 2 is a schematic cross-section of a liquid-cooled semiconductor device having a structure often used in the latter high-power device cape. is a connection terminal, 3 is a chip stage, 4 is a semiconductor chip,
5Fi wiring pad, 7 is a connector wao, 8 is a metal pipe, 9 is a refrigerant introduction pipe, 1O is a radiation fin, 11 is a cooling fin, 12 is a refrigerant, 15 is a brazing material such as gold silicon, 16 is a welded part, 17 indicates the hametic seal portion.
そして第１図の構造に於ては半導体（ＩＣ）チップ４は
、熱抵抗の高いセラミック配線基板１上に搭載されてい
るので、動作中半導体（ＩＣ）チップ４内で生じた熱は
、その大部分が半導体（ＩＣ）チップ４０表面から冷媒
１２、金属キャップ８を介して放熱冷却される０即ち冷
媒１２は内部の発熱によシ昇温し九半導体（Ｉ Ｃ）チ
ップ４表面から熱を奪って気化し、気泡１８となりて冷
媒１２内を通過し、骸蒸気が金属キャップ８の冷却フィ
ン１１に達し、熱交換されて液化するという熱サイクル
によシ冷却がなされる０
又２図に示す金属基板即ちステム・ヘッダ１′上に直に
半導体チップ４が搭載される構造の半導体装置に於ては
、半導体チップ４で開先じた熱は直ちにステム・ヘッダ
１′に放熱される０然しながら誼構造の半導体装置は通
常絶縁体上に装着されるので、ステム・ヘッダの放熱を
良くするために該図に示すよう′／に液冷製の半導体装
置が提供される。In the structure shown in FIG. 1, the semiconductor (IC) chip 4 is mounted on the ceramic wiring board 1 with high thermal resistance, so the heat generated within the semiconductor (IC) chip 4 during operation is absorbed by the semiconductor (IC) chip 4. Most of the heat is radiated and cooled from the surface of the semiconductor (IC) chip 40 via the coolant 12 and the metal cap 8. The temperature of the coolant 12 rises due to internal heat generation, and heat is transferred from the surface of the semiconductor (IC) chip 4. Cooling is achieved through a thermal cycle in which the vapor is absorbed, vaporized, becomes bubbles 18, passes through the refrigerant 12, reaches the cooling fins 11 of the metal cap 8, undergoes heat exchange, and liquefies. In a semiconductor device having a structure in which a semiconductor chip 4 is mounted directly on a metal substrate, that is, a stem header 1', the heat generated by the semiconductor chip 4 is immediately radiated to the stem header 1'. However, since a semiconductor device having a hollow structure is usually mounted on an insulator, a liquid-cooled semiconductor device is provided as shown in the figure in order to improve heat dissipation from the stem header.
そして該装置に於ては伝導によ多金属キャップ８に伝っ
た熱が放熱フィン１０を経て放熱されるｊｌｌ（７）冷
却バスと、ステム・ヘッダ１５表面に触れて気化した冷
媒の蒸気が気泡１８となって冷媒１２中をぬけ冷却フィ
ン１１に達して熱交換し、キャップ８の放熱フィン１０
を介して放熱する第２の冷却パスが形成される。In this device, the heat transferred to the multi-metallic cap 8 by conduction is radiated through the radiating fins 10 into the cooling bath (7), and the vapor of the refrigerant vaporized when it touches the surface of the stem header 15 is bubbled. 18, passes through the refrigerant 12, reaches the cooling fins 11, and exchanges heat with the heat dissipating fins 10 of the cap 8.
A second cooling path is formed which dissipates heat through.
然しなか、ら従来第１図の構造を有する液冷型半導体装
置に於ては、半導体チップの表面を榎う保護絶縁膜が比
較的平坦く形成されているために、図に示すようにチッ
プ４の角等の限られた場所を核として冷媒が沸騰する０
従って該チップの放熱は気泡１８の発生する小領域から
のみなされるために放熱効果が不充分であった０
又第２図の構造を有する装置に於ても、従来ステム・ヘ
ッダ上面は平坦に形成されていたために、上記同様冷媒
の沸騰領域（気泡１８の発生領域）が限られ、放熱効果
が充分ではなかつた０本発明は上記問題点を除去するた
めに、半導体チップの上面全域成るいはステム・ヘッダ
の上面全域上で冷媒の沸騰が行われるような構造を具備
せしめ九液冷型半導体装置を提供する０即ち本発明は液
冷型半導体装置に於て、半導体チップを覆う保禮絶縁膜
成るいは半導体チップが搭載された金属基板の上面を粗
面状に形成し、該半導体チップ成るいは金属基板の上面
全域上に冷媒沸騰の核を形成したことを特徴とする。However, in conventional liquid-cooled semiconductor devices having the structure shown in FIG. 1, the protective insulating film covering the surface of the semiconductor chip is formed relatively flat, so that the chip is The refrigerant boils around a limited area such as the corner of 4.
Therefore, the heat dissipation effect of the chip was only from the small area where the air bubbles 18 were generated, and the heat dissipation effect was insufficient.0 Also, even in the device having the structure shown in FIG. 2, the top surface of the stem header was conventionally flat. As a result, the boiling region of the refrigerant (region where bubbles 18 are generated) is limited as described above, and the heat dissipation effect is not sufficient. The present invention provides a liquid-cooled semiconductor device having a structure in which the refrigerant is boiled over the entire upper surface of the stem header.That is, the present invention provides a liquid-cooled semiconductor device with a structure in which a refrigerant is boiled over the entire upper surface of the stem header. It is characterized in that the upper surface of the insulating film or the metal substrate on which the semiconductor chip is mounted is formed into a rough surface, and the core of the refrigerant boiling is formed over the entire upper surface of the semiconductor chip or the metal substrate.
以下本発明を実施例について図を用い詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments and drawings.
第３図は本発明の籐１項に骸幽する一実施例に於ける上
面図（ａ）及びそのｈ−ｘ矢視断面１伽）で、第４図は
本発明の第２項に該当する一実施例に於ける上面図（ａ
）及びそのｈ−＆矢視断面図６）であるＯ
熱抵抗の高いセラミック配線基板等に複数個の半導体（
ＩＣ）チップが搭載される前記第１図に該当する液冷型
半導体装置には、半導体（ＩＣ）チップの表面を粗面状
に形成する本発明の第１項が適用される。即ち本発明の
第１項に該当する半導体チップは、例えば第３図（ａ）
及び（ｂ）に示すように半導体（Ｉ Ｃ）チップ２工の
上面に、該チップの機能領域上を覆い１００〜１５０〔
μｍ〕程度の厚さを有する保護絶縁膜例えばシん珪酸ガ
ラ、ｑＰｓＧ）膜２２が被着形成され、該ＰＢＱ＄２２
の上面に例えば１００（μｍ）程度のピッチで幅２０〜
５０〔μｍ玉深さ２０〜５０〔μｍ〕程度の溝２３が、
例えば直角に交差して設けられてなっている。Fig. 3 is a top view (a) and its h-x arrow cross section 1) of an embodiment of the present invention, which is covered in the rattan item 1, and Fig. 4 corresponds to the invention's item 2. A top view (a
) and its h-& arrow cross-sectional view 6).
The first aspect of the present invention, in which the surface of the semiconductor (IC) chip is formed into a rough surface, is applied to the liquid-cooled semiconductor device shown in FIG. 1 on which an IC chip is mounted. That is, the semiconductor chip corresponding to item 1 of the present invention is, for example, as shown in FIG. 3(a).
And as shown in (b), on the upper surface of two semiconductor (IC) chips, the functional area of the chip is covered with a 100 to 150 [
A protective insulating film (for example, cinsilicate glass, qPsG) film 22 having a thickness of approximately 1 μm is deposited on the PBQ$22
For example, at a pitch of about 100 (μm) on the top surface of the
50 [μm] Groove 23 with a depth of about 20 to 50 [μm],
For example, they are provided to intersect at right angles.
なお図中２４は配線パターンを示している。そして上記
＃Ｉ２３はウェット−エツチング法成るいｔｉｌＪアク
ティブ−イオン・エツチング法勢通常のエツチング法に
よシ形成されるが、溝２３の縁部がなるべく鋭利である
ことが好ましいので、その為にはりアクティブ・イオン
・エツチング法が適している。なお粗面の形状として紘
上記実施例に示した溝に限らず、２０〜５０〔μｍ−〕
８１度の直径を有し深さ２０〜５０（μｍ）８度の穴を
、上記同様のエツチング法を用いてＰ８Ｇ膜上面に例え
ば１００〔μｍ）８度のピッチで分散形成せしめても良
い。又粗面形成の手段としてはＰＢＧ膜上に、溶融した
ＰＳＧの所望の大きさの粒子を吹き付けて固着せしる方
法もある６但し此の方法で形成した粗面の凹凸は不規ｊ
ｌｌＫなる。Note that 24 in the figure indicates a wiring pattern. The above #I23 is formed by a wet etching method, a tilJ active ion etching method, or a normal etching method, but since it is preferable that the edges of the groove 23 be as sharp as possible, Active ion etching is suitable. Note that the shape of the rough surface is not limited to the grooves shown in the above examples;
Holes having a diameter of 81 degrees and a depth of 20 to 50 (μm) 8 degrees may be formed dispersedly on the upper surface of the P8G film at a pitch of 100 [μm) 8 degrees, for example, using the same etching method as described above. Another method for forming a rough surface is to spray particles of a desired size of molten PSG onto the PBG film and fix them6. However, the rough surface formed by this method has irregularities.
It becomes llK.
更に又保護絶縁膜がＰａＧ属以外の無機絶縁膜や、ポリ
イミド等の有機絶縁膜の場合にも本発明は適用できる。Furthermore, the present invention can also be applied when the protective insulating film is an inorganic insulating film other than PaG or an organic insulating film such as polyimide.
上記の場合と異な）金属基板即ちステム・ヘッダ上に直
かに半導体チップが搭載される前記第２図に示した構造
の液冷用半導体装置に於て社、本発明の第２項が適用さ
れステム・ヘッダ（金属基板）の上面が粗面状に形成さ
れる。第３図（ａ）及び伽）はその一実施例を示したも
ので、図に於て２５は銅（Ｃｕ）等からなるステム・ヘ
ッダ、２６は幅０．１〜０．１５ ＣＷｌｌ ）、深さ
０．１〜０．１５ （ｍ ）程度の溝、！！７はモリブ
デン（Ｍｅ）４Ｆで形成されたチップ・ステージ、！８
紘ハーメチック・シール部、２９は接続ビン、５（１２
パール等からなるキャップ溶接用リングを表わしている
。そして上記溝２６Ｂｖ−ザ加工成るいは機械加工にょ
如ステム・ヘッダ上に予め例えば０．３〜ｏ、ｓ（ｍ）
程度のピッチで形成される＠なお上記の例ではステム・
ヘッダ面の粗面化を壽によって行９たが、該粗面は穴に
上って形成しても曳い。そしてとの場合、穴径は０．１
〜０．１５ （ｓ＋ｓφ〕１度、その深さは０．１〜０
．１５ Ｃｗｔ ］１度で嵐く、又０．５〔露〕程度の
間隔でチップ・ステージ、ハーメチック・シール部、キ
ャップ溶接用リング部以外のステム・ヘッダ上面全域に
分散配置すれば良い。Item 2 of the present invention is applicable to a liquid cooling semiconductor device having the structure shown in FIG. The upper surface of the stem header (metal substrate) is formed into a rough surface. Figures 3(a) and 3) show an example of this, in which 25 is a stem header made of copper (Cu), etc., 26 is a stem with a width of 0.1 to 0.15 CWll), A groove with a depth of about 0.1 to 0.15 (m)! ! 7 is a chip stage made of molybdenum (Me) 4F,! 8
Hiro hermetic seal part, 29 is connection bottle, 5 (12
It represents a cap welding ring made of pearl or the like. The groove 26Bv is pre-processed or machined onto the stem header, for example, with a diameter of 0.3~o,s(m).
In the above example, the stem is formed with a pitch of approximately
Although the header surface was roughened by a cylindrical method, the rough surface could be formed by going up into the hole. And in the case of , the hole diameter is 0.1
~0.15 (s+sφ) 1 degree, its depth is 0.1~0
．． 15 Cwt], and may be distributed over the entire upper surface of the stem header except for the chip stage, hermetic seal part, and cap welding ring part at intervals of about 0.5 [dew].
上記本発明の構造を有する半導体（Ｉ Ｃ）チップ或る
いはステム・ヘッダ（金属基板）を用いて第１固成るい
は第２図と同様な構造に組み立てられた液冷用半導体装
置に於て、昇温した半導体チップ或るいはステム・ヘッ
ダに接している冷媒の沸騰線、半導体チップ或るいはス
テム・ヘッダの上面に設けられている連成るいは穴等の
凹凸部を核にして半導体（ＩＣ）チップ或い紘ステム・
ヘッダの上面全域で行われ、半導体（ＩＣ）チップ上面
金゛域成るいはステム・ヘッダ上面全域から気化熱が奪
われるので、冷却効率性増大し、その熱抵抗を従来の液
冷部半導体装置の圭以下に減少せしめることができる・
以上説明したように本発明によれば、半導体素子の熱抵
抗を減少せしめることができるので、半導体素子の高密
度集装中大電力化が可能になる。In a liquid cooling semiconductor device assembled into a structure similar to that shown in the first solid state or FIG. The boiling line of the refrigerant that is in contact with the heated semiconductor chip or stem header, or the irregularities such as the series or holes provided on the top surface of the semiconductor chip or stem header, are used as the core. Semiconductor (IC) chip or Hiro stem
The heat of vaporization is carried out over the entire top surface of the header, and the heat of vaporization is removed from the top metal area of the semiconductor (IC) chip or the entire top surface of the stem header, increasing cooling efficiency and reducing the thermal resistance compared to conventional liquid-cooled semiconductor devices. As explained above, according to the present invention, it is possible to reduce the thermal resistance of a semiconductor element, and therefore it is possible to increase the power consumption of semiconductor elements while high-density integration.
【図面の簡単な説明】
第１図及びｊ１２−は従来の液冷型半導体装置の断面模
式図、第３図社本発明の一実施例に於ける上面図（ＪＬ
）及びＡ−に矢揖断面図伽）、第４図は本発明の他の一
実施例に於ける上面図−）及びｈ−Ｎ矢視断向図伽）で
ある。
図に於て、２１線半導体（ＩＣ）チップ、２２はシん珪
酸ガラス膜、２８は溝、２５はステム・ヘッダ、２６紘
溝、２７はチップ・ステージ、２８はハーメチック値シ
ール部、２９は接続ビン、３０はキャップ溶接用リング
を示す。
昂 １（！ｌ
勇２図
晃 つ 図
９[Brief Description of the Drawings] Figures 1 and 12- are schematic cross-sectional views of a conventional liquid-cooled semiconductor device, and Figure 3 is a top view of an embodiment of the present invention (JL
) and A- are sectional views taken along arrows ｜), and FIG. 4 is a top view of another embodiment of the present invention. In the figure, 21 is a semiconductor (IC) chip, 22 is a cinsilicate glass film, 28 is a groove, 25 is a stem header, 26 is a groove, 27 is a chip stage, 28 is a hermetic value sealing part, and 29 is a Connection bottle 30 indicates a ring for cap welding. Akira 1 (!l Yuu 2 Figure Akira tsu Figure 9
Claims (1)
成してなることを特徴とする液冷型半導体装置。 ２、半導体チップが搭載された金属基板の上面を粗面状
に形成してな２！ことを特徴とする液冷型半導体装置。[Scope of Claims] 1. A liquid-cooled semiconductor device characterized in that the upper surface of a protective insulating film covering a semiconductor chip is formed into a rough surface. 2. The top surface of the metal substrate on which the semiconductor chip is mounted must be formed into a rough surface.2! A liquid-cooled semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56173959A JPS5875860A (en) | 1981-10-30 | 1981-10-30 | Liquid-cooled semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56173959A JPS5875860A (en) | 1981-10-30 | 1981-10-30 | Liquid-cooled semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5875860A true JPS5875860A (en) | 1983-05-07 |
| JPS6219074B2 JPS6219074B2 (en) | 1987-04-25 |
Family
ID=15970215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56173959A Granted JPS5875860A (en) | 1981-10-30 | 1981-10-30 | Liquid-cooled semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5875860A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114445A (en) * | 1981-12-28 | 1983-07-07 | Fujitsu Ltd | Liquid-cooled module |
| JPS60254757A (en) * | 1984-05-31 | 1985-12-16 | Toshiba Corp | Part for high density mounting circuit |
| JPS60254641A (en) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | Liquid-sealed-in package |
| JP2004297069A (en) * | 2003-03-27 | 2004-10-21 | Stmicroelectronics Inc | System and method for direct convective cooling of exposed integrated circuit die surface |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147576A (en) * | 1974-10-23 | 1976-04-23 | Hitachi Ltd | KANNAIKYUCHAKUSHIKI KATSUSEITANKYUCHAKUSOCHI |
-
1981
- 1981-10-30 JP JP56173959A patent/JPS5875860A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147576A (en) * | 1974-10-23 | 1976-04-23 | Hitachi Ltd | KANNAIKYUCHAKUSHIKI KATSUSEITANKYUCHAKUSOCHI |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114445A (en) * | 1981-12-28 | 1983-07-07 | Fujitsu Ltd | Liquid-cooled module |
| JPS60254757A (en) * | 1984-05-31 | 1985-12-16 | Toshiba Corp | Part for high density mounting circuit |
| JPS60254641A (en) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | Liquid-sealed-in package |
| JPH0342512B2 (en) * | 1984-05-31 | 1991-06-27 | ||
| JPH0348661B2 (en) * | 1984-05-31 | 1991-07-25 | Tokyo Shibaura Electric Co | |
| JP2004297069A (en) * | 2003-03-27 | 2004-10-21 | Stmicroelectronics Inc | System and method for direct convective cooling of exposed integrated circuit die surface |
| JP4657617B2 (en) * | 2003-03-27 | 2011-03-23 | エスティーマイクロエレクトロニクス，インコーポレイテッド | System and method for direct convection cooling of an exposed integrated circuit die surface |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6219074B2 (en) | 1987-04-25 |
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