JPS6219074B2 - - Google Patents
Info
- Publication number
- JPS6219074B2 JPS6219074B2 JP56173959A JP17395981A JPS6219074B2 JP S6219074 B2 JPS6219074 B2 JP S6219074B2 JP 56173959 A JP56173959 A JP 56173959A JP 17395981 A JP17395981 A JP 17395981A JP S6219074 B2 JPS6219074 B2 JP S6219074B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- refrigerant
- chip
- semiconductor device
- filled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 58
- 239000003507 refrigerant Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 230000001681 protective effect Effects 0.000 claims description 7
- 238000001816 cooling Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000009835 boiling Methods 0.000 description 3
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000002826 coolant Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は冷媒封入型半導体装置の冷却効率を向
上するための改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement for improving the cooling efficiency of a refrigerant-filled semiconductor device.
近時計算機システムの大規模化、高速化に伴つ
て、半導体集積回路素子（IC）を高集積化する
こと、及び半導体ICを高密度に実装することが
重要な問題となつている。 BACKGROUND OF THE INVENTION In recent years, as computer systems have become larger and faster, increasing the degree of integration of semiconductor integrated circuit elements (ICs) and packaging semiconductor ICs with high density have become important issues.
通常の半導体ICは、動作時に素子内で発生し
た熱の大部分がパツケージを経て、空冷により素
子外に放熱される構造を有している。従つてこの
ような通常素子に於ては、該素子が高密度に実装
され、これら実装素子の発熱によつてその環境温
度が大幅に上昇した際には、素子の冷却が充分に
なされず、素子温度が上昇してその機能が損なわ
れるという問題がある。そしてこの問題を除去す
るべく提供されたのが液冷型即ち冷媒封入型の半
導体装置である。 A typical semiconductor IC has a structure in which most of the heat generated within the device during operation passes through the package and is radiated outside the device through air cooling. Therefore, in such ordinary devices, when the devices are densely packaged and the ambient temperature rises significantly due to the heat generated by these mounted devices, the devices are not cooled sufficiently. There is a problem that the element temperature increases and its function is impaired. In order to eliminate this problem, a liquid-cooled semiconductor device, that is, a refrigerant-filled semiconductor device, has been provided.
冷媒封入型半導体装置の代表的構造としては、
セラミツク等の配線基板上に多数の半導体ICチ
ツプが集積搭載される論理素子等に於て多く用い
られる構造、或るいは金属基板上に一個の大型半
導体チツプが搭載される大電力素子等に多く用い
られる構造がある。 A typical structure of a refrigerant-filled semiconductor device is as follows.
This structure is often used in logic devices, etc., in which many semiconductor IC chips are integrated and mounted on a wiring board made of ceramic, etc., or in high-power devices, etc., in which one large semiconductor chip is mounted on a metal substrate. There is a structure used.
第１図は前者の論理素子等に多く用いられる構
造を有する冷媒封入型半導体装置の断面を模式的
に表わしたもので、図に於て１はセラミツク配線
基板、２は接続端子、３はチツプ・ステージ、４
は半導体（IC）チツプ、５は配線パツド、６は
内部配線、７はコネクタ線、８は金属キヤツプ、
９は冷媒注入管、１０は放熱フイン、１１は冷却
フイン、１２はフルオロカーボン（CmFn）等化
学的に不活性な冷媒、１３はパツキン、１４はか
しめ手段を示す。 Figure 1 schematically represents the cross section of a refrigerant-filled semiconductor device having a structure often used in the former logic elements, etc. In the figure, 1 is a ceramic wiring board, 2 is a connection terminal, and 3 is a chip.・Stage, 4
is a semiconductor (IC) chip, 5 is a wiring pad, 6 is an internal wiring, 7 is a connector wire, 8 is a metal cap,
Reference numeral 9 indicates a refrigerant injection pipe, 10 a heat radiation fin, 11 a cooling fin, 12 a chemically inert refrigerant such as fluorocarbon (CmFn), 13 a packing, and 14 a caulking means.
又第２図は後者の大電力素子等に多く用いられ
る構造を有する冷媒封入型半導体装置の断面を模
式的に表わしたもので、図に於て１′はステム・
ヘツダ（金属基板）、２は接続端子、３はチツ
プ・ステージ、４は半導体チツプ、５は配線パツ
ド、７はコネクタ線、８は金属キヤツプ、９は冷
媒導入管、１０は放熱フイン、１１は冷却フイ
ン、１２は冷媒、１５は金シリコン等のろう材、
１６は溶接部、１７はハメチツク・シール部を示
している。 Fig. 2 schematically shows a cross section of a refrigerant-filled semiconductor device having a structure often used in the latter type of high-power devices.
Header (metal board), 2 is a connection terminal, 3 is a chip stage, 4 is a semiconductor chip, 5 is a wiring pad, 7 is a connector wire, 8 is a metal cap, 9 is a refrigerant introduction pipe, 10 is a heat radiation fin, 11 is a Cooling fins, 12 is a refrigerant, 15 is a brazing material such as gold silicon,
Reference numeral 16 indicates a welded portion, and 17 indicates a hook seal portion.
そして第１図の構造に於ては半導体（IC）チ
ツプ４は、熱抵抗の高いセラミツク配線基板１上
に搭載されているので、動作中半導体（IC）チ
ツプ４内で生じた熱は、その大部分が半導体
（IC）チツプ４の表面から冷媒１２、金属キヤツ
プ８を介して放熱冷却される。即ち冷媒１２は内
部の発熱により昇温した半導体（IC）チツプ４
表面から熱を奪つて気化し、気泡１８となつて冷
媒１２内を通過し、該蒸気が金属キヤツプ８の冷
却フイン１１に達し、熱交換されて液化するとい
う熱サイクルにより冷却がなされる。 In the structure shown in FIG. 1, the semiconductor (IC) chip 4 is mounted on the ceramic wiring board 1 with high thermal resistance, so the heat generated within the semiconductor (IC) chip 4 during operation is absorbed by the semiconductor (IC) chip 4. Most of the heat is radiated and cooled from the surface of the semiconductor (IC) chip 4 via the coolant 12 and the metal cap 8. In other words, the refrigerant 12 cools the semiconductor (IC) chip 4 whose temperature has risen due to internal heat generation.
Cooling is achieved through a thermal cycle in which heat is removed from the surface and vaporized, forming bubbles 18 and passing through the refrigerant 12. The vapor reaches the cooling fins 11 of the metal cap 8, where it is heat exchanged and liquefied.
又２図に示す金属基板即ちステム・ヘツダ１′
上に直に半導体チツプ４が搭載される構造の半導
体装置に於ては、半導体チツプ４で発生した熱は
直ちにステム・ヘツダ１′に放熱される。然しな
がら該構造の半導体装置は通常絶縁体上に装着さ
れるので、ステム・ヘツダの放熱を良くするため
に該図に示すような冷媒封入型の半導体装置が提
供される。 Also, a metal substrate, that is, a stem header 1' shown in Figure 2
In a semiconductor device having a structure in which a semiconductor chip 4 is mounted directly on top, heat generated by the semiconductor chip 4 is immediately radiated to the stem header 1'. However, since a semiconductor device having this structure is usually mounted on an insulator, a refrigerant-filled semiconductor device as shown in the figure is provided in order to improve heat dissipation from the stem/header.
そして該装置に於ては伝導により金属キヤツプ
８に伝つた熱が放熱フイン１０を経て放熱される
第１の冷却パスと、ステム・ヘツダ１５表面に触
れて気化した冷媒の蒸気が気泡１８となつて冷媒
１２中をぬけ冷却フイン１１に達して熱交換し、
キヤツプ８の放熱フイン１０を介して放熱する第
２の冷却パスが形成される。 In this device, there is a first cooling path in which the heat transferred to the metal cap 8 by conduction is radiated through the heat radiating fins 10, and the vapor of the refrigerant that vaporizes when it touches the surface of the stem header 15 becomes bubbles 18. passes through the refrigerant 12 and reaches the cooling fins 11 to exchange heat,
A second cooling path is formed to radiate heat through the heat radiating fins 10 of the cap 8.
然しながら従来第１図の構造を有する冷媒封入
型半導体装置に於ては、半導体チツプの表面を覆
う保護絶縁膜が比較的平坦に形成されているため
に、図に示すようにチツプ４の角等の限られた場
所を核として冷媒が沸騰する。従つて該チツプの
放熱は気泡１８の発生する小領域からのみなされ
るために放熱効果が不充分であつた。 However, in the conventional coolant-filled semiconductor device having the structure shown in FIG. 1, since the protective insulating film covering the surface of the semiconductor chip is formed relatively flat, the corners of the chip 4, etc. The refrigerant boils with a core in a limited area. Therefore, the heat dissipation effect of the chip was insufficient because the heat dissipation was only from the small area where the bubbles 18 were generated.
又第２図の構造を有する装置に於ても、従来ス
テム・ヘツダ上面は平坦に形成されていたため
に、上記同様冷媒の沸騰領域（気泡１８の発生領
域）が限られ、放熱効果が充分ではなかつた。 Furthermore, even in the device having the structure shown in Fig. 2, since the upper surface of the stem/header has conventionally been formed flat, the boiling region of the refrigerant (region where bubbles 18 are generated) is limited as described above, and the heat dissipation effect is not sufficient. Nakatsuta.
本発明は上記問題点を除去するために、半導体
チツプの上面全域或るいはステム・ヘツダの上面
全域上で冷媒の沸騰が行われるような構造を具備
せしめた冷媒封入型半導体装置を提供する。 In order to eliminate the above-mentioned problems, the present invention provides a refrigerant-filled semiconductor device having a structure in which refrigerant is boiled over the entire upper surface of a semiconductor chip or over the entire upper surface of a stem header.
即ち本発明は半導体容器の底部基板上に上面が
保護絶縁膜で覆われた半導体チツプが搭載され、
該半導体容器内に冷媒が注入密封される冷媒封入
型半導体装置において、該半導体チツプを覆う保
護絶縁膜の上面、或いは半導体チツプが搭載され
る底部基板が金属基板よりなるとき該金属基板の
上面を、それぞれ粗面状に形成し、該半導体チツ
プ或いは金属基板の上面全域上に冷媒沸騰の核を
形成したことを特徴とする。 That is, in the present invention, a semiconductor chip whose upper surface is covered with a protective insulating film is mounted on a bottom substrate of a semiconductor container,
In a refrigerant-filled semiconductor device in which a refrigerant is injected into the semiconductor container and sealed, the upper surface of the protective insulating film covering the semiconductor chip or the upper surface of the metal substrate when the bottom substrate on which the semiconductor chip is mounted is made of a metal substrate. , are characterized in that they are each formed into a rough surface shape, and a core of refrigerant boiling is formed over the entire upper surface of the semiconductor chip or metal substrate.
以下本発明を実施例について図を用い詳細に説
明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments and drawings.
第３図は本発明の第１項に該当する一実施例に
於ける上面図ａ及びそのＡ−A′矢視断面図ｂ
で、
第４図は本発明の第２項に該当する一実施例に
於ける上面図ａ及びそのＡ−A′矢視断面図ｂで
ある。 FIG. 3 is a top view a and a sectional view b taken along the line A-A' in an embodiment corresponding to item 1 of the present invention.
FIG. 4 is a top view (a) and a sectional view (b) taken along the line A-A' of an embodiment corresponding to the second aspect of the present invention.
熱抵抗の高いセラミツク配線基板等に複数個の
半導体（IC）チツプが搭載される前記第１図に
該当する冷媒封入型半導体装置には、半導体
（IC）チツプの表面を粗面状に形成する本発明の
第１項が適用される。即ち本発明の第１項に該当
する半導体チツプは、例えば第３図ａ及びｂに示
すように半導体（IC）チツプ２１の上面に、該
チツプの機能領域上を覆い100〜150〔μｍ〕程度
の厚さを有する保護絶縁膜例えばりん珪酸ガラス
（PSG）膜２２が被着形成され、該PSG膜２２の
上面に例えば100〔μｍ〕程度のピツチで幅20〜
50〔μｍ〕、深さ20〜50〔μｍ〕程度の溝２３
が、例えば直角に交差して格子状に設けられてな
つている。 In a refrigerant-filled semiconductor device shown in FIG. 1, in which a plurality of semiconductor (IC) chips are mounted on a ceramic wiring board or the like with high thermal resistance, the surface of the semiconductor (IC) chips is formed to have a rough surface. Clause 1 of the invention applies. In other words, a semiconductor chip that falls under the first aspect of the present invention has a semiconductor (IC) chip 21 on the upper surface of which covers the functional area of the chip by about 100 to 150 [μm], as shown in FIGS. 3a and 3b, for example. A protective insulating film, for example, a phosphosilicate glass (PSG) film 22 having a thickness of
Groove 23 with a depth of about 50 [μm] and 20 to 50 [μm]
For example, they are arranged in a grid pattern, intersecting each other at right angles.
なお図中２４は配線パターンを示している。そ
して上記溝２３はウエツト・エツチング法或るい
はリアクテイブ・イオン・エツチング法等通常の
エツチング法により形成されるが、溝２３の縁部
がなるべく鋭利であることが好ましいので、その
為にはリアクテイブ・イオン・エツチング法が適
している。なお粗面の形状としては上記実施例に
示した溝に限らず、20〜50〔μｍφ〕程度の直径
を有し深さ20〜50〔μｍ〕程度の穴を、上記同様
のエツチング法を用いてPSG膜上面に例えば100
〔μｍ〕程度のピツチで分散形成せしめても良
い。又粗面形成の手段としてはPSG膜上に、溶融
したPSGの所望の大きさの粒子を吹き付けて固着
せしめる方法もある。但し此の方法で形成した粗
面の凹凸は不規則になる。 Note that 24 in the figure indicates a wiring pattern. The groove 23 is formed by a conventional etching method such as a wet etching method or a reactive ion etching method. However, it is preferable that the edges of the groove 23 be as sharp as possible. Ion etching method is suitable. Note that the shape of the rough surface is not limited to the grooves shown in the above examples, but holes with a diameter of about 20 to 50 [μmφ] and a depth of about 20 to 50 [μm] can be etched using the same etching method described above. For example, 100
It may be formed in a dispersed manner with a pitch of about [μm]. Another method for forming a rough surface is to spray particles of a desired size of molten PSG onto the PSG film and make them adhere. However, the unevenness of the rough surface formed by this method becomes irregular.
更に又保護絶縁膜がPSG膜以外の無機絶縁膜
や、ポリイミド等の有機絶縁膜の場合にも本発明
は適用できる。 Furthermore, the present invention is also applicable when the protective insulating film is an inorganic insulating film other than a PSG film or an organic insulating film such as polyimide.
上記の場合と異なり金属基板即ちステム・ヘツ
ダ上に直かに半導体チツプが搭載される前記第２
図に示した構造の冷媒封入型半導体装置に於て
は、本発明の第２項が適用されステム・ヘツダ
（金属基板）の上面が粗面状に形成される。第４
図ａ及びｂはその一実施例を示したもので、図に
於て２５は銅（Cu）等からなるステム・ヘツ
ダ、２６は幅0.1〜0.15〔mm〕、深さ0.1〜0.15
〔mm〕程度の溝、２７はモリブデン（Mo）等で形
成されたチツプ・ステージ、２８はハーメチツ
ク・シール部、２９は接続ピン、３０はコバール
等からなるキヤツプ溶接用リングを表わしてい
る。そして上記溝２６はレーザ加工或るいは機械
加工によりステム・ヘツダ上に予め例えば0.3〜
0.5〔mm〕程度のピツチで形成される。なお上記
の例ではステム・ヘツダ面の粗面化を溝によつて
行つたが、該粗面は穴によつて形成しても良い。
そしてこの場合、穴径は0.1〜0.15〔mmφ〕程
度、その深さは0.1〜0.15〔mm〕程度で良く、又
0.5〔mm〕程度の間隔でチツプ・ステージ、ハー
メチツク・シール部、キヤツプ溶接用リング部以
外のステム・ヘツダ上面全域に分散配置すれば良
い。 Unlike the above case, the semiconductor chip is mounted directly on the metal substrate, that is, the stem header.
In the refrigerant-filled semiconductor device having the structure shown in the figure, the second aspect of the present invention is applied, and the upper surface of the stem header (metal substrate) is formed into a rough surface. Fourth
Figures a and b show one example of this. In the figures, 25 is a stem header made of copper (Cu), etc., and 26 is a width of 0.1 to 0.15 [mm] and a depth of 0.1 to 0.15 mm.
27 is a chip stage made of molybdenum (Mo), 28 is a hermetic seal, 29 is a connecting pin, and 30 is a cap welding ring made of Kovar or the like. The groove 26 is formed on the stem header by laser processing or machining.
It is formed with a pitch of about 0.5 [mm]. In the above example, the stem/header surface is roughened by grooves, but the roughened surface may also be formed by holes.
In this case, the hole diameter may be about 0.1 to 0.15 [mmφ], the depth may be about 0.1 to 0.15 [mm], or
They may be distributed over the entire upper surface of the stem header except for the chip stage, hermetic seal, and cap welding ring at intervals of about 0.5 mm.
上記本発明の構造を有する半導体（IC）チツ
プ或るいはステム・ヘツダ（金属基板）を用いて
第１図或るいは第２図と同様な構造に組み立てら
れた冷媒封入型半導体装置に於て、昇温した半導
体チツプ或るいはステム・ヘツダに接している冷
媒の沸騰は、半導体チツプ或るいはステム・ヘツ
ダの上面に粗面を形成する溝或るいは穴等の凹凸
部を核にして半導体（IC）チツプ或いはステ
ム・ヘツダの上面全域で行われ、半導体（IC）
チツプ上面全域或るいはステム・ヘツダ上面全域
から気化熱が奪われるので、冷却効率は増大し、
その熱抵抗を従来の冷媒封入型半導体装置の1/2
以下に減少せしめることができる。 In a refrigerant-filled semiconductor device assembled into a structure similar to that shown in FIG. 1 or 2 using the semiconductor (IC) chip or stem header (metal substrate) having the structure of the present invention, The boiling of the refrigerant in contact with the heated semiconductor chip or stem header is caused by uneven parts such as grooves or holes forming a rough surface on the top surface of the semiconductor chip or stem header. Semiconductor (IC)
Since vaporization heat is removed from the entire top surface of the chip or the entire top surface of the stem/header, cooling efficiency increases,
Its thermal resistance is 1/2 that of conventional refrigerant-filled semiconductor devices.
It can be reduced to:
以上説明したように本発明によれば、半導体素
子の熱抵抗を減少せしめることができるので、半
導体素子の高密度実装や大電力化が可能になる。 As explained above, according to the present invention, it is possible to reduce the thermal resistance of a semiconductor element, thereby making it possible to implement high-density packaging and increase power consumption of semiconductor elements.
第１図及び第２図は従来の冷媒封入型半導体装
置の断面模式図、第３図は本発明の一実施例に於
ける上面図ａ及びＡ−A′矢視断面図ｂ、第４図
は本発明の他の一実施例に於ける上面図ａ及びＡ
−A′矢視断面図ｂである。
図に於て、２１は半導体（IC）チツプ、２２
はりん珪酸ガラス膜、２３は溝、２５はステム・
ヘツダ、２６は溝、２７はチツプ・ステージ、２
８はハーメチツク・シール部、２９は接続ピン、
３０はキヤツプ溶接用リングを示す。
1 and 2 are schematic cross-sectional views of a conventional refrigerant-filled semiconductor device, FIG. 3 is a top view a and a sectional view b taken along the line A-A', and FIG. 4 is a cross-sectional view of an embodiment of the present invention. are top views a and A in another embodiment of the present invention.
-A' arrow sectional view b. In the figure, 21 is a semiconductor (IC) chip, 22
Phososilicate glass film, 23 is a groove, 25 is a stem.
header, 26 groove, 27 chip stage, 2
8 is the hermetic seal, 29 is the connection pin,
30 indicates a cap welding ring.
Claims (1)
膜で覆われた半導体チツプが搭載され、該半導体
容器内に冷媒が注入密封される冷媒封入型半導体
装置において、該半導体チツプを覆う保護絶縁膜
の上面を粗面状に形成してなることを特徴とする
冷媒封入型半導体装置。 ２ 前記半導体容器の底部基板が金属よりなり、
該金属基板の上面を粗面状に形成してなることを
特徴とする特許請求の範囲第１項記載の冷媒封入
型半導体装置。[Scope of Claims] 1. A refrigerant-filled semiconductor device in which a semiconductor chip whose upper surface is covered with a protective insulating film is mounted on a bottom substrate of a semiconductor container, and a refrigerant is injected into the semiconductor container and sealed. A refrigerant-filled semiconductor device characterized in that a protective insulating film covering a chip has a rough upper surface. 2. The bottom substrate of the semiconductor container is made of metal,
2. A refrigerant-filled semiconductor device according to claim 1, wherein the metal substrate has a rough upper surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56173959A JPS5875860A (en) | 1981-10-30 | 1981-10-30 | Liquid-cooled semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56173959A JPS5875860A (en) | 1981-10-30 | 1981-10-30 | Liquid-cooled semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5875860A JPS5875860A (en) | 1983-05-07 |
| JPS6219074B2 true JPS6219074B2 (en) | 1987-04-25 |
Family
ID=15970215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56173959A Granted JPS5875860A (en) | 1981-10-30 | 1981-10-30 | Liquid-cooled semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5875860A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114445A (en) * | 1981-12-28 | 1983-07-07 | Fujitsu Ltd | Liquid-cooled module |
| JPS60254641A (en) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | Liquid-sealed-in package |
| JPS60254757A (en) * | 1984-05-31 | 1985-12-16 | Toshiba Corp | Part for high density mounting circuit |
| US6771500B1 (en) * | 2003-03-27 | 2004-08-03 | Stmicroelectronics, Inc. | System and method for direct convective cooling of an exposed integrated circuit die surface |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147576A (en) * | 1974-10-23 | 1976-04-23 | Hitachi Ltd | KANNAIKYUCHAKUSHIKI KATSUSEITANKYUCHAKUSOCHI |
-
1981
- 1981-10-30 JP JP56173959A patent/JPS5875860A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5147576A (en) * | 1974-10-23 | 1976-04-23 | Hitachi Ltd | KANNAIKYUCHAKUSHIKI KATSUSEITANKYUCHAKUSOCHI |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5875860A (en) | 1983-05-07 |
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