JPS58209158A - Master-slice semiconductor device - Google Patents
Master-slice semiconductor deviceInfo
- Publication number
- JPS58209158A JPS58209158A JP57092737A JP9273782A JPS58209158A JP S58209158 A JPS58209158 A JP S58209158A JP 57092737 A JP57092737 A JP 57092737A JP 9273782 A JP9273782 A JP 9273782A JP S58209158 A JPS58209158 A JP S58209158A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- input
- power
- terminal
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は集積回路装置に関し、！＃にマスタ・スライス
方式による論理集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device! # relates to a logic integrated circuit using the master slice method.
個々の入・出力端子に対応して夫々入力回路、出力回路
を有するマスク・スライス方式の論理集積回路に於ては
、七ｎら入・出力回路を構成するのに必要なトランジス
タ、抵抗等の素子群は、通常式・出力端子にほぼ対応が
つくように半導体チップ上の端子位置近次に配置さｒし
るが、上記回路を必要としない電源端子には、そｎに対
る素子群は配置さ１１ない。またケースコストを低くお
さえるために、各品植についてマスク・スライス基板で
決まる重大許容数以下の種々の必要端子数が生するのに
対応して、ケース端子数は、できるだけ必要端子数に近
いものを適用するのが好ましい。In mask-sliced logic integrated circuits that have input circuits and output circuits corresponding to individual input and output terminals, transistors, resistors, etc. necessary to configure the input and output circuits are The element groups are arranged close to the terminal positions on the semiconductor chip so that they almost correspond to the normal type/output terminals. is not placed 11. In addition, in order to keep the case cost low, the number of case terminals is as close as possible to the required number of terminals, since each product has a variety of required terminals that are less than the critical tolerance determined by the mask and sliced board. It is preferable to apply
従来のマスク・スライスに於ては、その搭載可能ゲート
数がさほど大きくなく、そｔ＋ｆ応じて、必要端子数も
高々数十端子であったのが、近年の微細加工技術の進展
と伴に搭載ゲート数が増大し、最大端子数は従来の２倍
近くを必要とするに致っている。この結果、１つのマス
ク・スライス基板から派生する種々品種の端子数の範囲
は、５０端子未満のものから、１００端子以上のものに
及び非常に多様なケースが１つのマスク・スライス基板
に適用さｎることになるため、チップ歿“計の上でチッ
プ上の電源端子位置と、ケースの電源端子位置との対応
をつけるのが１．ノ１−常に困姉になってきた。In conventional mask slicing, the number of gates that can be installed is not very large, and the number of required terminals is at most several dozen terminals depending on t + f, but with the recent progress in microfabrication technology, the number of gates that can be installed is not so large. The number of gates has increased, and the maximum number of terminals has become nearly double that of the conventional technology. As a result, the number of terminals of various products derived from one mask/slice board ranges from less than 50 terminals to more than 100 terminals, and a wide variety of cases are applied to one mask/slice board. 1. No. 1 - It has always been difficult to match the position of the power supply terminal on the chip with the position of the power supply terminal on the case on the chip scale.
本発明は、この様な実情に鑑み、多様なケース上の電源
端子位置にチップ上の電源端子位置を自由に対応させら
ｆる半導体チップを提供することを目的とし、入・出力
端子近傍で、し人・出力端子に対応して入・出力回路を
構成するのに必要な素子群を廟するマスク・スライス半
導体チップに於て、電源端子にも、上記人・出力回路の
構成に必要な素子群を対応させて配置することを特徴と
する。In view of these circumstances, the present invention aims to provide a semiconductor chip in which the position of the power supply terminal on the chip can be freely matched to the position of the power supply terminal on various cases. In a mask-sliced semiconductor chip that contains a group of elements necessary to configure the input/output circuit corresponding to the input/output terminals, the power supply terminal also includes the elements necessary for configuring the input/output circuit. It is characterized by arranging element groups in a corresponding manner.
以下図を参照しながら本発明を説明１−る。第１図は従
来方法によるマスク・スライスチップの共通パタンレイ
アウトを示すもので、１かチップ外殻、２〜８及び１７
〜２３は入力端子、９〜１６は入力にも出力にもできる
端子、２４〜２９は電源端子、３０は内部論理回路部で
羊にその全体を枠で示す。又、３１〜４４は入力回路部
、４５〜５２は入力回路と出力回路を合わせた部分で、
入力回路部３１〜３４及び入力回路と出力回路を合わせ
た部分４５〜５２のいづれもその全体を単に枠で示す。The present invention will be explained below with reference to the figures. Figure 1 shows the common pattern layout of the mask/slice chip according to the conventional method.
23 are input terminals, 9 to 16 are terminals that can be used as inputs or outputs, 24 to 29 are power supply terminals, and 30 is an internal logic circuit section, the entirety of which is shown in a frame. Further, 31 to 44 are input circuit parts, 45 to 52 are parts that combine the input circuit and the output circuit,
All of the input circuit sections 31 to 34 and the sections 45 to 52, which are a combination of input circuits and output circuits, are simply shown as frames.
又、右の一部は、左半面の折返し対線と考えて良く、図
が省略さｎている。Also, the part on the right can be considered to be a folded pair of lines on the left half, and the figure is omitted.
さて、電源端子２４〜２９には、そｆに対応する入力回
路或いは出力回路が配置さｆｌてぃない。Now, the power supply terminals 24 to 29 have no corresponding input circuit or output circuit disposed therein.
従って同チップを搭載する全てのケースのｉｉｆ源端子
は、第１図のチップを源端子２４〜２９の位置と、う１
〈対応が付く必要があり、特に、許容最大端子数を使用
する品種では、ケースに応じて電源端子位置を変更する
ことは、入・出力回路部を有し、ない、電源端子位置を
入・出力端子として使用しなけｒばならなくなり、入・
出力端子が不足してし７まうために不可能になる。Therefore, the IIF source terminals of all cases equipped with the same chip are the same as the chip in FIG.
(It is necessary to adapt the power supply terminal position depending on the case, especially for products that use the maximum allowable number of terminals.) It has to be used as an output terminal, and as an input/output terminal.
This becomes impossible due to the lack of output terminals.
第２図は、本発明を８５Ｊ明するためのチップレイアウ
ト図で、５３がチップ外殻、５４〜８１がチップ端子、
８２は、内部論理回路部、８３〜１００は入力回路部、
１０１〜１１０は入力回路と出力回路とを合わせた部分
である。第２図も第１図と同様、右の−；’Ｈ左半面と
折返し対線と考スて良く図が省略さｆている。FIG. 2 is a chip layout diagram for explaining the present invention, in which 53 is a chip outer shell, 54 to 81 are chip terminals,
82 is an internal logic circuit section, 83 to 100 are input circuit sections,
101 to 110 are a combination of an input circuit and an output circuit. Similarly to FIG. 1, FIG. 2 is omitted because it can be thought of as the left half of the right -;'H and the folded pair.
さて、第２図に於ては、チップ端子の全てに入力回路部
、又は出力回路部が対応しているので、第１図で説明し
たような、許谷琺大端子数使用時の電源端子位に変ｋに
伴う、入・出力端子不足は生じない。ところで第２図に
於て電源端子化さｎた端子部分での端子からチップ内部
への電源配線は、例えば、第３図のようになる。第３図
に於て】１１は、チップ外殻の一部１１２，１１５は夫
々再２図の端子７８及び８１に対応し、入力端子に割シ
当てらｔしたもの、１１３．１１４は、夫々第２図の端
子７９及び８０に対応し、１１３はＶＣＣ，１１４はＧ
ＮＤの夫々のｖＬ源端子に割シ当てらｎている。Now, in Figure 2, all of the chip terminals correspond to the input circuit section or the output circuit section, so the power supply terminal position when using a large number of terminals as explained in Figure 1. There will be no shortage of input/output terminals due to the change in k. By the way, the power supply wiring from the terminal to the inside of the chip at the terminal portion converted into a power supply terminal in FIG. 2 is as shown in FIG. 3, for example. In FIG. 3, parts 112 and 115 of the chip shell correspond to the terminals 78 and 81 in FIG. 2, respectively, and are assigned to input terminals, and 113 and 114 respectively Corresponding to terminals 79 and 80 in Fig. 2, 113 is VCC, 114 is G
N is assigned to each vL source terminal of the ND.
１１６〜１１９は、第２図９７〜１００に対応する入力
回路用の素子群、１２０は、端子１１４と同電位の第２
層配線１２１は端子１１３と同電位の第２１−配線で開
孔１２３〜１２６オ経由して、第１層配置１２２に飼シ
、さらに開孔１２７〜１３２を経由して、結果として端
子１１３と同電位になる第２層配線１２１に到る。116-119 are input circuit element groups corresponding to FIG. 2 97-100, and 120 is a second
The layer wiring 121 is a 21st wiring having the same potential as the terminal 113, and is connected to the first layer arrangement 122 via the openings 123 to 126, and then to the terminal 113 via the openings 127 to 132. This reaches the second layer wiring 121 which has the same potential.
１３３、１３４は、ｗ１ｔｍ＝己線１２２の内部がくり
ぬかｎていることを示す。芒て、第３図にｂｓて、入力
回路用の素子群１１７，１１８では、入力回路用の配線
接続は行なわｎず、同位置では、ＶＣＣ１３５゜０ＮＤ
１２０ の電源配線が通過するだけである。同、ここに
於て、第１廣自［゛紛１２２のくりぬき和（１３３及び
１３４は、共通マスク基板上のコンタクト用開孔部のう
ち、無祈１し得ないインピーダンスを経てチップのＧＮ
Ｄ市位に導通しているものと、ＶＣＣ亀位である第１Ｆ
ＷＩ自己紛１２２との接続をさけるために設けらｎたも
のである。133 and 134 indicate that the inside of the w1tm=self line 122 is hollowed out. 3, in the input circuit element groups 117 and 118, wiring connections for the input circuit are not made, and at the same position, VCC135°0ND
Only 120 power lines pass through it. In the same manner, here, the hollowed out sum of 122 (133 and 134 is the GN of the chip through impedance that cannot be reached among the contact openings on the common mask substrate).
The one connected to the D city level and the 1st F which is the VCC position
This is provided to avoid connection with the WI self-container 122.
以上に記し、た如く、本発明によｒば、チップ上端子の
任童位置で電源嬶子化が可能［Ｚるため、禅々のケース
の電源端子位置との対応が１中に付けらｔする。この結
果、例えば、チップ端子と、ケース端子とを接続する際
のボンディング作業に最φなチップ端子全ケースに合わ
せて決めることが可能になり、また例えばケースのイン
ダクタンスによるノイズ防止のｔめ、インタフタンスを
低減するべく、品種個別にｔ源端子数をケース、チップ
伴々、増設″４−ることも自由にできる。As described above, according to the present invention, it is possible to connect the power supply at the position of the terminal on the chip. Do t. As a result, for example, when bonding a chip terminal and a case terminal, it is possible to determine the maximum diameter chip terminal according to all cases, and also to prevent noise caused by case inductance, for example, the interface In order to reduce the electrical resistance, the number of t-source terminals can be freely increased for each type of case and chip.
同、以上では、チップ上の全端子に入・出力回路部が対
応する例を示したが一部・であっても杢゛発明の効釆が
損わ′ｎないことは明白である。In the above, an example has been shown in which the input/output circuit section corresponds to all the terminals on the chip, but it is clear that the effectiveness of the invention will not be impaired even if only a portion of the terminals correspond to the input/output circuit sections.
第１図は従来のマスク・スライスチップの素子群配置の
ようすを示す平（６）図、第２図は本発明のマスク・ス
ライスチップ素子群配置のようすを示す平面図、第３図
Ｖｉ第２図に示すチップ端子の一部を電源端子化した時
のようすを示す平面図、である。
なお図１において、１・・・・・・チップ外殻、２〜２
９・・・・・・チップ端子、３０・・・・・・内部回路
部、３１〜５２・・・・・・入出力回路部、５３・・・
・・・チップ外殻、５４〜８１・・・・・・テップ端子
、８２・・・・・・内部回路部、８３〜１１０・・・・
・・入出力回路部ｓ、１１１・・・・・・チップ外殻の
一部、１１２．１１５・・・・・・イハ号片端子、１１
６〜１１９・・・入力回路用素子群、１１３，１１４・
・・・・・竜シ柑端子、１２０．１２１．、１３５−−
−−−−％２Ｗｔ配線、１２３〜１２６、 １２７〜１
３２・・・・・・プ、１層配線と第２層配置詠を接続す
るｌこめの一部、１２２・・・・・・第１−配線、１３
３１３４・・・・・・ｋｓ１層配嶽１２２の内部のくり
ぬき部分、を示す。
第１ 圀
茶２ 図
第３図FIG. 1 is a plan view (6) showing the arrangement of elements in a conventional mask/slice chip, FIG. 2 is a plan view showing the arrangement of elements in a mask/slice chip according to the present invention, and FIG. FIG. 2 is a plan view showing a state in which a part of the chip terminal shown in FIG. 2 is converted into a power supply terminal. In addition, in FIG. 1, 1... Chip outer shell, 2-2
9... Chip terminal, 30... Internal circuit section, 31-52... Input/output circuit section, 53...
... Chip outer shell, 54-81 ... Tip terminal, 82 ... Internal circuit section, 83-110 ...
...Input/output circuit section s, 111...Part of chip outer shell, 112.115...Iha number piece terminal, 11
6 to 119... Input circuit element group, 113, 114.
...Ryushikan terminal, 120.121. , 135--
-----%2Wt wiring, 123-126, 127-1
32...P, part of the l-piece connecting the first layer wiring and the second layer layout, 122...1st wiring, 13
3134 . . . indicates a hollowed out portion inside the ks1 layer casing 122. Part 1 Kunicha 2 Figure 3
Claims (1)
力回路を構成するのに必要な素子群を肩するマスク・ス
ライス半導体チップに於て、電源端子にも上記人・出力
回路の構成に必要な素子群を対応させて配置することを
特徴とするマスタデスライス半導体装置。In the mask/slice semiconductor chip that carries the necessary elements to configure the input/output circuits corresponding to the input/output terminals near the input/output terminals, the power supply terminals also include the above-mentioned input/output circuits. A master deslice semiconductor device characterized in that element groups necessary for the configuration are arranged in correspondence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57092737A JPS58209158A (en) | 1982-05-31 | 1982-05-31 | Master-slice semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57092737A JPS58209158A (en) | 1982-05-31 | 1982-05-31 | Master-slice semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58209158A true JPS58209158A (en) | 1983-12-06 |
| JPH0141032B2 JPH0141032B2 (en) | 1989-09-01 |
Family
ID=14062725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57092737A Granted JPS58209158A (en) | 1982-05-31 | 1982-05-31 | Master-slice semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58209158A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5941852A (en) * | 1982-06-24 | 1984-03-08 | ストレイジ・テクノロジ−・パ−トナ−ズ | Integrated circuit chip |
| JPS59139646A (en) * | 1983-01-31 | 1984-08-10 | Hitachi Micro Comput Eng Ltd | Semiconductor integrated circuit device |
| JPS59159557A (en) * | 1983-03-01 | 1984-09-10 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS61204957A (en) * | 1985-03-08 | 1986-09-11 | Hitachi Ltd | Large scale integrated circuit device |
| JPS61263241A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | Gate array |
| EP0563973A2 (en) * | 1992-04-01 | 1993-10-06 | Nec Corporation | Master slice integrated circuit having a reduced chip size and a reduced power supply noise |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5493375A (en) * | 1977-12-30 | 1979-07-24 | Fujitsu Ltd | Semiconductor integrated circuit device |
| JPS5561054A (en) * | 1978-10-30 | 1980-05-08 | Mitsubishi Electric Corp | Large scale integrated circuit |
| JPS58197746A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1982
- 1982-05-31 JP JP57092737A patent/JPS58209158A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5493375A (en) * | 1977-12-30 | 1979-07-24 | Fujitsu Ltd | Semiconductor integrated circuit device |
| JPS5561054A (en) * | 1978-10-30 | 1980-05-08 | Mitsubishi Electric Corp | Large scale integrated circuit |
| JPS58197746A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5941852A (en) * | 1982-06-24 | 1984-03-08 | ストレイジ・テクノロジ−・パ−トナ−ズ | Integrated circuit chip |
| JPS59139646A (en) * | 1983-01-31 | 1984-08-10 | Hitachi Micro Comput Eng Ltd | Semiconductor integrated circuit device |
| JPS59159557A (en) * | 1983-03-01 | 1984-09-10 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH0465547B2 (en) * | 1983-03-01 | 1992-10-20 | Hitachi Ltd | |
| JPS61204957A (en) * | 1985-03-08 | 1986-09-11 | Hitachi Ltd | Large scale integrated circuit device |
| JPS61263241A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | Gate array |
| EP0563973A2 (en) * | 1992-04-01 | 1993-10-06 | Nec Corporation | Master slice integrated circuit having a reduced chip size and a reduced power supply noise |
| EP0563973A3 (en) * | 1992-04-01 | 1994-08-10 | Nec Corp | Master slice integrated circuit having a reduced chip size and a reduced power supply noise |
| US5422441A (en) * | 1992-04-01 | 1995-06-06 | Nec Corporation | Master slice integrated circuit having a reduced chip size and a reduced power supply noise |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0141032B2 (en) | 1989-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02163960A (en) | Semiconductor device | |
| US6770493B2 (en) | Integrated circuit package capable of operating in multiple orientations | |
| JP2560805B2 (en) | Semiconductor device | |
| JPS58209158A (en) | Master-slice semiconductor device | |
| JPS61222148A (en) | Manufacture of one-chip microcomputer | |
| JP2681427B2 (en) | Semiconductor device | |
| JP3228589B2 (en) | Multi-chip module | |
| JPH03259561A (en) | Semiconductor device | |
| JPH08306734A (en) | Integrated circuit device with bonding pad option and methodof executing bonding pad option | |
| JPH04349640A (en) | Analog-digital hybrid integrated circuit device package | |
| JP3179415B2 (en) | Semiconductor integrated circuit device and circuit selection method thereof | |
| JPH02306650A (en) | Semiconductor device | |
| JPH01132150A (en) | Carrier substrate of semiconductor chip | |
| KR100282994B1 (en) | Semiconductor integrated circuit device with functional circuit | |
| JPH058576B2 (en) | ||
| KR100487502B1 (en) | Microcomputer using triple wire bonding for noise prohibition | |
| JPS6089955A (en) | Semiconductor device | |
| KR100310380B1 (en) | Integrated circuit | |
| JPS6126940Y2 (en) | ||
| JPS59193057A (en) | Memory decoder circuit | |
| JPH0372655A (en) | Semiconductor integrated circuit device | |
| JPS632149B2 (en) | ||
| JPS6376345A (en) | Construction of output macro cell | |
| JPS58182841A (en) | Monolithic integrated circuit | |
| JPS6221240A (en) | Manufacture of semiconductor device |