JPH0465547B2 - - Google Patents
Info
- Publication number
- JPH0465547B2 JPH0465547B2 JP58033279A JP3327983A JPH0465547B2 JP H0465547 B2 JPH0465547 B2 JP H0465547B2 JP 58033279 A JP58033279 A JP 58033279A JP 3327983 A JP3327983 A JP 3327983A JP H0465547 B2 JPH0465547 B2 JP H0465547B2
- Authority
- JP
- Japan
- Prior art keywords
- buffer circuit
- circuit cell
- signal buffer
- cell group
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000872 buffer Substances 0.000 claims description 97
- 230000002457 bidirectional effect Effects 0.000 claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 26
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 230000003139 buffering effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体集積回路装置に関し、詳しく
は、半導体基体の周辺部に配置される入出力緩衝
回路セル群における出力信号緩衝回路セル群と双
方向信号緩衝回路セル群の配置関係の改良に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device, and more specifically, to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device that is connected to a group of output signal buffer circuit cells in a group of input/output buffer circuit cells disposed around a semiconductor substrate. This invention relates to improvements in the arrangement of signal buffer circuit cell groups.
半導体集積回路装置は半導体基体上に多数の回
路セルを形成し、個々の回路セルの内部接続およ
び回路セルの相互接続、および外部ピンとの接続
には半導体基体上に絶縁体を介して積層された２
層以上の配線層を用いることが多い。また半導体
基体の内部側に内部回路セル群が形成され、周辺
部に入出力緩衝回路セル群が形成されるのが普通
であり、入出力緩衝回路セルは電気的強度および
駆動能力を内部回路セルよりも強化してある。
A semiconductor integrated circuit device has a large number of circuit cells formed on a semiconductor substrate, and the internal connections of individual circuit cells, interconnections of circuit cells, and connections with external pins are made by laminating layers on the semiconductor substrate via insulators. 2
In many cases, more than one wiring layer is used. In addition, it is common for an internal circuit cell group to be formed inside the semiconductor substrate, and an input/output buffer circuit cell group to be formed on the periphery. It has been strengthened.
また、内部回路セル群と外部との間で授受する
信号の緩衝を行う入出力緩衝回路セルとしては、
入力信号緩衝回路セル、出力信号緩衝回路セル、
入出力兼用の双方向信号緩衝回路セルの３種類が
一般にある。出力信号緩衝回路セルや双方向信号
緩衝回路セのシンク電流が流れる電源幹線（一般
に接地される）は、電流容量が大きく、また電位
変動をきらうため、配線幅を大きくして分布抵抗
を減少させる必要がある。しかし、このような幅
広の電源幹線は、何本も設けるのは集積度向上の
妨げとなるため、出力信号緩衝回路セルと双方向
信号緩衝回路セルとに共通の１本の配線ラインと
して形成することが多い。 In addition, as an input/output buffer circuit cell that buffers signals exchanged between the internal circuit cell group and the outside,
Input signal buffer circuit cell, output signal buffer circuit cell,
There are generally three types of bidirectional signal buffer circuit cells that serve both input and output. The power supply main line (generally grounded) through which the sink current of the output signal buffer circuit cell and bidirectional signal buffer circuit cell flows has a large current capacity and is sensitive to potential fluctuations, so the wiring width is increased to reduce distributed resistance. There is a need. However, providing multiple such wide power supply main lines impedes the improvement of the degree of integration, so they are formed as a single wiring line common to the output signal buffer circuit cell and the bidirectional signal buffer circuit cell. There are many things.
第１図はこのような従来の半導体集積回路装置
の回路セルのレイアウトを略示する平面図であ
り、配線パターンは省略してある。 FIG. 1 is a plan view schematically showing the layout of circuit cells of such a conventional semiconductor integrated circuit device, and wiring patterns are omitted.
第１図において、半導体チツプ１は内部領域２
と周辺部領域３とから成る。内部領域２には内部
回路を形成する内部回路セル４が縦横に複数個配
列されている。内部回路セル４相互間の領域５は
配線領域である。周辺部領域３には複数個の入出
力緩衝回路セル６が内部領域を囲むようにして環
状に配置されている。入出力緩衝回路セル６には
入力信号緩衝回路セルＩ，出力信号緩衝回路セル
Ｏ，双方向信号緩衝回路セルＰの３種類がある。
これら３種類の入出力緩衝回路セルは周辺部領域
３内に不規則な順序で配置されている。なお双方
向信号緩衝回路セルＰは入力信号緩衝回路セルＩ
と出力信号緩衝回路セルＯが対をなしたものであ
る。各入出力緩衝回路セル６は信号用ボンデイン
グパツド１０を介して半導体チツプ塔載パツケー
ジ上の信号ピン（図示していない）と接続され
る。 In FIG. 1, a semiconductor chip 1 has an internal region 2.
and a peripheral region 3. In the internal region 2, a plurality of internal circuit cells 4 forming an internal circuit are arranged vertically and horizontally. A region 5 between internal circuit cells 4 is a wiring region. In the peripheral region 3, a plurality of input/output buffer circuit cells 6 are arranged in a ring shape so as to surround the inner region. There are three types of input/output buffer circuit cells 6: input signal buffer circuit cells I, output signal buffer circuit cells O, and bidirectional signal buffer circuit cells P.
These three types of input/output buffer circuit cells are arranged in an irregular order within the peripheral region 3. Note that the bidirectional signal buffer circuit cell P is the input signal buffer circuit cell I.
and output signal buffer circuit cell O form a pair. Each input/output buffer circuit cell 6 is connected to a signal pin (not shown) on a semiconductor chip mounting package via a signal bonding pad 10.
第２図は第１図の周辺部領域３の一部を拡大し
た図である。周辺部領域３には複数本の電源幹線
が内部領域２を囲むように配線されている。該電
源幹線は本例では３本ある。１本は内部回路セル
４および入出力緩衝回路セル６にドレイン電位を
供給する電源幹線１１である。もう１本は内部回
路セル４および入力信号緩衝回路セルＩにソース
電位を供給する電源幹線１２である。残りの１本
は出力信号緩衝回路セルＯおよび双方向信号緩衝
回路セルＰにソース電位を供給する電源幹線１３
である。電源幹線１１はボンデイングパツド１４
と、電源幹線１２はボンデイングパツド１５と、
電源幹線１３はボンデイングパツド１６とそれぞ
れ接続されている。ボンデイングパツド１４，１
５，１６は周辺部領域３にそれぞれ複数個存在す
るが、これらは半導体チツプ搭載パツケージ上の
給電ピン（図示していない）と接続される。第１
図においては、これら３種のボンデイングパツド
のうち電源幹線１３用のボンデイングパツド１
６，１６ａ，１６ｂのみ示してある。 FIG. 2 is an enlarged view of a part of the peripheral region 3 of FIG. A plurality of power main lines are wired in the peripheral area 3 so as to surround the internal area 2 . In this example, there are three power main lines. One is a power supply main line 11 that supplies drain potential to the internal circuit cell 4 and the input/output buffer circuit cell 6. The other line is a power supply main line 12 that supplies source potential to the internal circuit cell 4 and the input signal buffer circuit cell I. The remaining one is a power supply main line 13 that supplies source potential to the output signal buffer circuit cell O and the bidirectional signal buffer circuit cell P.
It is. The power main line 11 is connected to the bonding pad 14
And, the power main line 12 is connected to the bonding pad 15,
The power main lines 13 are connected to bonding pads 16, respectively. Bonding pad 14,1
A plurality of numerals 5 and 16 exist in the peripheral region 3, and these are connected to power supply pins (not shown) on the semiconductor chip mounting package. 1st
In the figure, of these three types of bonding pads, bonding pad 1 for the power main line 13 is shown.
Only 6, 16a, and 16b are shown.
さて、電源幹線１１，１２，１３はいずれも分
布抵抗を有するため、そこに流れる電流値が変化
すると各位置の電位が変動する。この電位変動
は、ノイズマージンが一般に大きなドレイン電位
を供給するための電源幹線１１についてはあまり
問題にならないが、ノイズマージンが一般に小さ
く変動をきらうソース電位を供給するための電源
幹線１２，１３については、ノイズの発生原因と
なるので重大である。特に、出力信号緩衝回路セ
ルＯと双方向信号緩衝回路セルＰのシンク電流が
共通に流れる電源幹線１３については、次に述べ
るような問題があつた。 Now, since the power supply main lines 11, 12, and 13 all have distributed resistance, when the value of the current flowing therein changes, the potential at each position changes. This potential fluctuation is not so much of a problem for the power supply main line 11 that supplies the drain potential, which generally has a large noise margin, but for the power supply main lines 12 and 13 that supply the source potential, which generally has a small noise margin and does not want to fluctuate. This is important because it causes noise. In particular, the following problem occurred regarding the power main line 13 through which the sink currents of the output signal buffer circuit cell O and the bidirectional signal buffer circuit cell P commonly flow.
第３図は、出力信号緩衝回路セルＯと双方向信
号緩衝回路セルＰに共通の電源幹線１３の電位変
動の影響を説明するための回路図である。電源幹
線１３は図示のように、入出力緩衝回路セル６の
配列ピツチ当り分布抵抗r2を有する。半導体集積
回路装置を使用する場合、ボンデイングパツド１
６と接続の給電ピンは接地される。r3はボンデイ
ングパツド１６と外部ピンとの間のボンデイング
ワイヤ等の抵抗を示す。Ｑ１とＱ２は双方向信号
緩衝回路セルＰの出力例回路を構成するＰチヤネ
ル型とＮチヤネル型のMOSトランジスタであり、
MOSトランジスタＱ２のソースは電源幹線１３
と接続され、MOSトランジスタＱ１のドレイン
は電源幹線１１と接続される。 FIG. 3 is a circuit diagram for explaining the influence of potential fluctuations on the power main line 13 common to the output signal buffer circuit cell O and the bidirectional signal buffer circuit cell P. As shown, the power supply main line 13 has a distributed resistance r 2 per arrangement pitch of the input/output buffer circuit cells 6. When using a semiconductor integrated circuit device, bonding pad 1
The power supply pin connected to 6 is grounded. r3 represents the resistance of the bonding wire or the like between the bonding pad 16 and the external pin. Q1 and Q2 are P-channel type and N-channel type MOS transistors that constitute the output example circuit of the bidirectional signal buffer circuit cell P,
The source of MOS transistor Q2 is the power supply main line 13
The drain of the MOS transistor Q1 is connected to the power main line 11.
双方向信号緩衝回路セルＰの入力信号が高電位
になると、MOSトランジスタＱ２はゲート電位
がソース電位より高くなり導通し、出力端子１８
からのシンク電流IOLが電源幹線１３へ流れ込む。
今、第３図において左端側の双方向信号緩衝回路
セルＰのみ、入力信号が高電位となつた場合、そ
の位置での電源幹線１３の電位V1は次式で表わ
される（シンク電流は１つのボンデイングパツド
１６側へのみ流れるとする）。 When the input signal of the bidirectional signal buffer circuit cell P becomes a high potential, the gate potential of the MOS transistor Q2 becomes higher than the source potential and conducts, and the output terminal 18 becomes conductive.
A sink current IOL flows into the power supply main line 13.
Now, if the input signal becomes high potential only in the bidirectional signal buffer circuit cell P on the left side in FIG . (assuming that it flows only to the two bonding pads 16 side).
V1＝（2r2＋r3）IOL
この時、図中の右端側の出力信号緩衝回路Ｏの
位置での電位V2も上記V1と同電位まで上昇する。 V 1 =(2r 2 +r 3 )I OL At this time, the potential V 2 at the position of the output signal buffer circuit O on the right side in the figure also rises to the same potential as the above V 1 .
また、図中の中央の双方向信号緩衝回路セルＰ
からのみシンク電流が電源幹線１３に流れ込む
と、上記の出力信号緩衝回路セルＯの位置での電
位V2は次式のレベルまで上昇する。 Also, the bidirectional signal buffer circuit cell P in the center of the figure
When a sink current flows into the power main line 13 only from V, the potential V2 at the position of the output signal buffer circuit cell O rises to the level expressed by the following equation.
V2＝（4r2＋r3）IOL
このように、双方向信号緩衝回路セルＰからシ
ンク電流が電源幹線１３に流入すると、その近傍
にある出力信号緩衝回路セルＯの接続点における
電源幹線１３の電位も上昇する。そして、このよ
うな電位の上昇量は、シンク電流の流入点がボン
デイングパツド１６から遠いほど大きくなる。 V 2 = (4r 2 + r 3 )I OL In this way, when the sink current flows from the bidirectional signal buffer circuit cell P into the power supply main line 13, the power supply main line 13 at the connection point of the output signal buffer circuit cell O located nearby The potential of will also increase. The amount of increase in potential increases as the inflow point of the sink current is farther away from the bonding pad 16.
一般に、出力信号緩衝回路セルＯは、その接続
点における電源幹線１３の電位があるレベル以上
に上昇すると、出力信号にノイズを発生する。こ
のノイズが一定レベル（スレツシユホールドレベ
ル）を超えると、該出力信号緩衝回路セルＯの出
力信号の伝搬先に存在する回路を誤動作させてし
まう。したがつて、各出力信号緩衝回路セルＯの
接続点における電源幹線１３の電位の上昇を極力
抑える必要があり、そのためには、双方向信号緩
衝回路セルＰのシンク電流の流入点をボンデイン
グパツド１６に極力近づける必要がある。 Generally, the output signal buffer circuit cell O generates noise in the output signal when the potential of the power main line 13 at its connection point rises above a certain level. If this noise exceeds a certain level (threshold level), the circuits present at the propagation destination of the output signal of the output signal buffer circuit cell O will malfunction. Therefore, it is necessary to suppress the increase in the potential of the power main line 13 at the connection point of each output signal buffer circuit cell O as much as possible. It is necessary to get it as close to 16 as possible.
しかるに従来は、第１図および第３図に示すよ
うに、出力信号緩衝回路セルＯ，入力信号緩衝回
路セルＩ，双方向信号緩衝回路セルＰを混在配置
していたため、すべての双方向信号緩衝回路セル
Ｐを上記の条件を完全に満足させるように配置す
ることは困難であり、動作条件によつては一部の
出力信号緩衝回路セルＯの出力信号に大きなノイ
ズが発生することがあつた。即ち、前述の説明で
は１個の双方向信号緩衝回路セルＰからシンク電
流が流入する場合を想定したが、実際的には双方
向信号緩衝回路セルＰの入力信号は同時に切り換
わる確率の高いデータバス系信号の場合が多く、
複数の双方向信号緩衝回路セルＰから同時に電源
幹線１３にシンク電流が流入することがある。例
えば、４バイト幅（パリテイビツトを含めて36ビ
ツト）のデータバス系信号を双方向信号緩衝回路
セルＰで緩衝する場合、最悪ケースでは36個の双
方向回路セルＰから同時に流入するシンク電流が
重畳して電源幹線１３に流れることになり、出力
信号緩衝回路セルＯの出力信号にスレツシユホー
ルドレベルを越える大きなノイズが発生するとい
う問題があつた。 However, in the past, as shown in FIGS. 1 and 3, output signal buffer circuit cell O, input signal buffer circuit cell I, and bidirectional signal buffer circuit cell P were arranged in a mixed manner. It is difficult to arrange the circuit cells P so as to completely satisfy the above conditions, and depending on the operating conditions, large noise may occur in the output signals of some output signal buffer circuit cells O. . That is, in the above explanation, it was assumed that a sink current flows from one bidirectional signal buffer circuit cell P, but in reality, the input signals of the bidirectional signal buffer circuit cell P are data with a high probability of switching simultaneously. Often bus signals,
Sink currents may simultaneously flow into the power main line 13 from a plurality of bidirectional signal buffer circuit cells P. For example, when buffering a data bus signal with a width of 4 bytes (36 bits including parity bits) using a bidirectional signal buffer circuit cell P, in the worst case, sink currents flowing simultaneously from 36 bidirectional circuit cells P will overlap. This causes a problem in that large noise exceeding the threshold level is generated in the output signal of the output signal buffer circuit cell O.
本発明の目的は、上記問題を解消した半導体集
積回路装置を提供することにある。
An object of the present invention is to provide a semiconductor integrated circuit device that solves the above problems.
本発明は、前述のような半導体集積回路装置に
おいて、双方向緩衝回路セル群と出力信号緩衝回
路セル群の共通のシンク電流路を形成している電
源幹線の第１のボンデイングパツドの近傍領域に
は双方向信号緩衝回路セル群を集中配置し、該第
１のボンデイングパツドに対して充分離れた位置
の第２のボンデイングパツドの近傍領域には出力
信号緩衝回路群を集中配置することにより、該出
力信号緩衝回路セル群の出力信号に発生するノイ
ズを低減するものである。
The present invention provides a semiconductor integrated circuit device as described above, in which a region near a first bonding pad of a power main line forming a common sink current path for a bidirectional buffer circuit cell group and an output signal buffer circuit cell group is provided. A bidirectional signal buffer circuit cell group is arranged in a concentrated manner, and an output signal buffer circuit group is arranged in a concentrated manner in a region near a second bonding pad that is sufficiently distant from the first bonding pad. This reduces the noise generated in the output signal of the output signal buffer circuit cell group.
以下、第４図および第５図により本発明の一実
施例を説明する。
An embodiment of the present invention will be described below with reference to FIGS. 4 and 5.
第４図は本発明に係る半導体集積回路装置の概
略平面図であり、第１図および第２図と対応する
部分には同一の参照番号または参照記号を付して
ある。 FIG. 4 is a schematic plan view of a semiconductor integrated circuit device according to the present invention, and parts corresponding to those in FIGS. 1 and 2 are given the same reference numbers or symbols.
本実施例と前述の従来例との相異点は、電源幹
線１３の１方のボンデイングパツド１６ａの近傍
領域に、入出力緩衝回路セル６のうちすべての双
方向信号緩衝回路セルＰを集中させて配置したこ
とと、すべての出力信号緩衝回路セルＯを他方の
ボンデイングパツド１６ｂの近傍領域に集中配置
したこと、および、その結果として、入力信号緩
衝回路セルＩは図示のように配置が変更になつて
いることである。なお、各入出力緩衝回路セル６
の上記のような配置変更に伴い、内部回路セル４
の配列や配線の変更が必要となる場合があるが、
これは一般の設計手法で対応できることであり、
また本発明の要旨ではないので詳細は省略する。
また、図示しない他の電源幹線（第２図の１１，
１２）は従来と同様である。 The difference between this embodiment and the conventional example described above is that all the bidirectional signal buffer circuit cells P of the input/output buffer circuit cells 6 are concentrated in the vicinity of one bonding pad 16a of the power main line 13. As a result, the input signal buffer circuit cells I are arranged as shown in the figure. Things are about to change. In addition, each input/output buffer circuit cell 6
Due to the above-mentioned layout change, the internal circuit cell 4
It may be necessary to change the arrangement or wiring of the
This can be handled using general design methods,
Further, since this is not the gist of the present invention, details will be omitted.
In addition, other power supply main lines (11 in Fig. 2,
12) is the same as before.
このような構成にした効果を第５図によつて説
明する。なお、図中のr2，r3は第３図中の同符号
と同じ分布抵抗を意味し、また双方向信号緩衝回
路セルＰの回路構成も従来と同様である。 The effect of such a configuration will be explained with reference to FIG. Note that r 2 and r 3 in the figure mean the same distributed resistances as the same symbols in FIG. 3, and the circuit configuration of the bidirectional signal buffer circuit cell P is also the same as the conventional one.
説明を単純化するために、双方向信号緩衝回路
セルＰから電源幹線１３に流入したシンク電流は
ボンデイングパツド１６ａ側へのみ流れ、他方の
ボンデイングパツド１６ｂ側へは分流しないもの
とする。双方向信号緩衝回路セルＰのシンク電流
によつて最も電位が上昇するのはＡ点であるが、
このＡ点の電位上昇量はＡ点からボンデイングパ
ツド１６ａまでの分布抵抗r2の総和Σr2が大きい
ほど大きくなる。このΣr2の値はＡ点からボンデ
イングパツド１６ａまでの線長ｌに比例するが、
本発明では双方向信号緩衝回路セルＰのみ集中し
て配置するので、従来のように入力信号緩衝回路
セルＩや出力信号緩衝回路セルＯを介在させた場
合よりも上記線長ｌを短かくでき、Σr2も減小す
るから、Ａ点の電位上昇量（接地電位に対する上
昇量）は従来より減少する。 To simplify the explanation, it is assumed that the sink current flowing into the power main line 13 from the bidirectional signal buffer circuit cell P flows only to the bonding pad 16a side, and does not flow to the other bonding pad 16b side. The point where the potential increases the most due to the sink current of the bidirectional signal buffer circuit cell P is at point A.
The amount of potential increase at point A increases as the sum Σr 2 of the distributed resistances r 2 from point A to bonding pad 16a increases. The value of Σr 2 is proportional to the line length l from point A to bonding pad 16a,
In the present invention, since only the bidirectional signal buffer circuit cells P are arranged in a concentrated manner, the line length l can be made shorter than when input signal buffer circuit cells I and output signal buffer circuit cells O are interposed as in the conventional case. , Σr 2 are also reduced, so the amount of potential rise at point A (the amount of rise relative to the ground potential) is smaller than before.
ここで、他方のボンデイングパツド１６ｂが非
接地であると仮定しよう。各出力信号緩衝回路セ
ルＯの接続点における電位はＡ点と同じ電位まで
上昇するが、この電位上昇量は従来における最悪
ケースとなる出力信号緩衝回路セルＯの接続点電
位の上昇量より減少することは明らかである。し
たがつて、出力信号緩衝回路セルＯのノイズレベ
ルを従来より下げることができる。 Let us now assume that the other bonding pad 16b is ungrounded. The potential at the connection point of each output signal buffer circuit cell O rises to the same potential as point A, but the amount of increase in potential is smaller than the amount of increase in the potential at the connection point of output signal buffer circuit cell O, which is the worst case in the conventional case. That is clear. Therefore, the noise level of the output signal buffer circuit cell O can be lowered than before.
本実施例では、ノイズレベルは更に低下する。
即ち、ボンデイングパツド１６ｂを接地すると、
各出力信号緩衝回路セルＯの接続点の電位は、Ａ
点からボンデイングパツド１６ｂまでの分布抵抗
r2の直列回路によつてＡ点電位を分圧したものと
なり、Ａ点電位より相当に低くなるからである。
この分圧効下を最大限に発揮させるために、本実
施例においては、ボンデイングパツド１６ｂをボ
ンデイングパツド１６ａから最も遠い位置に配置
するとともに、出力信号緩衝回路セルＯをボンデ
イングパツド１６ｂの近傍に集中配置し、以て出
力信号緩衝回路セルＯの出力信号に発生するノイ
ズを可及的に低レベルに抑えている。 In this example, the noise level is further reduced.
That is, when the bonding pad 16b is grounded,
The potential at the connection point of each output signal buffer circuit cell O is A
Distributed resistance from point to bonding pad 16b
This is because the potential at point A is divided by the series circuit of r2 , and is considerably lower than the potential at point A.
In order to make the most of this partial voltage effect, in this embodiment, the bonding pad 16b is placed at the farthest position from the bonding pad 16a, and the output signal buffer circuit cell O is placed at the farthest position from the bonding pad 16b. By arranging them in a concentrated manner in the vicinity, the noise generated in the output signal of the output signal buffer circuit cell O is suppressed to the lowest possible level.
なお、内部回路セル４との配線関係等で、出力
信号緩衝回路セルＯだけを集中配置することが困
難な場合もあり得る。その場合、上記の分圧効果
の犠牲を伴うが、一部の入力信号緩衝回路セルＩ
を出力信号緩衝回路セルＯと混在して配置するこ
とも可能である。また、可能であれば、電源幹線
１３のボンデイングパツドを３個以上設けてもよ
い。 Note that it may be difficult to centrally arrange only the output signal buffer circuit cells O due to the wiring relationship with the internal circuit cells 4 and the like. In that case, some of the input signal buffer circuit cells I
It is also possible to arrange them together with the output signal buffer circuit cell O. Furthermore, if possible, three or more bonding pads for the power main line 13 may be provided.
以上、CMOS回路構成の半導体集積回路装置
の例について詳述したが、本発明は他の回路構成
の半導体集積装置についても適用し得るものであ
る。 Although an example of a semiconductor integrated circuit device with a CMOS circuit configuration has been described above in detail, the present invention can also be applied to semiconductor integrated devices with other circuit configurations.
以上に詳述したように、本発明によれば、半導
体集積回路装置において、双方向信号緩衝回路セ
ル群と出力信号緩衝回路セル群の共通のシンク電
流路を形成している電源幹線の第１の給電用ボン
デイングパツドの近傍領域に双方向信号緩衝回路
セル群を集中的に配置したので、双方向信号緩衝
回路セルのシンク電流による電位上昇を減ずるこ
とができ、さらに、上記第１の給電用ボンデイン
グパツドとは充分離れた位置の第２の給電用ボン
デイングパツドの近傍領域に出力信号緩衝回路セ
ル群を集中的に配置したので、出力信号緩衝回路
セルの該電源幹線との接続点の電位をさらに低く
することができ、これらの結果、出力緩衝回路セ
ルの出力信号に発生するノイズを可及的に低減す
ることができ、この種の半導体集積回路装置の誤
動作を防ぎ、信頼性を向上させることができる。
As described in detail above, according to the present invention, in a semiconductor integrated circuit device, the first power supply main line forming a common sink current path for the bidirectional signal buffer circuit cell group and the output signal buffer circuit cell group Since the bidirectional signal buffer circuit cells are arranged in a concentrated manner in the vicinity of the bonding pad for power feeding, it is possible to reduce the potential rise due to the sink current of the bidirectional signal buffer circuit cells. Since the output signal buffer circuit cells are centrally arranged in the vicinity of the second power supply bonding pad, which is sufficiently far away from the second power supply bonding pad, the connection point between the output signal buffer circuit cells and the main power supply line is As a result, the noise generated in the output signal of the output buffer circuit cell can be reduced as much as possible, preventing malfunction of this type of semiconductor integrated circuit device and improving reliability. can be improved.
第１図は従来の半導体集積回路装置の一例を示
す概略平面図、第２図は第１図の一部の拡大平面
図、第３図は同従来例の問題点を説明するための
回路図、第４図は本発明の一実施例を示す概略平
面図、第５図は同実施例における基準電位変動お
よびノイズレベルの抑制効果を説明するための回
路図である。
１…半導体チツプ、６…入出力緩衝回路セル
（Ｉ…入力信号緩衝回路セル、Ｏ…出力信号緩衝
回路セル、Ｐ…双方向信号緩衝回路セル）、１３
…電源幹線（シンク電流路）、１６ａ，１６ｂ…
ボンデイングパツド。
Fig. 1 is a schematic plan view showing an example of a conventional semiconductor integrated circuit device, Fig. 2 is an enlarged plan view of a part of Fig. 1, and Fig. 3 is a circuit diagram for explaining the problems of the conventional example. , FIG. 4 is a schematic plan view showing one embodiment of the present invention, and FIG. 5 is a circuit diagram for explaining the effect of suppressing reference potential fluctuation and noise level in the same embodiment. 1... Semiconductor chip, 6... Input/output buffer circuit cell (I... Input signal buffer circuit cell, O... Output signal buffer circuit cell, P... Bidirectional signal buffer circuit cell), 13
...Power main line (sink current path), 16a, 16b...
Bonding Pad.
Claims (1)
備し、該半導体基体の周辺領域には、前記内部回
路セル群と外部との間の信号の緩衝を行うための
入力信号緩衝回路セル群と出力信号緩衝回路セル
群と双方向信号緩衝回路セル群からなる入出力緩
衝回路セル群と、前記内部回路セル群と前記入出
力緩衝回路セル群にソース電位とドレイン電位を
供給するための複数の電源幹線と、前記入出力緩
衝回路セル群と接続されて外部との信号の送受口
となる信号用ボンデイングパツド群と、前記電源
幹線と接続されて外部からの給電口となる複数の
給電用ボンデイングパツドを具備してなる半導体
集積回路装置において、 前記複数の電源幹線のうち少なくとも前記出力
信号緩衝回路セル群と双方向信号緩衝回路セル群
にソース電位を供給するための電源幹線を共通化
し、該電源幹線に接続される給電用ボンデイング
パツドとして第１パツドと第２パツドを互いに離
れた位置に設け、前記第１パツドの近傍領域に前
記双方向信号緩衝回路セル群を集中配置し、前記
第２パツドの近傍領域に前記出力信号緩衝回路セ
ル群を集中配置したことを特徴とする半導体集積
回路装置。[Claims] 1. An internal circuit cell group is provided in an internal region of a semiconductor substrate, and an input signal for buffering signals between the internal circuit cell group and the outside is provided in a peripheral region of the semiconductor substrate. Supplying a source potential and a drain potential to an input/output buffer circuit cell group consisting of a buffer circuit cell group, an output signal buffer circuit cell group, and a bidirectional signal buffer circuit cell group, the internal circuit cell group, and the input/output buffer circuit cell group. a plurality of power supply main lines for the purpose of transmitting power, a group of signal bonding pads connected to the input/output buffer circuit cell group and serving as a port for transmitting and receiving signals from the outside, and a group of signal bonding pads connected to the power supply main line and serving as a power supply port from the outside. In a semiconductor integrated circuit device comprising a plurality of power supply bonding pads, one of the plurality of power supply main lines is for supplying a source potential to at least the output signal buffer circuit cell group and the bidirectional signal buffer circuit cell group. A power supply main line is shared, a first pad and a second pad are provided at positions separated from each other as power supply bonding pads connected to the power supply main line, and the bidirectional signal buffer circuit cell group is provided in a region near the first pad. A semiconductor integrated circuit device characterized in that the output signal buffer circuit cells are arranged in a concentrated manner in a region near the second pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58033279A JPS59159557A (en) | 1983-03-01 | 1983-03-01 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58033279A JPS59159557A (en) | 1983-03-01 | 1983-03-01 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59159557A JPS59159557A (en) | 1984-09-10 |
| JPH0465547B2 true JPH0465547B2 (en) | 1992-10-20 |
Family
ID=12382085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58033279A Granted JPS59159557A (en) | 1983-03-01 | 1983-03-01 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59159557A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59167036A (en) * | 1983-03-14 | 1984-09-20 | Nec Corp | Semiconductor integrated circuit |
| US5015600A (en) * | 1990-01-25 | 1991-05-14 | Northern Telecom Limited | Method for making integrated circuits |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58209158A (en) * | 1982-05-31 | 1983-12-06 | Nec Corp | Master-slice semiconductor device |
-
1983
- 1983-03-01 JP JP58033279A patent/JPS59159557A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58209158A (en) * | 1982-05-31 | 1983-12-06 | Nec Corp | Master-slice semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59159557A (en) | 1984-09-10 |
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