JPH0141032B2 - - Google Patents

Info

Publication number
JPH0141032B2
JPH0141032B2 JP57092737A JP9273782A JPH0141032B2 JP H0141032 B2 JPH0141032 B2 JP H0141032B2 JP 57092737 A JP57092737 A JP 57092737A JP 9273782 A JP9273782 A JP 9273782A JP H0141032 B2 JPH0141032 B2 JP H0141032B2
Authority
JP
Japan
Prior art keywords
input
terminals
chip
terminal
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57092737A
Other languages
Japanese (ja)
Other versions
JPS58209158A (en
Inventor
Soichi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57092737A priority Critical patent/JPS58209158A/en
Publication of JPS58209158A publication Critical patent/JPS58209158A/en
Publication of JPH0141032B2 publication Critical patent/JPH0141032B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】 本発明は集積回路装置に関し、特にマスタ・ス
ライス方式による論理集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and particularly to a logic integrated circuit using a master slice method.

個々の入・出力端子に対応して夫々入力回路、
出力回路を有するマスタ・スライス方式の論理集
積回路に於ては、それら入・出力回路を構成する
のに必要なトランジスタ、抵抗等の素子群は、通
常入・出力端子にほぼ対応がつくように半導体チ
ツプ上の端子位置近傍に配置されるが、上記回路
を必要としない電源端子には、それに対応する素
子群は配置されない。またケースコストを低くお
さえるために、各品種についてマスタ・スライス
基板で決まる最大許容数以下の種々の必要端子数
が生ずるのに対応して、ケース端子数は、できる
だけ必要端子数に近いものを適用するのが好まし
い。 Input circuits corresponding to individual input/output terminals,
In master-slice type logic integrated circuits that have output circuits, the transistors, resistors, and other elements necessary to configure the input/output circuits are usually arranged so that they almost correspond to the input/output terminals. A power supply terminal, which is arranged near a terminal position on a semiconductor chip but does not require the above-mentioned circuit, does not have a corresponding element group arranged thereon. In addition, in order to keep case costs low, the number of case terminals is set as close to the required number of terminals as possible, as each product requires a different number of terminals that is less than the maximum allowable number determined by the master slice board. It is preferable to do so.

従来のマスタ・スライスに於ては、その搭載可
能ゲート数がさほど大きくなく、それに応じて、
必要端子数も高々数十端子であつたのが、近年の
微細加工技術の進展と共に搭載ゲート数が増大
し、最大端子数は従来の２倍近くを必要とするに
致つている。この結果、１つのマスタ・スライス
基板から派生する種々品種の端子数の範囲は、50
端子未満のものから、100端子以上のものに及び
非常に多様なケースが１つのマスタ・スライス基
板に適用されることになるため、チツプ設計の上
でチツプ上の電源端子位置と、ケースの電源端子
位置との対応をつけるのが、非常に困難になつて
きた。 In conventional master slices, the number of gates that can be installed is not very large, and accordingly,
The required number of terminals used to be several tens at most, but with the recent advances in microfabrication technology, the number of gates to be mounted has increased, and the maximum number of terminals is now nearly twice as large as in the past. As a result, the range of the number of terminals of various products derived from one master slice board is 50.
A wide variety of cases, ranging from less than 100 terminals to more than 100 terminals, will be applied to one master slice board. It has become extremely difficult to establish correspondence with terminal positions.

本発明は、この様な実情に鑑み、多様なケース
上の電源端子位置にチツプ上の電源粒子位置を自
由に対応させられる半導体チツプを提供すること
を目的とし、入・出力端子近傍で、該入・出力端
子に対応して入・出力回路を構成するのに必要な
素子群を有するマスタ・スライス半導体チツプに
於て、電源端子にも、上記入・出力回路の構成に
必要な素子群を対応させて配置することを特徴と
する。 In view of these circumstances, the present invention aims to provide a semiconductor chip in which the positions of power particles on the chip can be freely made to correspond to the positions of power supply terminals on various cases. In a master slice semiconductor chip that has a group of elements necessary to configure the input/output circuit corresponding to the input/output terminal, the group of elements necessary to configure the input/output circuit are also included in the power supply terminal. They are characterized by being arranged in correspondence.

以下図を参照しながら本発明を説明する。第１
図は従来方法によるマスタ・スライスチツプの共
通パタンレイアウトを示すもので、１がチツプ外
殻、２〜８及び１７〜２３は入力端子、９〜１６
は入力にも出力にもできる端子、２４〜２９は電
源端子、３０は内部論理回路部で単にその全体を
枠で示す。又、３１〜４４は入力回路部、４５〜
５２は入力回路と出力回路を合わせた部分で、入
力回路部３１〜３４及び入力回路と出力回路を合
わせた部分４５〜５２のいずれもその全体を単に
枠で示す。又、右の一部は、左半面の折返し対称
と考えて良く、図が省略されている。 The present invention will be explained below with reference to the figures. 1st
The figure shows a common pattern layout of a master slice chip according to the conventional method, in which 1 is the chip outer shell, 2 to 8 and 17 to 23 are input terminals, and 9 to 16 are input terminals.
Numerals 24 to 29 are power supply terminals, and 30 is an internal logic circuit section, the entirety of which is simply indicated by a frame. Further, 31 to 44 are input circuit sections, and 45 to 44 are input circuit sections.
Reference numeral 52 denotes a portion that is a combination of an input circuit and an output circuit, and both of the input circuit sections 31 to 34 and the portions 45 to 52 that are a combination of an input circuit and an output circuit are simply shown as frames. Also, the right part can be considered to be a folded symmetry of the left half, and is omitted from the drawing.

さて、電源端子２４〜２９には、それに対応す
る入力回路或いは出力回路が配置されていない。
従つて同チツプを搭載する全てのケースの電源端
子は、第１図のチツプ電源端子２４〜２９の位置
と、うまく対応が付く必要があり、特に、許容最
大端子数を使用する品種では、ケースに応じて電
源端子位置を変更することは、入・出力回路部を
有しない、電源端子位置を入・出力端子として使
用しなければならなくなり、入・出力端子が不足
してしまうために不可能になる。 Now, the power supply terminals 24 to 29 are not provided with corresponding input circuits or output circuits.
Therefore, the power supply terminals of all cases equipped with the same chip must correspond well to the positions of chip power supply terminals 24 to 29 in Figure 1.Especially, for products that use the maximum allowable number of terminals, the case It is impossible to change the power terminal position according to the input/output circuit because the power terminal position, which does not have an input/output circuit section, must be used as an input/output terminal, and there will be a shortage of input/output terminals. become.

第２図は、本発明を説明するためのチツプレイ
アウト図で、５３がチツプ外殻、５４〜８１がチ
ツプ端子、８２は、内部論理回路部、８３〜１０
０は入力回路部、１０１〜１１０は入力回路と出
力回路とを合わせた部分である。第２図も第１図
と同様、、右の一部は左半面と折返し対称と考え
て良く図が省略されている。 FIG. 2 is a chip layout diagram for explaining the present invention, in which 53 is a chip outer shell, 54 to 81 are chip terminals, 82 is an internal logic circuit section, and 83 to 10
0 is an input circuit section, and 101 to 110 are a combination of an input circuit and an output circuit. Similarly to FIG. 1, in FIG. 2, the right part is omitted because it can be considered to be folded and symmetrical with the left half.

さて、第２図に於ては、チツプ端子の全てに入
力回路部、又は出力回路部が対応しているので、
第１図で説明したような、許容最大端子数使用時
の電源端子位置変更を伴う、入・出力端子不足は
生じない。ところで第２図に於て電源端子化され
た端子部分での端子からチツプ内部への電源配線
は、例えば、第３図のようになる。第３図に於て
１１１は、チツプ外殻の一部１１２，１１５は
夫々第２図の端子７８及び８１に対応し、入力端
子に割り当てられたもの、１１３，１１４は、
夫々第２図の端子７９及び８０に対応し、１１３
はVCC、１１４はGNDの夫々の電源端子に割り
当てられている。１１６〜１１９は、第２図９７
〜１００に対応する入力回路用の素子群、１２０
は、端子１１４と同電位の第２層配線１２１は端
子１１３と同電位の第２層配線で開孔１２３〜１
２６を経由して、第１層配線１２２に到り、さら
に開孔１２７〜１３２を経由して、結果として端
子１１３と同電位になる第２層配線１３５に到
る。１３３，１３４は、第１層配線１２２の内部
がくりぬかれていることを示す。さて、第３図に
於て、入力回路用の素子群１１７，１１８では、
入力回路用の配線接続は行なわれず、同位置で
は、VCC１３５、GND１２０の電源配線が通過
するだけである。尚、ここに於て、第１層配線１
２２のくりぬき部１３３及び１３４は、共通マス
タ基板上のコンタクト用開孔部のうち、無視し得
ないインピーダンスを経てチツプGND電位に導
通しているものと、VCC電位である第１層配線
１２２との接続をさけるために設けられたもので
ある。 Now, in Figure 2, all of the chip terminals correspond to input circuit sections or output circuit sections, so
As explained in FIG. 1, there is no shortage of input/output terminals due to a change in the position of the power supply terminals when the maximum allowable number of terminals is used. By the way, the power supply wiring from the terminal part converted into a power supply terminal to the inside of the chip in FIG. 2 is as shown in FIG. 3, for example. In FIG. 3, part 111 of the chip shell 112 and 115 correspond to the terminals 78 and 81 in FIG. 2, respectively, and are assigned to input terminals, and 113 and 114 are
113, corresponding to terminals 79 and 80 in FIG.
is assigned to the VCC power supply terminal, and 114 is assigned to the GND power supply terminal. 116 to 119 are shown in Fig. 2 97
- Element group for input circuit corresponding to 100, 120
The second layer wiring 121 having the same potential as the terminal 114 is the second layer wiring having the same potential as the terminal 113, and the openings 123 to 1
26, it reaches the first layer wiring 122, further passes through the openings 127 to 132, and finally reaches the second layer wiring 135, which has the same potential as the terminal 113. 133 and 134 indicate that the inside of the first layer wiring 122 is hollowed out. Now, in FIG. 3, in the input circuit element groups 117 and 118,
Wiring connections for the input circuit are not made, and only the power supply wiring for VCC 135 and GND 120 passes through the same position. In addition, here, the first layer wiring 1
The hollowed out parts 133 and 134 of 22 are connected to the contact openings on the common master board that are connected to the chip GND potential through a non-negligible impedance, and to the first layer wiring 122 which is at the VCC potential. This was provided to avoid the connection of

以上に記した如く、本発明によれば、チツプ上
端子の任意位置で電源端子化が可能になるため、
種々のケースの電源端子位置との対応が自由に付
けられる。この結果、例えば、チツプ端子と、ケ
ース端子とを接続する際のボンデイング作業に最
適なチツプ端子をケースに合わせて決めることが
可能になり、また例えばケースのインダクタンス
によるノイズ防止のため、インダクタンスを低減
するべく、品種個別に電源端子数をケース、チツ
プ伴々、増設することも自由にできる。 As described above, according to the present invention, it is possible to convert the terminals on the chip into power supply terminals at any position.
Correspondence with the power terminal position of various cases can be freely established. As a result, for example, it is possible to determine the optimal chip terminal according to the case for bonding work when connecting a chip terminal and a case terminal, and it is also possible to reduce inductance, for example, to prevent noise caused by case inductance. In order to achieve this, the number of power supply terminals can be freely increased depending on the case and chip for each product type.

尚、以上では、チツプ上の全端子に入・出力回
路部が対応する例を示したが一部であつても本発
明の効果が損われないことは明白である。 In the above, an example has been shown in which the input/output circuit sections correspond to all the terminals on the chip, but it is clear that the effects of the present invention will not be impaired even if the input/output circuit sections correspond to all the terminals on the chip.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のマスタ・スライスチツプの素子
群配置のようすを示す平面図、第２図は本発明の
マスタ・スライスチツプ素子群配置のようすを示
す平面図、第３図は第２図に示すチツプ端子の一
部を電源端子化した時のようすを示す平面図、で
ある。 なお図において、１……チツプ外殻、２〜２９
……チツプ端子、３０……内部回路部、３１〜５
２……入出力回路部、５３……チツプ外殻、５４
〜８１……チツプ端子、８２……内部回路部、８
３〜１１０……入出力回路部、１１１……チツプ
外殻の一部、１１２，１１５……信号用端子、１
１６〜１１９……入力回路用素子群、１１３，１
１４……電源用端子、１２０，１２１，１３５…
…第２層配線、１２３〜１２６，１２７〜１３２
……第１層配線と第２層配線を接続するための開
孔、１２２……第１層配線、１３３，１３４……
第１層配線１２２の内部のくりぬき部分、を示
す。 FIG. 1 is a plan view showing the arrangement of the elements of a conventional master slice chip, FIG. 2 is a plan view showing the arrangement of the elements of the master slice chip of the present invention, and FIG. FIG. 3 is a plan view showing a state in which a part of the chip terminal shown in FIG. In the figure, 1... Chip outer shell, 2 to 29
...Chip terminal, 30...Internal circuit section, 31-5
2... Input/output circuit section, 53... Chip outer shell, 54
~81... Chip terminal, 82... Internal circuit section, 8
3-110...Input/output circuit section, 111...Part of chip outer shell, 112, 115...Signal terminal, 1
16-119...Input circuit element group, 113,1
14... Power supply terminal, 120, 121, 135...
...Second layer wiring, 123-126, 127-132
...Opening hole for connecting the first layer wiring and the second layer wiring, 122...First layer wiring, 133, 134...
A hollowed out portion inside the first layer wiring 122 is shown.

Claims (1)

【特許請求の範囲】[Claims] １ 入・出力端子近傍に、該入・出力端子に対応
する入・出力回路を構成するのに必要な素子群を
有するマスタ・スライス半導体チツプに於て、電
源端子にも上記入・出力回路の構成に必要な素子
群を対応させて配置することを特徴とするマスタ
スライス半導体装置。1. In a master slice semiconductor chip that has a group of elements necessary to configure the input/output circuit corresponding to the input/output terminal near the input/output terminal, the power supply terminal also has the elements of the input/output circuit corresponding to the input/output terminal. A master slice semiconductor device characterized in that element groups necessary for the configuration are arranged in correspondence.
JP57092737A 1982-05-31 1982-05-31 Master-slice semiconductor device Granted JPS58209158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57092737A JPS58209158A (en) 1982-05-31 1982-05-31 Master-slice semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57092737A JPS58209158A (en) 1982-05-31 1982-05-31 Master-slice semiconductor device

Publications (2)

Publication Number Publication Date
JPS58209158A JPS58209158A (en) 1983-12-06
JPH0141032B2 true JPH0141032B2 (en) 1989-09-01

Family

ID=14062725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57092737A Granted JPS58209158A (en) 1982-05-31 1982-05-31 Master-slice semiconductor device

Country Status (1)

Country Link
JP (1) JPS58209158A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5941852A (en) * 1982-06-24 1984-03-08 ストレイジ・テクノロジ−・パ−トナ−ズ Integrated circuit chip
JPS59139646A (en) * 1983-01-31 1984-08-10 Hitachi Micro Comput Eng Ltd Semiconductor integrated circuit device
JPS59159557A (en) * 1983-03-01 1984-09-10 Hitachi Ltd Semiconductor integrated circuit device
JPS61204957A (en) * 1985-03-08 1986-09-11 Hitachi Ltd Large scale integrated circuit device
JPS61263241A (en) * 1985-05-17 1986-11-21 Matsushita Electronics Corp Gate array
JPH05308136A (en) * 1992-04-01 1993-11-19 Nec Corp Master slice integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5493375A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Semiconductor integrated circuit device
JPS5561054A (en) * 1978-10-30 1980-05-08 Mitsubishi Electric Corp Large scale integrated circuit
JPS58197746A (en) * 1982-05-14 1983-11-17 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5493375A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Semiconductor integrated circuit device
JPS5561054A (en) * 1978-10-30 1980-05-08 Mitsubishi Electric Corp Large scale integrated circuit
JPS58197746A (en) * 1982-05-14 1983-11-17 Hitachi Ltd Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPS58209158A (en) 1983-12-06

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