JPS58173958U - Malfunction alert public telephone - Google Patents
Malfunction alert public telephoneInfo
- Publication number
- JPS58173958U JPS58173958U JP5170183U JP5170183U JPS58173958U JP S58173958 U JPS58173958 U JP S58173958U JP 5170183 U JP5170183 U JP 5170183U JP 5170183 U JP5170183 U JP 5170183U JP S58173958 U JPS58173958 U JP S58173958U
- Authority
- JP
- Japan
- Prior art keywords
- coin
- failure
- detection
- program
- detectors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Prepayment Telephone Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の実施例を示し、第１図は硬貨収納部の構成
を示す概念図、第２図は公衆電話機の全構成を示すブロ
ック図、第３図は制御回路の構成ならびに信号の入出力
状況を示すブロック図、第４図は制御回路による故障検
知実行ステップのフ−ローチャート、第５図は硬貨処理
回路の構成ならびに信号の入出力状況を示すブロック図
、第６図は硬貨処理回路による故障検知実行ステップの
フローチャート、第７図乃至第１３図は他の実施例を示
ス故障検知実行ステップのフローチャートである。
ＭＣＣ・・・・・・制御回路、ＣＣＣ・・・・・・硬貨
処理回路、ＣＰＵ１． ＣＰＵ２・・・・・・プロセッ
サ、ＲＯＭ□、ＲＯＭ２°°。
・・・メモリ（記憶装置） 、ＲＡＭ□、 ＲＡＭ２・
・・・・・補助メモリ（補助記憶装置）、■ｌＯ１・・
・・・・入出力回路（オフフック検出手段）、ＣＯ・・
・・・・材質判別器、ＤＡ、、 ＤＡ２． ＣＣ１〜Ｃ
Ｃ３，ＣＣ１〜ＣＣ３，ＣＣ１〜ＣＣ３゜ＭＲ・・・・
・・硬貨検出器、ＣＵＴ・・・・・・蓄積カウンタ、Ｃ
Ｂ・・・・・・金庫装着スロイッチ、ＴＣＣ・・・・・
・通話制御回路、ｃｐ・・・・・・課金信号受信回路、
Ｈ・・・・・・フックスイッチ、ＤＩＳｌ、 ＤＩＳ２
・・・・・・表示部（報知回路）、ＷＴ・・・・・・警
告音送出回路（報知回路）。The figures show an embodiment of the present invention. Fig. 1 is a conceptual diagram showing the structure of the coin storage section, Fig. 2 is a block diagram showing the entire structure of the public telephone, and Fig. 3 shows the structure of the control circuit and signal input. A block diagram showing the output status, Fig. 4 is a flowchart of the failure detection execution step by the control circuit, Fig. 5 is a block diagram showing the configuration of the coin processing circuit and signal input/output status, and Fig. 6 is a coin processing Flowchart of the step of executing failure detection by circuit. FIGS. 7 to 13 are flowcharts of the step of executing failure detection using other embodiments. MCC...Control circuit, CCC...Coin processing circuit, CPU1. CPU2... Processor, ROM□, ROM2°°. ...Memory (storage device), RAM□, RAM2・
...Auxiliary memory (auxiliary storage device), ■lO1...
...Input/output circuit (off-hook detection means), CO...
...Material discriminator, DA,, DA2. CC1~C
C3, CC1~CC3, CC1~CC3°MR...
・・Coin detector, CUT・・Accumulation counter, C
B...Safe installed slot switch, TCC...
・Call control circuit, cp...charging signal receiving circuit,
H...Hook switch, DIS1, DIS2
...Display section (notification circuit), WT... Warning sound sending circuit (notification circuit).
Claims (1)
器を配置し、該各硬貨検出器の各検出々力に応じて硬貨
選別および蓄積プログラムならびに硬貨収納プログラム
を実行し通話制御を行なう公衆電話機において、オフフ
ックを検出するオフフック検出手段と、前記各硬貨検出
器の各検出々力を順次にチェックする故障検知プログラ
ムを格納した記憶装置と、前記オフフック検出手段の出
力に応じ前記故障検知プログラムに基づいて前記各硬貨
検出器の各検出々力を瞬時の間にチェックして各々の論
理値が初期状態であるとき、゛故障なビと判断し前記通
話制御を行ないかつ前記論理値が初期状態でないときに
は“故障あり″と判断するプロセッサと、該プロセッサ
が“故障あり゛と判断したとき利用者に対して故障の報
知を行なう報知回路とを備えたことを特徴とする故障報
知式公衆電話機。A public service system in which a plurality of coin detectors are arranged in a coin path between a coin input slot and a storage safe, and a coin sorting and accumulation program and a coin storage program are executed according to the detection power of each coin detector to control telephone calls. In the telephone, an off-hook detection means for detecting off-hook, a storage device storing a failure detection program for sequentially checking each detection force of each of the coin detectors, and a storage device storing a failure detection program for sequentially checking each detection force of each of the coin detectors; Based on this, the detection power of each coin detector is instantaneously checked, and if each logical value is in the initial state, it is determined that there is a failure, the call control is performed, and the logical value is in the initial state. 1. A failure notification type public telephone set, comprising: a processor that determines that there is a failure when the failure occurs; and a notification circuit that notifies a user of the failure when the processor determines that there is a failure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5170183U JPS58173958U (en) | 1983-04-07 | 1983-04-07 | Malfunction alert public telephone |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5170183U JPS58173958U (en) | 1983-04-07 | 1983-04-07 | Malfunction alert public telephone |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58173958U true JPS58173958U (en) | 1983-11-21 |
| JPS6115645Y2 JPS6115645Y2 (en) | 1986-05-15 |
Family
ID=30062410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5170183U Granted JPS58173958U (en) | 1983-04-07 | 1983-04-07 | Malfunction alert public telephone |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58173958U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5192106A (en) * | 1975-02-12 | 1976-08-12 | ||
| JPS52127003A (en) * | 1976-04-19 | 1977-10-25 | Hitachi Ltd | Communication control device for switching lines |
-
1983
- 1983-04-07 JP JP5170183U patent/JPS58173958U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5192106A (en) * | 1975-02-12 | 1976-08-12 | ||
| JPS52127003A (en) * | 1976-04-19 | 1977-10-25 | Hitachi Ltd | Communication control device for switching lines |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6115645Y2 (en) | 1986-05-15 |
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