JPS58101360A - Data processor - Google Patents
Data processorInfo
- Publication number
- JPS58101360A JPS58101360A JP20015881A JP20015881A JPS58101360A JP S58101360 A JPS58101360 A JP S58101360A JP 20015881 A JP20015881 A JP 20015881A JP 20015881 A JP20015881 A JP 20015881A JP S58101360 A JPS58101360 A JP S58101360A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- central processing
- cpus
- interrupt
- processing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、複数の中央処理装置で構成されるデータ処理
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device comprised of a plurality of central processing units.
従来相手中央処理装置との通信を行な5時には、相手中
央処理装置の記憶装置の特定番地に通信内容をあらかじ
め格納しておき、相手中央処理装置の割込レジスタの所
定のビットへ命令により@1”を書き込む。一方、鋏割
込レジスタの所定のビットへ”1″を書き区まれた中央
処理装置では割込レジスタの所定のビットが11″であ
ることを知って前記の特定番地の内容を読み出すことに
より通信内容を知る。Conventionally, at 5 o'clock when communicating with a partner central processing unit, the content of the communication is stored in advance at a specific address in the storage device of the partner central processing unit, and is sent to a predetermined bit of the interrupt register of the partner central processing unit by a command. 1" is written to the specified bit of the scissors interrupt register. On the other hand, the central processing unit that has written "1" to the predetermined bit of the scissors interrupt register knows that the predetermined bit of the interrupt register is 11" and writes the contents of the specific address. The content of the communication can be known by reading the .
ところが、複数の中央処理装置で構成されたデータ処理
装置では、1台の中央処理装置から他の複数の中央処理
装置への同一内容の通信を行なう際に他の複数の中央処
理装置数に勢しい回数だけ諌命令を実行しなければなら
ない欠点がある。しかも他の複数の中央処理装置の内で
最初の通信と最後の通信間に時差が生じ、この時差を吸
収するために繁雑なプログラムを組む欠点もある。However, in a data processing device composed of multiple central processing units, when one central processing unit communicates the same content to multiple other central processing units, the number of other central processing units is exceeded. The drawback is that the reprimand command must be executed the correct number of times. Moreover, there is a time difference between the first communication and the last communication among the other plurality of central processing units, and there is also the disadvantage that a complicated program is required to absorb this time difference.
本発明の目的は、他の複数の中央処理装置への通信に幽
りプログラムを簡略化する通信手段を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a communication means that simplifies a program for communicating with a plurality of other central processing units.
本発明では、1命令で1台の中央処理装置から他の複数
の中央処理装置への同時割込を行な5手段を設け、前述
の目的を達成するものである。The present invention achieves the above-mentioned object by providing five means for simultaneously interrupting a plurality of other central processing units from one central processing unit with one instruction.
以下図面により実施例を説明する。図は本発明のデータ
処理装置を示したものである。11〜1nは中央処理装
置、21〜2nは他中央処理装置への割込起動回路、
51〜釦は割込起動信号線、41−nは自装置に対する
割込起動禁止信号線、 81〜iはゲート、41〜釦は
割込レジスタ、71〜7nは他装置からの割込起動を識
別するための割込レジスタの特定ビット、81〜軸は割
込レジスタの特定ビット71〜7n IIC’″1′″
が設定されたことにより起動される割込処理部である。Examples will be described below with reference to the drawings. The figure shows a data processing device of the present invention. 11 to 1n are central processing units, 21 to 2n are interrupt activation circuits for other central processing units,
51-buttons are interrupt activation signal lines, 41-n are interrupt activation prohibition signal lines for the own device, 81-i are gates, 41-buttons are interrupt registers, and 71-7n are interrupt activation signal lines for the own device. Specific bits of the interrupt register for identification, 81 to axis are specific bits of the interrupt register 71 to 7n IIC'''1'''
This is an interrupt processing unit that is activated when .
ここで、−例として中央処理装置11かう他の中央処理
装置12.4flK同時割込をかける場合の動作を説明
する。Here, as an example, the operation in the case where the central processing unit 11 and other central processing units 12, 4flK are simultaneously interrupted will be described.
まず中央処理装置11で割込起動回路21を起動する命
令を実行する。この結果割込起動回路21が起動され、
割込起動信号線s1の信号は割込起動禁止信号線41の
信号によりゲート51で自装置の割込レジスタ61への
”1”の設定は禁示されるとともに他の中央処理装置1
ト1nへはゲート52−5−6nを介して割込レジスタ
6 Nnの特定ビット7 ドアIIへ@1”を設定する
。他の中央処理装置12〜1nの割込処理部■1aは割
込レジスタ4 )−60の特定ビット7トー7W&へ′
″1′が設定されたことにより割込処理を実行する。First, the central processing unit 11 executes an instruction to activate the interrupt activation circuit 21. As a result, the interrupt activation circuit 21 is activated,
The signal on the interrupt activation signal line s1 is prohibited from being set to "1" in the interrupt register 61 of the own device at the gate 51 by the signal on the interrupt activation prohibition signal line 41, and is also prohibited from being set to "1" in the interrupt register 61 of the own device.
The specific bit 7 of the interrupt register 6Nn is set to ``@1'' to the door II via the gate 52-5-6n.The interrupt processing unit 1a of the other central processing units 12 to 1n register 4)-60 specific bit 7 to 7W&'
Since "1" is set, interrupt processing is executed.
このようにして中央処理装置11から他の中央処理装置
1 )−I nへの同時割込が実行される。同時割込後
の各中央処理装置の動作は従来技術と同じである。また
中央処理装置11.1ト1nへの同時割込も同様に説明
できる。In this way, simultaneous interrupts from the central processing unit 11 to the other central processing units 1 )-I n are executed. The operation of each central processing unit after the simultaneous interrupt is the same as in the prior art. Simultaneous interrupts to the central processing unit 11.1 and 1n can also be explained in the same way.
以上述べたように本発明を実施することにより、1命令
で1台の中央処理装置から他の複数の中央処理装置への
同時割込が可能となり、プログラムが簡略化できる効果
を有するものである。As described above, by implementing the present invention, it is possible to interrupt simultaneously from one central processing unit to multiple other central processing units with a single instruction, which has the effect of simplifying the program. .
図は本発明によるデータ処理装置の一実施例のプルツク
図である。
11〜1n−・中央処理装置
21〜1m・・・割込起動回路
51〜釦−割込起動信号線
4l−4n ・・・割込起動禁止信号線51〜釦−・・
グー) 41S411−割込レジスタフ1〜7n
・・・特定ビット 8l−8n ・・・割込処理部代
理人弁理+ 麿 1)飼 −The figure is a pull diagram of an embodiment of a data processing device according to the present invention. 11 to 1n-・Central processing unit 21 to 1m...Interrupt activation circuit 51 to button--Interrupt activation signal line 4l-4n...Interrupt activation prohibition signal line 51 to button--
41S411-Interrupt register 1~7n
...Specific bits 8l-8n ...Interrupt processing department attorney + Maro 1) Kai -
Claims (1)
て、命令により1台の中央処理装置から、他の中央処理
装置への割込を同時に行なう手段を有することを特徴と
するデータ処理装置。1. A data processing device comprising a plurality of central processing units, characterized in that the data processing device includes means for simultaneously interrupting one central processing unit to another central processing unit based on a command.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20015881A JPS58101360A (en) | 1981-12-14 | 1981-12-14 | Data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20015881A JPS58101360A (en) | 1981-12-14 | 1981-12-14 | Data processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58101360A true JPS58101360A (en) | 1983-06-16 |
JPS6326421B2 JPS6326421B2 (en) | 1988-05-30 |
Family
ID=16419748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20015881A Granted JPS58101360A (en) | 1981-12-14 | 1981-12-14 | Data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58101360A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58121468A (en) * | 1982-01-13 | 1983-07-19 | Matsushita Electric Ind Co Ltd | Multiprocessor device |
JPS6081648A (en) * | 1983-10-11 | 1985-05-09 | Nippon Telegr & Teleph Corp <Ntt> | Information processor |
JPH0318958A (en) * | 1989-06-15 | 1991-01-28 | Nec Corp | Multiprocessor system |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02100867U (en) * | 1989-01-31 | 1990-08-10 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55153021A (en) * | 1979-05-16 | 1980-11-28 | Hitachi Ltd | Data transfer system of multiprocessor system |
JPS57152066A (en) * | 1981-03-16 | 1982-09-20 | Tokyo Electric Co Ltd | Opu communication system in multi-opu system |
-
1981
- 1981-12-14 JP JP20015881A patent/JPS58101360A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55153021A (en) * | 1979-05-16 | 1980-11-28 | Hitachi Ltd | Data transfer system of multiprocessor system |
JPS57152066A (en) * | 1981-03-16 | 1982-09-20 | Tokyo Electric Co Ltd | Opu communication system in multi-opu system |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58121468A (en) * | 1982-01-13 | 1983-07-19 | Matsushita Electric Ind Co Ltd | Multiprocessor device |
JPS6081648A (en) * | 1983-10-11 | 1985-05-09 | Nippon Telegr & Teleph Corp <Ntt> | Information processor |
JPH0318958A (en) * | 1989-06-15 | 1991-01-28 | Nec Corp | Multiprocessor system |
Also Published As
Publication number | Publication date |
---|---|
JPS6326421B2 (en) | 1988-05-30 |
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