JPS5792413A - Demodulation system for phase-modulated signal - Google Patents
Demodulation system for phase-modulated signalInfo
- Publication number
- JPS5792413A JPS5792413A JP16578780A JP16578780A JPS5792413A JP S5792413 A JPS5792413 A JP S5792413A JP 16578780 A JP16578780 A JP 16578780A JP 16578780 A JP16578780 A JP 16578780A JP S5792413 A JPS5792413 A JP S5792413A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- waveform
- circuit
- fall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Digital Magnetic Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To demodulate a PE signal into an NRZ signal by a simple circuit by outputting a waveform which falls with a prescribed time constant by detecting the change point of the waveform of a readout signal, and inverting the state of the output waveform corresponding to the fall of the output waveform. CONSTITUTION:An analog PE signal inputted to an input terminal 1 is converted into a digital PE signal (a) through an AD converting circuit 2, and the signal is inputted to rise and fall differentiating circuits 3 and 4, which output rising and falling clock pulses (b) and (e) respectively. Consequently, the trigger clock (d) of a waveform shaping circuit 7 appears at the output of an OR gate 6. The waveform shaping circuit 7 is triggered by a trigger clock (d) to output logic[1]and, when the trigger clock (d) is not received during the period a prescribed time constant, inverts the output to logic[0]. For this purpose, the output waveform (e) of the circuit 7 is passed through the 2nd fall differentiating circuit 8, etc., to obtain demodulated data (f). The data (f) is in NRZ form. Thus, the PE signal is converted into the NRZ signal by the simple circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16578780A JPS5792413A (en) | 1980-11-27 | 1980-11-27 | Demodulation system for phase-modulated signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16578780A JPS5792413A (en) | 1980-11-27 | 1980-11-27 | Demodulation system for phase-modulated signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5792413A true JPS5792413A (en) | 1982-06-09 |
| JPS6349286B2 JPS6349286B2 (en) | 1988-10-04 |
Family
ID=15818991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16578780A Granted JPS5792413A (en) | 1980-11-27 | 1980-11-27 | Demodulation system for phase-modulated signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5792413A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61156922A (en) * | 1984-12-21 | 1986-07-16 | アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド | Replication of clock signal from manchester's coded signal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5091311A (en) * | 1973-12-12 | 1975-07-22 | ||
| JPS5388114U (en) * | 1976-11-30 | 1978-07-19 | ||
| JPS54150110A (en) * | 1978-05-17 | 1979-11-26 | Fujitsu Ltd | Data demodulating system |
-
1980
- 1980-11-27 JP JP16578780A patent/JPS5792413A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5091311A (en) * | 1973-12-12 | 1975-07-22 | ||
| JPS5388114U (en) * | 1976-11-30 | 1978-07-19 | ||
| JPS54150110A (en) * | 1978-05-17 | 1979-11-26 | Fujitsu Ltd | Data demodulating system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61156922A (en) * | 1984-12-21 | 1986-07-16 | アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド | Replication of clock signal from manchester's coded signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6349286B2 (en) | 1988-10-04 |
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