JPS57157621A - Digital error generating circuit - Google Patents
Digital error generating circuitInfo
- Publication number
- JPS57157621A JPS57157621A JP56042971A JP4297181A JPS57157621A JP S57157621 A JPS57157621 A JP S57157621A JP 56042971 A JP56042971 A JP 56042971A JP 4297181 A JP4297181 A JP 4297181A JP S57157621 A JPS57157621 A JP S57157621A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- digital data
- error
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
PURPOSE:To simply produce a random error without carrying out a D/A conversion, by causing an error at a random bit position of a series of digital data signals which are successively transferred. CONSTITUTION:It is supposed that four FF outputs forming an artificial random code generating circuit 1 are set at ''1001'' and a 16-notation counter 2 is set at ''0000'' respectively. As a comparator 3 produces no coincidence signal 8, a digital data signal input 4 is converted directly into a signal output 5. When the counter 2 reaches ''100'', the comparator 3 delivers the signal 8. As a result, the signal polarity is inverted by an OR circuit 7 for the input 4 to be converted into the output 5. In other words, an error is included into the digital data signal. At the time, the signal 8 is converted into a clock input of the circuit 1 and the FF output of the circuit 1 proceeds to the next state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56042971A JPS57157621A (en) | 1981-03-24 | 1981-03-24 | Digital error generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56042971A JPS57157621A (en) | 1981-03-24 | 1981-03-24 | Digital error generating circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57157621A true JPS57157621A (en) | 1982-09-29 |
JPS639685B2 JPS639685B2 (en) | 1988-03-01 |
Family
ID=12650917
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56042971A Granted JPS57157621A (en) | 1981-03-24 | 1981-03-24 | Digital error generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57157621A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63171036A (en) * | 1987-01-08 | 1988-07-14 | Fujitsu Ltd | Error inserting circuit |
JPH0371740A (en) * | 1989-08-11 | 1991-03-27 | Nec Corp | Code error addition circuit |
-
1981
- 1981-03-24 JP JP56042971A patent/JPS57157621A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63171036A (en) * | 1987-01-08 | 1988-07-14 | Fujitsu Ltd | Error inserting circuit |
JPH0371740A (en) * | 1989-08-11 | 1991-03-27 | Nec Corp | Code error addition circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS639685B2 (en) | 1988-03-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS57157621A (en) | Digital error generating circuit | |
JPS5591233A (en) | Successive comparison type a/d converter | |
JPS53121556A (en) | 2-phase clock pulse generator circuit | |
JPS5299044A (en) | Analogue memory circuit | |
JPS6419821A (en) | Reset synchronization delay circuit | |
JPS5384668A (en) | Parallel-processing-type signal conversion circuit | |
EP0119716A3 (en) | Coder-decoder and control thereof | |
JPS5414145A (en) | Polygonal line decoder of digital type | |
JPS531451A (en) | D-a converter | |
JPS53139968A (en) | A-d convertor | |
JPS547846A (en) | Discrimination system for digital amplitude, polarity and code | |
JPS5338929A (en) | Intermittent signal output method and device | |
JPS5742227A (en) | Signal converter | |
JPS5410608A (en) | Semi-ternary code word synchronous circiut | |
JPS53113466A (en) | Polygonal line decoder of digital type | |
JPS5286758A (en) | High accurate digital delay circuit | |
JPS5538684A (en) | Shift register | |
JPS6411421A (en) | Code converting circuit | |
JPS6410708A (en) | Offset canceling circuit | |
JPS51112255A (en) | Signal generator | |
JPS53101966A (en) | Ad converter | |
JPS5376000A (en) | Writing circuit | |
JPS5216144A (en) | Digital synchronous clock generator | |
JPS53128244A (en) | Time axis converting device | |
JPS52115107A (en) | Conversion system of binary signal |