JPS5753169A - Bit discriminating circuit - Google Patents

Bit discriminating circuit

Info

Publication number
JPS5753169A
JPS5753169A JP12980680A JP12980680A JPS5753169A JP S5753169 A JPS5753169 A JP S5753169A JP 12980680 A JP12980680 A JP 12980680A JP 12980680 A JP12980680 A JP 12980680A JP S5753169 A JPS5753169 A JP S5753169A
Authority
JP
Japan
Prior art keywords
bit
circuit
shift register
read
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12980680A
Other languages
Japanese (ja)
Inventor
Takao Yoshihara
Shunji Suzawa
Masayoshi Kawaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12980680A priority Critical patent/JPS5753169A/en
Publication of JPS5753169A publication Critical patent/JPS5753169A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/068—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by sampling faster than the nominal bit rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To obtain a bit discriminating circuit where noise is not mixed, by sampling one bit at plural points and by discriminating sampled logical signals by majority logic. CONSTITUTION:A bit serial signal is connected to an input circuit 2, and one output is inputted to an input terminal D of the first shift register 12, and the other output is inputted to a sampling circuit 10. The sampling circuit 10 generates plural sampling pulses within the time of one bit, and these sampling pulses are connected to a read terminal T of the first shift register to read the signal from the input circuit 2 into the first shift register. When one-bit components are read, they are read out in parallel from the first shift register to a majority circuit 13 and are subjected to majority discrimination. The majority discimination output is read into the second shift register by the timing signal of the bit period obtained by dividing the output of the sampling circuit 10 by a frequency divider 11.
JP12980680A 1980-09-17 1980-09-17 Bit discriminating circuit Pending JPS5753169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12980680A JPS5753169A (en) 1980-09-17 1980-09-17 Bit discriminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12980680A JPS5753169A (en) 1980-09-17 1980-09-17 Bit discriminating circuit

Publications (1)

Publication Number Publication Date
JPS5753169A true JPS5753169A (en) 1982-03-30

Family

ID=15018676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12980680A Pending JPS5753169A (en) 1980-09-17 1980-09-17 Bit discriminating circuit

Country Status (1)

Country Link
JP (1) JPS5753169A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0310330A2 (en) * 1987-09-29 1989-04-05 Matsushita Electric Industrial Co., Ltd. Digital signal recording/reproducing apparatus
JPH01197526A (en) * 1988-02-02 1989-08-09 Teijin Ltd Preparation of ultrahigh molecular weight polyamide molded artille
JPH0362826A (en) * 1989-07-31 1991-03-18 Teijin Ltd Production of polyamide form
JPH0424210A (en) * 1990-05-14 1992-01-28 Teijin Seiki Co Ltd Traverse device
US7885290B2 (en) 2006-09-21 2011-02-08 Fujitsu Limited Communication terminal apparatus and signal receiving method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0310330A2 (en) * 1987-09-29 1989-04-05 Matsushita Electric Industrial Co., Ltd. Digital signal recording/reproducing apparatus
JPH01197526A (en) * 1988-02-02 1989-08-09 Teijin Ltd Preparation of ultrahigh molecular weight polyamide molded artille
JPH0362826A (en) * 1989-07-31 1991-03-18 Teijin Ltd Production of polyamide form
JPH0424210A (en) * 1990-05-14 1992-01-28 Teijin Seiki Co Ltd Traverse device
US7885290B2 (en) 2006-09-21 2011-02-08 Fujitsu Limited Communication terminal apparatus and signal receiving method

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