JPS57190333A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57190333A
JPS57190333A JP7588681A JP7588681A JPS57190333A JP S57190333 A JPS57190333 A JP S57190333A JP 7588681 A JP7588681 A JP 7588681A JP 7588681 A JP7588681 A JP 7588681A JP S57190333 A JPS57190333 A JP S57190333A
Authority
JP
Japan
Prior art keywords
layer
pad
insulation film
substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7588681A
Other languages
Japanese (ja)
Inventor
Tetsuo Akisawa
Masaru Katagiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7588681A priority Critical patent/JPS57190333A/en
Publication of JPS57190333A publication Critical patent/JPS57190333A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve protecting function against excess input and improve rate of integration by a method wherein a pad layer is formed above an impurity region of an Si substrate via an insulation layer and the pad layer and the impurity region are electrically connected. CONSTITUTION:An N-layer 11 is formed on a P-type Si substrate 10 and covered by an insulation film 12. A connection hole 13 which reaches the N-layer 11 is drilled in the insulation film 12. A pad layer 14 is formed on the insulation film 12 including the hole 13 above the N-layer 11 and is connected to the N- layer 11. An occupied region of the pad layer 14 is included in the occupied region of the N-layer 11. With this constitution, a drawing-out part of the pad is not needed, large protecting resistance can be obtained by making the N- layer 11 large and circuit elements in the substrate can be protected against excess input. And as the pad 14 is formed above the N-layer 11, the rate of integration can be improved by reducing the occupied region.
JP7588681A 1981-05-20 1981-05-20 Semiconductor device Pending JPS57190333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7588681A JPS57190333A (en) 1981-05-20 1981-05-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7588681A JPS57190333A (en) 1981-05-20 1981-05-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57190333A true JPS57190333A (en) 1982-11-22

Family

ID=13589219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7588681A Pending JPS57190333A (en) 1981-05-20 1981-05-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57190333A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150678A (en) * 1984-01-18 1985-08-08 Mitsubishi Electric Corp Protective circuit for input to semiconductor device
JPS61198765A (en) * 1985-02-28 1986-09-03 Nippon Denso Co Ltd Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146069A (en) * 1974-10-18 1976-04-20 Hitachi Ltd HANDOTA ISOCHI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146069A (en) * 1974-10-18 1976-04-20 Hitachi Ltd HANDOTA ISOCHI

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150678A (en) * 1984-01-18 1985-08-08 Mitsubishi Electric Corp Protective circuit for input to semiconductor device
JPS61198765A (en) * 1985-02-28 1986-09-03 Nippon Denso Co Ltd Semiconductor device

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