JPS54137952A - Delay pulse generating circuit - Google Patents

Delay pulse generating circuit

Info

Publication number
JPS54137952A
JPS54137952A JP4630578A JP4630578A JPS54137952A JP S54137952 A JPS54137952 A JP S54137952A JP 4630578 A JP4630578 A JP 4630578A JP 4630578 A JP4630578 A JP 4630578A JP S54137952 A JPS54137952 A JP S54137952A
Authority
JP
Japan
Prior art keywords
gate
circuit
threshold level
inputs
inverted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4630578A
Other languages
Japanese (ja)
Inventor
Yoshio Ogino
Takumi Mizukawa
Yuichi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4630578A priority Critical patent/JPS54137952A/en
Publication of JPS54137952A publication Critical patent/JPS54137952A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE: To obtain a narrow pulse delayed by a simple constitution, by a CR charging circuit composed of a couple of CMOS gate circuits with the same function.
CONSTITUTION: The 1st gate circuit B inverts a boundle of inputs and the 2nd gate circuit A uses respective inputs separately. As a result, threshold level X of gate A becomes a little bit lower than threshold level Y of gate B under the influence of the resistance division of a CMOS. Voltage (b) can therefore be obtained which decreases gradually through the charging of the CR circuit when a H-level signal is inputted to input terminal (a). Since inputs of gates A and B are both connected to voltage (b), the potential of gate B is inverted at Y first and that of gate A is inverted at X. In consequence, a pulse can be outputted which is equivalent to the time width depending upon the difference between threshold levels X and Y. In addition, the output corresponding to a step input is delayed as long as the time for a decrease down to threshold level Y.
COPYRIGHT: (C)1979,JPO&Japio
JP4630578A 1978-04-18 1978-04-18 Delay pulse generating circuit Pending JPS54137952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4630578A JPS54137952A (en) 1978-04-18 1978-04-18 Delay pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4630578A JPS54137952A (en) 1978-04-18 1978-04-18 Delay pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS54137952A true JPS54137952A (en) 1979-10-26

Family

ID=12743473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4630578A Pending JPS54137952A (en) 1978-04-18 1978-04-18 Delay pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS54137952A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131367A (en) * 1973-04-18 1974-12-17
JPS5047554A (en) * 1973-08-28 1975-04-28

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131367A (en) * 1973-04-18 1974-12-17
JPS5047554A (en) * 1973-08-28 1975-04-28

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