JPS60190020A - Cmos integrated circuit device - Google Patents
Cmos integrated circuit deviceInfo
- Publication number
- JPS60190020A JPS60190020A JP59045471A JP4547184A JPS60190020A JP S60190020 A JPS60190020 A JP S60190020A JP 59045471 A JP59045471 A JP 59045471A JP 4547184 A JP4547184 A JP 4547184A JP S60190020 A JPS60190020 A JP S60190020A
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- Prior art keywords
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- output
- circuit
- bit
- data
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
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- Tests Of Electronic Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、ＣＭＯ８集積回路装置に係り、特に負荷波動
能力の大きい出力回路を有する高速のＣＭＯ８集積回路
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a CMO8 integrated circuit device, and particularly to a high-speed CMO8 integrated circuit device having an output circuit with a large load wave capability.
０Ｍ０８回路は、定常状態では電源電流が流れないが、
出力レベルが変化するときに配線やゲート入力などの寄
生容量を充放電するための電流が流れる。この電流は負
荷駆動能力の大きな回路はど多く流れ、高速な回路はど
電流の立上りが速くピーク値が大きくなる。In the 0M08 circuit, no power supply current flows in the steady state, but
When the output level changes, current flows to charge and discharge parasitic capacitances such as wiring and gate inputs. A large amount of this current flows in a circuit with a large load driving capacity, and a high-speed circuit causes a rapid current rise and a large peak value.
このような特性をもってＣＭＯ８集積回路装置（ＬＳＩ
）の出力回路が同時に切換わると、ＬＳＩ全体の電源電
流のピーク値は、出力回路数に比例して大きくなり、電
源配線の抵抗やインダクタンイを通じて他の信号にノイ
ズを与え、装置の誤動作を招く原因となっている。この
ため、従来は出力回路の信号切替え時の誤動作を防止す
るためつどのような対策を行なっていた。With these characteristics, CMO8 integrated circuit device (LSI)
) switch at the same time, the peak value of the power supply current for the entire LSI increases in proportion to the number of output circuits, which causes noise to other signals through the resistance and inductance of the power supply wiring, causing equipment malfunction. It is the cause of the invitation. For this reason, conventional measures have been taken to prevent malfunctions when switching signals in the output circuit.
（１）誤動作を生じるような大きなノイズが発生しない
ように電ｇ電流のピーク値をおさえるため。(1) To suppress the peak value of electric current so as not to generate large noise that may cause malfunction.
出力回路のトランジスタの大きさを小さくする。Reduce the size of the transistor in the output circuit.
（２）ＬＳＩ内の電源配線のインピーダンスを小さくす
るため、電源ビン数を増加し、かつ電源配線幅を広くす
る。(2) In order to reduce the impedance of the power supply wiring within the LSI, increase the number of power supply bins and widen the width of the power supply wiring.
（３）出力回路の負荷容量を小さくする。(3) Reduce the load capacity of the output circuit.
（４）電源配線のインピーダンスを小さくするため、Ｌ
ＳＩを実装する基板の電源配風を強化する。(4) To reduce the impedance of power supply wiring,
Strengthen the power distribution of the board on which the SI is mounted.
しかし、（１）の方法では負荷駆動能力が低くなり、Ｔ
Ｔ Ｌ回路の負荷を接続するとファンアウト数を大き
くできない。（２）の方法では信号ピン数が減少し、Ｌ
、ＳＩのチップ面積が大きくなる。However, with method (1), the load driving ability becomes low and T
If a TL circuit load is connected, the fan-out number cannot be increased. In method (2), the number of signal pins is reduced and L
, the chip area of SI increases.
（３）の方法は論理設計上の制約となり、（４）は基板
実装上の制約となっている。Method (3) is a constraint on logical design, and method (4) is a constraint on board mounting.
本発明の目的は、負荷駆動能力の大きい出力回路を有し
、同一タイミングで切換わる出力信号の本数が多いＣＭ
ＯＳ集積回路装置において、ＬＳＩチップ面積の増大
を招くことなく、また負荷容量および基板実装上の制限
をすることなく、出力信号切換え時の電源電流のピーク
値を小さくして。An object of the present invention is to provide a CM that has an output circuit with a large load driving capacity and that has a large number of output signals that switch at the same timing.
To reduce the peak value of power supply current when switching output signals in an OS integrated circuit device without increasing the LSI chip area or limiting load capacity or board mounting.
装置の誤動作をひきおこすようなノイズをおさえるＣＭ
Ｏ８集積回路装置を提供することにある。A commercial that suppresses noise that can cause equipment malfunctions.
An object of the present invention is to provide an O8 integrated circuit device.
（発明の概要）
本発明は、上記目的を達成するために、ａ数本の出力信
号の切換えタイミングを、数本の信号線束ごとに一定時
間ずつ遅らせることによって、信号切換え時に生じる電
源ノイズのピーク値を減少せしめたものである。(Summary of the Invention) In order to achieve the above object, the present invention delays the switching timing of a number of output signals by a certain period of time for each of several signal line bundles, thereby reducing the peak of power supply noise that occurs when switching signals. The value has been decreased.
以下、本発明の詳細な説明する。第１図に音声認識用Ｃ
Ｎ０５ＬＳＩ回路を示す。これは、音声の標準パターン
が蓄えられている標準パターンメモリのアドレスをある
シーケンスに従って計算する機能を有する。図で、ＩＮ
Ｉ〜ＩＮ４は入力ピン、ＯＵＴは出力ビンであり、ＤＩ
ＲおよびＭＡＲはクロックＧＫの立上りでデータＤをラ
ッチするＤタイプフリッププロップ、ＭＵＸはセレクト
人力ＳによってデータＡ、Ｂのいずれかを選択するマル
チプレクサ、ＩＮＧはインフレメンタ、ＴＩＮはタイミ
ング発生回路、ＩＮＶはインバータ、ＣＫＤＲＶはクロ
ックドライブ用のＮ Ａ、 Ｎ Ｄゲート、０ＵＴＤＲ
Ｖはインバータの論理機能を持つＣＭＯＳ出力回路を示
す。The present invention will be explained in detail below. Figure 1 shows C for speech recognition.
The N05LSI circuit is shown. This has the function of calculating the address of a standard pattern memory in which standard patterns of speech are stored according to a certain sequence. In the figure, IN
I~IN4 are input pins, OUT is an output bin, and DI
R and MAR are D-type flip-props that latch data D at the rising edge of clock GK, MUX is a multiplexer that selects either data A or B by the selector S, ING is an inflator, TIN is a timing generation circuit, and INV is a Inverter, CKDRV is NA, ND gate for clock drive, 0UTDR
V indicates a CMOS output circuit having the logic function of an inverter.
第１図の回路で、音声の標準パターンメモリのアドレス
計算はつどのように行なわれる。In the circuit of FIG. 1, address calculations for the standard speech pattern memory are carried out each time.
（１）上位計算機からＤＡＴＡ線を通じて転送されてく
るメモリの初期アクセスアドレスｎをＩＣＫによってＤ
ＩＲに取り込む。(1) The initial access address n of the memory transferred from the host computer through the DATA line is D by ICK.
Incorporate into IR.
（２）メモリのアクセス命令が上位計算機からＣＮＴに
発せられると、回路はＭ Ａ Ｒにまずｎをラッチする
。このとき、ＴＴＭの出力Ｓｌは＃ １１７レベルで、
Ｍ Ｕ ＸはデータＢを選択し、ＩＮＣは＋１が禁止さ
れる。(2) When a memory access command is issued from the host computer to the CNT, the circuit first latches n in MAR. At this time, the TTM output Sl is at #117 level,
MUX selects data B, and INC is prohibited from +1.
（３）つづいてＳｌはＩＩ Ｏｌｊレベルとなり、４０
０ｎ １ｌｌｅｃごとに発せられるＯＣＫによって、Ｍ
ＡＲの出力はｎからｎ ＋ｌ ＋ ｎ ＋ ２ ＋・・
・・・・と変化し、それが出力回′１４！ｒＯＵＴＤＲ
Ｖを経てＯＵＴピンに出力され、さらにメモリアドレス
端子に印加される。(3) Next, Sl becomes II Olj level, 40
By OCK issued every 0n 1llec, M
The output of AR is from n to n + l + n + 2 +...
...and that is the output time '14! rOUTDR
It is output to the OUT pin via V, and is further applied to the memory address terminal.
（４）ある一連の標準パターンのアクセスが終了すると
、ＭＡＲには再びｎがラッチされ、以下（３）と同様に
ｎからｎ＋１．ｎ＋２．・・・・・・の番地がアクセス
される。(4) When the access for a certain series of standard patterns is completed, n is latched in the MAR again, and in the same manner as in (3) below, from n to n+1. n+2. The address of ... is accessed.
ところで、標準パターンメモリも、音声認識用上位計算
機のメモリ空間の一部として扱う場合、そのアドレスビ
ット数は第１図に示すように２０ビツト（ＩＭＷ）にな
る。したがって、標準パターンメモリのアドレス計算時
に、アドレス値りがＩＮＣによって７ＦＦＦＦ （１６
進表示）から８００００ （１６進表示）に変化したと
きは、０ＵＴＤＲＶに入力されるデータはＣＫのタイミ
ングで２０ビツトａｔ Ｉ ＩＩ→１／ ＯＩＩまたは
／ｌ Ｏ７７→ＩＩ １４７レベルに同時に切り換わる
。ここで２０個の出力回路０ＵＴＤＲＶおよび電源には
ピーク値の大きな同時切換電流が瞬時に流れ、それが１
ａ源配線の抵抗やインダクタンスを通じて他の（Ｌ：ｉ
”３にノイズを与え、装置の誤動作を招く。By the way, if the standard pattern memory is also treated as part of the memory space of the host computer for speech recognition, the number of address bits will be 20 bits (IMW) as shown in FIG. Therefore, when calculating the standard pattern memory address, the address value is 7FFFF (16
When the level changes from 80000 (in hexadecimal) to 80000 (in hexadecimal), the data input to 0UTDRV simultaneously switches to the 20-bit at I II → 1/OII or /1 O77 → II 147 level at the CK timing. Here, simultaneous switching currents with large peak values flow instantaneously through the 20 output circuits 0UTDRV and the power supply, and
through the resistance and inductance of the a source wiring (L:i
``It causes noise to the device and causes malfunction of the device.
第２図に、第１図の破線内の回路を対象とした本発明の
実施例を示す。ここでは第１図に示した２０本のデータ
線りを６ビツトのＤｌ、７ビツ１−のＤ２．Ｄ３に分割
し、ＤＩはＣＫのタイミングでＭＡＲｌにラッチし、Ｄ
２はＣＫよりもインバータＩＮＶ２段の遅延時間（約５
ｎ ５ｅｃ）だけ遅れたクロックＧＫ２でＭＡＲ２に
ランチし、Ｄ３はＣＫ２よりもＩＮＶ２段の遅延時間Ｃ
３ｎｓｅｃ）だけ遅れたクロックＣＫ３でＭ Ａ、 Ｒ
，３にラッチする。したがって出力回路は、（：にのタ
イミングで６個（ＯＵＴＤＩい口）、それより少し近れ
たＣＫ２のタイミングで７個（ＯＵＴＤＲＶ２）、さら
に少し遅れてＣ，Ｋ ３のタイミングで７個（ＯＵＴＤ
ＲＶ３）が順次に切り換わって行く。FIG. 2 shows an embodiment of the present invention targeted at the circuit within the broken line in FIG. Here, the 20 data lines shown in FIG. 1 are connected to 6-bit Dl, 7-bit 1-D2, . D3, DI is latched to MARl at CK timing, and D
2 is the delay time of the two stages of inverter INV (approximately 5
Launches to MAR2 with clock GK2 delayed by n 5ec), and D3 has delay time C of INV2 stage than CK2.
M A, R with clock CK3 delayed by 3 nsec)
,3. Therefore, there are 6 output circuits (OUTDI) at the timing of (:), 7 outputs (OUTDRV2) at the slightly closer timing of CK2 (OUTDRV2), and 7 output circuits (OUTDRV2) at the timing of C, K3 a little later.
RV3) are sequentially switched.
２μｍ程度のプロセスを用いた０ＭＯ８ＬＳＩでは、出
力回路切換時に電源電流に生じるピーク電流（ノイズ）
の半値幅は、負荷容量を３０ＰＦとしたとき３〜５ｎｓ
ｅｃであるから、実施例によれば、２０ビツトのデータ
の切換時に出方回路および電源に生じるピーク電流の大
きさは、第１図の場合に比べて７／２０程度におさえる
ことができ、出力回路の同時切換に起因するノイズによ
る装置の誤動作を避けることができる。この様子を第３
図に示す、第３図のＣＫ、ＣＫ２．ＣＫ３のタイミング
は第２図で説明したものであり、電源電圧Ｖｃｃの波形
で、破線は２０ビツトの出力回路がＧＫのタイミングで
同時に切り換わったときの第１図の回路におけるノイズ
波形、実線は本発明によりノイズのピーク値を低減した
第２図の場合の波形を示してる。In 0MO8LSI using a process of about 2μm, the peak current (noise) that occurs in the power supply current when switching the output circuit
The half-value width of is 3 to 5 ns when the load capacity is 30PF.
ec, according to the embodiment, the magnitude of the peak current generated in the output circuit and power supply when switching 20 bits of data can be suppressed to about 7/20 of that in the case of FIG. Malfunction of the device due to noise caused by simultaneous switching of output circuits can be avoided. This situation can be seen in the third
CK, CK2. The timing of CK3 is as explained in Fig. 2, and the waveform of the power supply voltage Vcc is shown.The broken line is the noise waveform in the circuit shown in Fig. 1 when the 20-bit output circuit switches simultaneously at the timing of GK, and the solid line is the waveform of the power supply voltage Vcc. The waveform in the case of FIG. 2 in which the peak value of noise is reduced by the present invention is shown.
第２図ではＤを６ビツト（ＤＩ）、７ビツト（Ｄ２）お
よび７ビツト（Ｄ３）と３分割したが、Ｄを５ビツトず
つ４分割すれば、同時にデータが変化したときのノイズ
の大きさは第１図と比べて５／２０程度に減少できる。In Figure 2, D is divided into three parts: 6 bits (DI), 7 bits (D2), and 7 bits (D3), but if D is divided into four parts of 5 bits each, the amount of noise when data changes simultaneously can be reduced. can be reduced to about 5/20 compared to FIG.
第４図に本発明の別な実施例を示す。ここではＭＡＲの
ＧＫは共通として、ＭＡＲの出力データ線に遅延回路を
挿入することによって、データが同時に切り換わったと
きの電源ノイズを低減するという、第２図の実施例と同
様の効果を得ている。FIG. 4 shows another embodiment of the invention. Here, the GK of the MARs is common, and by inserting a delay circuit in the output data line of the MARs, the same effect as the embodiment shown in Fig. 2 is obtained, in which power supply noise is reduced when data is switched simultaneously. ing.
さらに本発明の別な実施例を示す。第５図はデータの出
力形態が３ステートの場合で、出力制御信号ＯＥがＩＩ
Ｏｙルベルのとき１６ビツトのＤがＬＳＩから入出力
ピンＩＯに出力される。ＯＥが“１”レベルのときには
出力がハイインピーダンスとなり、ＩＯピンから１６ビ
ツトのＤＢＵＳのデータがＬＳＩに入力される。第６図
は、第５図破線内の３ステ一ト回路ＯＵＴの詳細である
。これは、第５図のＤおよびＤＢＵＳ １ビツトあたり
の図で、ｄはＤのうちの１ビツト、ｄｂｕｓはＤＢＵＳ
の１ビツト、ＩＮＶはインバータ。Furthermore, another embodiment of the present invention will be shown. Figure 5 shows the case where the data output form is 3 states, and the output control signal OE is II.
When Oy level, 16 bits D is output from the LSI to the input/output pin IO. When OE is at the "1" level, the output becomes high impedance, and 16-bit DBUS data is input to the LSI from the IO pin. FIG. 6 shows details of the three-state circuit OUT within the broken line in FIG. This is a diagram per 1 bit of D and DBUS in Figure 5, where d is 1 bit of D and dbus is DBUS
1 bit, INV is the inverter.
ＮＡＮＤはＮＡＮＤゲト、ＮＯＲはＮＯＲゲート、破線
で囲んだ０ＵＴＤＲＶは、ＰチャンネルＭＯＳトランジ
スタ（Ｐ−ＭＯＳ）およびＮチャンネルＭＯＳトランジ
スタ（Ｎ−ＭＯＳ）がら構成されるＣＭＯＳ出力回路で
ある。ＶＤＤ 、 Ｖｓｓは電源。NAND is a NAND gate, NOR is a NOR gate, and 0UTDRV surrounded by a broken line is a CMOS output circuit composed of a P-channel MOS transistor (P-MOS) and an N-channel MOS transistor (N-MOS). VDD and Vss are power supplies.
ＣＬは負荷容量および寄生容量を示す。この回路では、
出力制御信号ＯＥがＩｔ １７ルベルのときＰ−ＭＯＳ
およびＮ−ＭＯＳすなわち出力回路０ＵＴＤＲＶはオフ
状態で、ｄｂｕｓはハイインピーダンスであり、ＯＥが
ＩＩ ＯＩｔになるとｄに応じてＰ−ＭＯＳ、Ｎ−ＭＯ
Ｓのどちらか一方がオンしてｄｂｕｓにｄの値が出力さ
れるにのとき、出力回路０ＵＴＤＲＶにはＣＬを充放電
するための電流が流れる。CL indicates load capacitance and parasitic capacitance. In this circuit,
P-MOS when output control signal OE is It17 level
and N-MOS, that is, the output circuit 0UTDRV is in the off state, dbus is high impedance, and when OE becomes II OIt, P-MOS, N-MO
When either one of S is turned on and the value of d is output to dbus, a current for charging and discharging CL flows through the output circuit 0UTDRV.
さて、第５図ではＯＥが′０″となった瞬時、１６個の
０ＵＴＤＲＶがハイインピーダンスから同時にＤのレベ
ルに切換わり、第１図で説明したのと同様にノイズが発
生した装置の誤動作を招く。Now, in Figure 5, at the instant when OE becomes '0'', 16 0UTDRVs simultaneously switch from high impedance to D level, which causes a malfunction of the device that generates noise in the same way as explained in Figure 1. invite
第シ図に、第５図の破線内の回路を対象とした本発明の
実施例を示す。ここでは第５図の１６本のデータＤを６
ビツトのＤＩ、５ビツトのＤ２゜Ｄ３に分割し、Ｄｌは
ＯＥのタイミングで出力回路０ＵＴＤＲＶに入力し、Ｄ
２はＯＥよりもインバータ２段の遅延時間（約５ｎｓ）
だけ遅れたＯ Ｅ’ ２ テＯＵ Ｔ Ｄ ＲＶ ニ入
力し、Ｄ３はＯＥ２よりもインバータ２段の遅延時間（
約５ｎｓ）だけ遅れたＯＥ３で０ＵＴＤＲＶに入力する
。したがって、出力回路はＯＥのタイミングで６個（Ｏ
ＵＴＩ）、そ才しよりも５ｎｓ遅れたＯＥ２のタイミン
グで５個（ＯＵＴ２）、さらに５ｎｓ遅れたＯＥ３で５
個（ＯＵＴ３）が順次スイッチングしてゆく。この結果
、第３図と同様にノイズのピーク値を低減することがで
きる。FIG. 5 shows an embodiment of the present invention targeting the circuit within the broken line in FIG. Here, the 16 pieces of data D in Figure 5 are
Divided into DI of bit, D2 and D3 of 5 bits, Dl is input to output circuit 0UTDRV at the timing of OE,
2 is the delay time of the 2nd stage of inverter (approx. 5ns) compared to OE.
OE' 2 TE OUT D RV 2 is inputted with a delay of
OE3 is input to 0UTDRV with a delay of approximately 5 ns). Therefore, there are six output circuits (O
UTI), 5 at the timing of OE2 (OUT2), which was 5 ns later than that, and 5 at OE3, which was further delayed by 5 ns.
(OUT3) are sequentially switched. As a result, the peak value of noise can be reduced as in FIG. 3.
本発明によれば、負荷駆動能力の大きい出力回路を有す
る高速のＣＭＯＳ集積回路装置で、同一タイミングで切
り換わる出力信号の本数が多い装置において。According to the present invention, in a high-speed CMOS integrated circuit device having an output circuit with a large load driving capacity, and in which a large number of output signals are switched at the same timing.
（１）出力回路の負荷駆動能力をそこなわず、（２）Ｌ
ＳＩ内の電源配線強化のためのチップ面積の増加および
信号ピン数の減少をまねくことなく、
（３）基板の電源配線を強化するという実装上の制約も
なく、
出力回路同時切換時の電源ノイズによる装置の誤動作を
回避することができ、（２）、（３）に係り廉価で、（
１）に係り高性能で、耐雑音性の面で信頼性の高いＣＭ
Ｏ５集積回路装置を提供することができる。(1) Do not damage the load driving ability of the output circuit; (2) L
without increasing the chip area or reducing the number of signal pins to strengthen the power supply wiring within the SI, (3) without mounting constraints such as strengthening the power supply wiring on the board, and reducing power supply noise when switching output circuits simultaneously. It is possible to avoid malfunction of the device due to
1) A CM with high performance and high reliability in terms of noise resistance.
An O5 integrated circuit device can be provided.
第１図および第２図は、本発明の実施例の回路構成を示
す図、第３図は第２図のタイムチャート、第４図は本発
明の他の実施例の回Ｓ構成を示す図、第５図、第６図お
よび第７図は本発明の別な実施例の回路を示す図である
。
ＭＡＲ，ＭＡＲＩ〜ＭＡＲ３・・・Ｄタイプフリップフ
ロップで構成されるメモリアドレスレジスタ。
０ＵＴＤＲＶ、０ＵＴＤＲＶＩ〜０ＵＴＤＲＶ３・・・
ｃ’ｙｏｓ出力回路、ＩＮＶ・・・インバータ、ＯＵＴ
、０ＵＴＩ 〜ＯＵＴ３−ＣＭＯ８出力回路第 １ 目
ｌＮ４
第 ３ 日
第１頁の続き
［相］発 明 者 石 川 克 文 日立重大み、ルシ
ステム
［相］発 明 者 大 沼 邦 彦 日立重大み；か工
場内
５＝町５丁目２番１号 株式会社日立コントロース゛内1 and 2 are diagrams showing the circuit configuration of an embodiment of the present invention, FIG. 3 is a time chart of FIG. 2, and FIG. 4 is a diagram showing the circuit configuration of another embodiment of the present invention. , FIG. 5, FIG. 6, and FIG. 7 are diagrams showing circuits of other embodiments of the present invention. MAR, MARI to MAR3...Memory address registers composed of D-type flip-flops. 0UTDRV, 0UTDRVI~0UTDRV3...
c'yos output circuit, INV...inverter, OUT
, 0UTI ~ OUT3-CMO8 output circuit 1st page lN4 3rd day, page 1 continuation [Phase] Inventor Katsu Ishikawa Written by Seiji Hitachi, System [Phase] Inventor Kunihiko Ohnuma Seiji Hitachi; Inside the factory 5 = 5-2-1 Town Hitachi Controls Co., Ltd.
Claims (1)
個の出力回路を備え、該出力回路への複数ビットの入力
データが同一タイミングで変化するＣＭＯ８集積回路装
置において、該出力回路へのデータの入力タイミングを
数ビットのデータごとに遅延させる手段を設けたことを
特徴とするＣＭＯ８集積回路装置。(2) In a CMO8 integrated circuit device that is equipped with a plurality of output circuits that output multiple bits of data to the outside of the device, and in which multiple bits of input data to the output circuit change at the same timing, the data to the output circuit is A CMO8 integrated circuit device, characterized in that it is provided with means for delaying the input timing of every several bits of data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59045471A JPS60190020A (en) | 1984-03-12 | 1984-03-12 | Cmos integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59045471A JPS60190020A (en) | 1984-03-12 | 1984-03-12 | Cmos integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60190020A true JPS60190020A (en) | 1985-09-27 |
Family
ID=12720300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59045471A Pending JPS60190020A (en) | 1984-03-12 | 1984-03-12 | Cmos integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60190020A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5073730A (en) * | 1990-04-23 | 1991-12-17 | International Business Machines Corporation | Current transient reduction for vlsi chips |
| US5229657A (en) * | 1991-05-01 | 1993-07-20 | Vlsi Technology, Inc. | Method and apparatus for controlling simultaneous switching output noise in boundary scan paths |
| WO2003071681A1 (en) * | 2002-02-21 | 2003-08-28 | Koninklijke Philips Electronics N.V. | Integrated circuit having reduced substrate bounce |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS539439A (en) * | 1976-07-14 | 1978-01-27 | Hitachi Ltd | Information gate system |
| JPS57168319A (en) * | 1981-04-09 | 1982-10-16 | Fujitsu Ltd | Parallel output buffer circuit |
-
1984
- 1984-03-12 JP JP59045471A patent/JPS60190020A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS539439A (en) * | 1976-07-14 | 1978-01-27 | Hitachi Ltd | Information gate system |
| JPS57168319A (en) * | 1981-04-09 | 1982-10-16 | Fujitsu Ltd | Parallel output buffer circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5073730A (en) * | 1990-04-23 | 1991-12-17 | International Business Machines Corporation | Current transient reduction for vlsi chips |
| US5229657A (en) * | 1991-05-01 | 1993-07-20 | Vlsi Technology, Inc. | Method and apparatus for controlling simultaneous switching output noise in boundary scan paths |
| WO2003071681A1 (en) * | 2002-02-21 | 2003-08-28 | Koninklijke Philips Electronics N.V. | Integrated circuit having reduced substrate bounce |
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