JPS56143067A - Multiprocessor control system - Google Patents

Multiprocessor control system

Info

Publication number
JPS56143067A
JPS56143067A JP4412580A JP4412580A JPS56143067A JP S56143067 A JPS56143067 A JP S56143067A JP 4412580 A JP4412580 A JP 4412580A JP 4412580 A JP4412580 A JP 4412580A JP S56143067 A JPS56143067 A JP S56143067A
Authority
JP
Japan
Prior art keywords
devices
operation mode
common
cps
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4412580A
Other languages
Japanese (ja)
Other versions
JPS5831020B2 (en
Inventor
Masato Suyama
Kazuyuki Masuo
Takaharu Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP55044125A priority Critical patent/JPS5831020B2/en
Publication of JPS56143067A publication Critical patent/JPS56143067A/en
Publication of JPS5831020B2 publication Critical patent/JPS5831020B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To prevent destruction of contents of a common device due to PC being in failure, by providing a plurality of control processors CPs and a duplex common device accessible commonly from said CPs with an operation mode memory means respectively for processing. CONSTITUTION:Means MC0, MC1, MP0-MPn storing the operating mode which indicates whether duplicated common memory devices 11, 12 must be operated in synchronism of both the systems or individually operated, are provided in the devices 11, 12 and CP0-CPn. If, CP0, for example, accesses to the devices 10, 11, the control signals like address and the like are added with the operation mode set to the means MC0 of the device itself and transmitted to the signal line 140. In the devices 11, 12, the control circuits CTL0, CTL1 collate the content of MC0, MC1 in the device of itself with the operation mode fed from CP0, and if they are in agreement, the access request is received, and if in disagreement, the disagreement signal is fed to CP0. Thus, if the devices 11, 12 are in synchronous operation, and even if CP in failure accesses in separation mode, the destruction of contents of the common device is avoided.
JP55044125A 1980-04-04 1980-04-04 multiprocessor control system Expired JPS5831020B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55044125A JPS5831020B2 (en) 1980-04-04 1980-04-04 multiprocessor control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55044125A JPS5831020B2 (en) 1980-04-04 1980-04-04 multiprocessor control system

Publications (2)

Publication Number Publication Date
JPS56143067A true JPS56143067A (en) 1981-11-07
JPS5831020B2 JPS5831020B2 (en) 1983-07-02

Family

ID=12682875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55044125A Expired JPS5831020B2 (en) 1980-04-04 1980-04-04 multiprocessor control system

Country Status (1)

Country Link
JP (1) JPS5831020B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01155440A (en) * 1987-12-14 1989-06-19 Hitachi Ltd System for testing computer system
JP2014095989A (en) * 2012-11-08 2014-05-22 Nec Corp Computer system, and diagnostic method and diagnostic program for computer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01155440A (en) * 1987-12-14 1989-06-19 Hitachi Ltd System for testing computer system
JP2014095989A (en) * 2012-11-08 2014-05-22 Nec Corp Computer system, and diagnostic method and diagnostic program for computer system

Also Published As

Publication number Publication date
JPS5831020B2 (en) 1983-07-02

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