JPS5733498A - Control system of main storage - Google Patents

Control system of main storage

Info

Publication number
JPS5733498A
JPS5733498A JP10764580A JP10764580A JPS5733498A JP S5733498 A JPS5733498 A JP S5733498A JP 10764580 A JP10764580 A JP 10764580A JP 10764580 A JP10764580 A JP 10764580A JP S5733498 A JPS5733498 A JP S5733498A
Authority
JP
Japan
Prior art keywords
error
main storage
signal
controller
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10764580A
Other languages
Japanese (ja)
Inventor
Yasushi Fukunaga
Tadaaki Bando
Tetsuya Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP10764580A priority Critical patent/JPS5733498A/en
Publication of JPS5733498A publication Critical patent/JPS5733498A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To simplify the memory eror processing function, by processing only the error that cannot be recovered by a reaccess through a controller that gave an access to a processor or other memories. CONSTITUTION:A main storage controller 26 is initialized by a memory start request signal 34 and monitors an address overerror signal 35 and a protection error signal 36. In case either one of these two signals has an error, the controller 26 carries out an error retry control. When no error exists, a main storage start signal 38 is delivered. Then the contents of an address register 21 and a write data register 22 are sent to the main storage via a buffer 30 when a function register 23 shows the writing action.
JP10764580A 1980-08-07 1980-08-07 Control system of main storage Pending JPS5733498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10764580A JPS5733498A (en) 1980-08-07 1980-08-07 Control system of main storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10764580A JPS5733498A (en) 1980-08-07 1980-08-07 Control system of main storage

Publications (1)

Publication Number Publication Date
JPS5733498A true JPS5733498A (en) 1982-02-23

Family

ID=14464433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10764580A Pending JPS5733498A (en) 1980-08-07 1980-08-07 Control system of main storage

Country Status (1)

Country Link
JP (1) JPS5733498A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5390731A (en) * 1977-01-21 1978-08-09 Nec Corp Control circuit for memory unit
JPS5532230A (en) * 1978-08-25 1980-03-06 Nec Corp Memory unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5390731A (en) * 1977-01-21 1978-08-09 Nec Corp Control circuit for memory unit
JPS5532230A (en) * 1978-08-25 1980-03-06 Nec Corp Memory unit

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