JPS6415853A - Memory access processing system - Google Patents
Memory access processing systemInfo
- Publication number
- JPS6415853A JPS6415853A JP17193487A JP17193487A JPS6415853A JP S6415853 A JPS6415853 A JP S6415853A JP 17193487 A JP17193487 A JP 17193487A JP 17193487 A JP17193487 A JP 17193487A JP S6415853 A JPS6415853 A JP S6415853A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- circuit
- processing system
- memory access
- access request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To improve the memory access efficiency without increasing the bus width, etc., by using a continuous access request production circuit where each adaptor of a memory access processing system produces the continuous access signals in accordance with the storing state of the transferred data in a buffer. CONSTITUTION:The adaptors 20-0 and 20-1 of a memory access processing system are actuated based on the information received from the host controllers 10-0 and 10-1 through the control interfaces 1 and 2. A buffer control circuit 22 of each of both adaptors 20-0 and 20-1 reads data out of an address by the prescribed number of bytes and stores it into a memory address register 23. At the same time, the information on the idle state of a buffer 21 is sent to a request production circuit 24 and a continuous access request production circuit 25. The circuit 25 transmits an access request signal 4 when the buffer 21 has an idle space of just a single byte. Then the continuous access request signals 8 are transmitted from the circuit 25 when the buffer has an idle space of 3 bytes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17193487A JPS6415853A (en) | 1987-07-09 | 1987-07-09 | Memory access processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17193487A JPS6415853A (en) | 1987-07-09 | 1987-07-09 | Memory access processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6415853A true JPS6415853A (en) | 1989-01-19 |
Family
ID=15932538
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17193487A Pending JPS6415853A (en) | 1987-07-09 | 1987-07-09 | Memory access processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6415853A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0460748A (en) * | 1990-06-28 | 1992-02-26 | Nec Corp | Processor extension system |
US6606701B1 (en) | 1998-11-30 | 2003-08-12 | Nec Electronics Corporation | Micro-processor |
-
1987
- 1987-07-09 JP JP17193487A patent/JPS6415853A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0460748A (en) * | 1990-06-28 | 1992-02-26 | Nec Corp | Processor extension system |
US6606701B1 (en) | 1998-11-30 | 2003-08-12 | Nec Electronics Corporation | Micro-processor |
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